From: Nicholas Piggin <npiggin@gmail.com>
To: qemu-ppc@nongnu.org
Cc: "Daniel Henrique Barboza" <danielhb413@gmail.com>,
"Fabiano Rosas" <farosas@linux.ibm.com>,
qemu-devel@nongnu.org, "Nicholas Piggin" <npiggin@gmail.com>,
"Cédric Le Goater" <clg@kaod.org>
Subject: [PATCH v2 7/9] target/ppc: Add powerpc_reset_excp_state helper
Date: Wed, 16 Feb 2022 20:25:43 +1000 [thread overview]
Message-ID: <20220216102545.1808018-8-npiggin@gmail.com> (raw)
In-Reply-To: <20220216102545.1808018-1-npiggin@gmail.com>
This moves the logic to reset the QEMU exception state into its own
function.
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
target/ppc/excp_helper.c | 41 ++++++++++++++++++++--------------------
1 file changed, 21 insertions(+), 20 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 6b6ec71bc2..778eb4f3b0 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -360,12 +360,20 @@ static void ppc_excp_apply_ail(PowerPCCPU *cpu, int excp, target_ulong msr,
}
#endif
-static void powerpc_set_excp_state(PowerPCCPU *cpu,
- target_ulong vector, target_ulong msr)
+static void powerpc_reset_excp_state(PowerPCCPU *cpu)
{
CPUState *cs = CPU(cpu);
CPUPPCState *env = &cpu->env;
+ /* Reset exception state */
+ cs->exception_index = POWERPC_EXCP_NONE;
+ env->error_code = 0;
+}
+
+static void powerpc_set_excp_state(PowerPCCPU *cpu, target_ulong vector, target_ulong msr)
+{
+ CPUPPCState *env = &cpu->env;
+
assert((msr & env->msr_mask) == msr);
/*
@@ -376,21 +384,20 @@ static void powerpc_set_excp_state(PowerPCCPU *cpu,
* will prevent setting of the HV bit which some exceptions might need
* to do.
*/
+ env->nip = vector;
env->msr = msr;
hreg_compute_hflags(env);
- env->nip = vector;
- /* Reset exception state */
- cs->exception_index = POWERPC_EXCP_NONE;
- env->error_code = 0;
- /* Reset the reservation */
- env->reserve_addr = -1;
+ powerpc_reset_excp_state(cpu);
/*
* Any interrupt is context synchronizing, check if TCG TLB needs
* a delayed flush on ppc64
*/
check_tlb_flush(env, false);
+
+ /* Reset the reservation */
+ env->reserve_addr = -1;
}
static void powerpc_excp_40x(PowerPCCPU *cpu, int excp)
@@ -471,8 +478,7 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int excp)
case POWERPC_EXCP_FP:
if ((msr_fe0 == 0 && msr_fe1 == 0) || msr_fp == 0) {
trace_ppc_excp_fp_ignore();
- cs->exception_index = POWERPC_EXCP_NONE;
- env->error_code = 0;
+ powerpc_reset_excp_state(cpu);
return;
}
env->spr[SPR_40x_ESR] = ESR_FP;
@@ -609,8 +615,7 @@ static void powerpc_excp_6xx(PowerPCCPU *cpu, int excp)
case POWERPC_EXCP_FP:
if ((msr_fe0 == 0 && msr_fe1 == 0) || msr_fp == 0) {
trace_ppc_excp_fp_ignore();
- cs->exception_index = POWERPC_EXCP_NONE;
- env->error_code = 0;
+ powerpc_reset_excp_state(cpu);
return;
}
@@ -783,8 +788,7 @@ static void powerpc_excp_7xx(PowerPCCPU *cpu, int excp)
case POWERPC_EXCP_FP:
if ((msr_fe0 == 0 && msr_fe1 == 0) || msr_fp == 0) {
trace_ppc_excp_fp_ignore();
- cs->exception_index = POWERPC_EXCP_NONE;
- env->error_code = 0;
+ powerpc_reset_excp_state(cpu);
return;
}
@@ -969,8 +973,7 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int excp)
case POWERPC_EXCP_FP:
if ((msr_fe0 == 0 && msr_fe1 == 0) || msr_fp == 0) {
trace_ppc_excp_fp_ignore();
- cs->exception_index = POWERPC_EXCP_NONE;
- env->error_code = 0;
+ powerpc_reset_excp_state(cpu);
return;
}
@@ -1168,8 +1171,7 @@ static void powerpc_excp_booke(PowerPCCPU *cpu, int excp)
case POWERPC_EXCP_FP:
if ((msr_fe0 == 0 && msr_fe1 == 0) || msr_fp == 0) {
trace_ppc_excp_fp_ignore();
- cs->exception_index = POWERPC_EXCP_NONE;
- env->error_code = 0;
+ powerpc_reset_excp_state(cpu);
return;
}
@@ -1406,8 +1408,7 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int excp)
case POWERPC_EXCP_FP:
if ((msr_fe0 == 0 && msr_fe1 == 0) || msr_fp == 0) {
trace_ppc_excp_fp_ignore();
- cs->exception_index = POWERPC_EXCP_NONE;
- env->error_code = 0;
+ powerpc_reset_excp_state(cpu);
return;
}
--
2.23.0
next prev parent reply other threads:[~2022-02-16 10:42 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-02-16 10:25 [PATCH v2 0/9] ppc: nested KVM HV for spapr virtual hypervisor Nicholas Piggin
2022-02-16 10:25 ` [PATCH v2 1/9] target/ppc: raise HV interrupts for partition table entry problems Nicholas Piggin
2022-02-16 10:25 ` [PATCH v2 2/9] spapr: prevent hdec timer being set up under virtual hypervisor Nicholas Piggin
2022-02-16 10:25 ` [PATCH v2 3/9] ppc: allow the hdecr timer to be created/destroyed Nicholas Piggin
2022-02-16 10:25 ` [PATCH v2 4/9] target/ppc: add vhyp addressing mode helper for radix MMU Nicholas Piggin
2022-02-16 10:25 ` [PATCH v2 5/9] target/ppc: make vhyp get_pate method take lpid and return success Nicholas Piggin
2022-02-16 10:25 ` [PATCH v2 6/9] target/ppc: add helper for books vhyp hypercall handler Nicholas Piggin
2022-02-16 10:25 ` Nicholas Piggin [this message]
2022-02-16 10:25 ` [PATCH v2 8/9] target/ppc: Introduce a vhyp framework for nested HV support Nicholas Piggin
2022-02-16 10:38 ` Cédric Le Goater
2022-02-16 10:25 ` [PATCH v2 9/9] spapr: implement nested-hv capability for the virtual hypervisor Nicholas Piggin
2022-02-16 10:52 ` Cédric Le Goater
2022-02-16 11:38 ` Nicholas Piggin
2022-02-16 12:30 ` Nicholas Piggin
2022-02-17 17:11 ` Cédric Le Goater
2022-02-18 7:45 ` [PATCH v2 0/9] ppc: nested KVM HV for spapr " Cédric Le Goater
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