From: Bernhard Beschow <shentey@gmail.com>
To: qemu-devel@nongnu.org
Cc: "Hervé Poussineau" <hpoussin@reactos.org>,
"Bernhard Beschow" <shentey@gmail.com>,
"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
"Aurelien Jarno" <aurelien@aurel32.net>
Subject: [PATCH v3 6/7] hw/isa/piix4: Replace some magic IRQ constants
Date: Wed, 16 Feb 2022 23:45:18 +0100 [thread overview]
Message-ID: <20220216224519.157233-7-shentey@gmail.com> (raw)
In-Reply-To: <20220216224519.157233-1-shentey@gmail.com>
This is a follow-up on patch "malta: Move PCI interrupt handling from
gt64xxx_pci to piix4". gt64xxx_pci used magic constants, and probably
didn't want to use piix4-specific constants. Now that the interrupt
handing resides in piix4, its constants can be used.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
---
hw/isa/piix4.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
index 2e9b5ccada..f876c71750 100644
--- a/hw/isa/piix4.c
+++ b/hw/isa/piix4.c
@@ -61,10 +61,10 @@ static void piix4_set_irq(void *opaque, int irq_num, int level)
/* now we change the pic irq level according to the piix irq mappings */
/* XXX: optimize */
pic_irq = s->dev.config[PIIX_PIRQCA + irq_num];
- if (pic_irq < 16) {
+ if (pic_irq < ISA_NUM_IRQS) {
/* The pic level is the logical OR of all the PCI irqs mapped to it. */
pic_level = 0;
- for (i = 0; i < 4; i++) {
+ for (i = 0; i < PIIX_NUM_PIRQS; i++) {
if (pic_irq == s->dev.config[PIIX_PIRQCA + i]) {
pic_level |= pci_bus_get_irq_level(bus, i);
}
@@ -315,7 +315,7 @@ DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus, I2CBus **smbus)
NULL, 0, NULL);
}
- pci_bus_irqs(pci_bus, piix4_set_irq, pci_slot_get_pirq, s, 4);
+ pci_bus_irqs(pci_bus, piix4_set_irq, pci_slot_get_pirq, s, PIIX_NUM_PIRQS);
return dev;
}
--
2.35.1
next prev parent reply other threads:[~2022-02-16 22:52 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-02-16 22:45 [PATCH v3 0/7] malta: Fix PCI IRQ levels to be preserved during migration, cleanup Bernhard Beschow
2022-02-16 22:45 ` [PATCH v3 1/7] hw/mips/gt64xxx_pci: Fix PCI IRQ levels to be preserved during migration Bernhard Beschow
2022-02-17 11:57 ` Peter Maydell
2022-02-16 22:45 ` [PATCH v3 2/7] malta: Move PCI interrupt handling from gt64xxx_pci to piix4 Bernhard Beschow
2022-02-16 23:15 ` Philippe Mathieu-Daudé via
2022-02-16 22:45 ` [PATCH v3 3/7] hw/isa/piix4: Resolve redundant i8259[] attribute Bernhard Beschow
2022-02-16 23:13 ` Philippe Mathieu-Daudé via
2022-02-17 6:34 ` Michael S. Tsirkin
2022-02-16 22:45 ` [PATCH v3 4/7] hw/isa/piix4: Pass PIIX4State as opaque parameter for piix4_set_irq() Bernhard Beschow
2022-02-17 6:34 ` Michael S. Tsirkin
2022-02-16 22:45 ` [PATCH v3 5/7] hw/isa/piix4: Resolve global instance variable Bernhard Beschow
2022-02-17 6:34 ` Michael S. Tsirkin
2022-02-16 22:45 ` Bernhard Beschow [this message]
2022-02-16 23:09 ` [PATCH v3 6/7] hw/isa/piix4: Replace some magic IRQ constants Philippe Mathieu-Daudé via
2022-02-17 6:35 ` Michael S. Tsirkin
2022-02-16 22:45 ` [PATCH v3 7/7] hw/mips/gt64xxx_pci: Resolve gt64120_register() Bernhard Beschow
2022-02-16 23:13 ` Philippe Mathieu-Daudé via
2022-02-17 2:22 ` BALATON Zoltan
2022-02-17 6:36 ` [PATCH v3 0/7] malta: Fix PCI IRQ levels to be preserved during migration, cleanup Michael S. Tsirkin
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