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Tsirkin" To: Bernhard Beschow Subject: Re: [PATCH v3 5/7] hw/isa/piix4: Resolve global instance variable Message-ID: <20220217013418-mutt-send-email-mst@kernel.org> References: <20220216224519.157233-1-shentey@gmail.com> <20220216224519.157233-6-shentey@gmail.com> MIME-Version: 1.0 In-Reply-To: <20220216224519.157233-6-shentey@gmail.com> Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=mst@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=170.10.129.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -28 X-Spam_score: -2.9 X-Spam_bar: -- X-Spam_report: (-2.9 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.083, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?iso-8859-1?Q?Herv=E9?= Poussineau , qemu-devel@nongnu.org, Aurelien Jarno , Philippe =?iso-8859-1?Q?Mathieu-Daud=E9?= Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Wed, Feb 16, 2022 at 11:45:17PM +0100, Bernhard Beschow wrote: > Now that piix4_set_irq's opaque parameter references own PIIX4State, > piix4_dev becomes redundant. > > Signed-off-by: Bernhard Beschow > Reviewed-by: Philippe Mathieu-Daudé Acked-by: Michael S. Tsirkin > --- > hw/isa/piix4.c | 10 +++------- > include/hw/southbridge/piix.h | 2 -- > 2 files changed, 3 insertions(+), 9 deletions(-) > > diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c > index caa2002e2c..2e9b5ccada 100644 > --- a/hw/isa/piix4.c > +++ b/hw/isa/piix4.c > @@ -39,8 +39,6 @@ > #include "sysemu/runstate.h" > #include "qom/object.h" > > -PCIDevice *piix4_dev; > - > struct PIIX4State { > PCIDevice dev; > qemu_irq cpu_intr; > @@ -58,16 +56,16 @@ static void piix4_set_irq(void *opaque, int irq_num, int level) > { > int i, pic_irq, pic_level; > PIIX4State *s = opaque; > - PCIBus *bus = pci_get_bus(piix4_dev); > + PCIBus *bus = pci_get_bus(&s->dev); > > /* now we change the pic irq level according to the piix irq mappings */ > /* XXX: optimize */ > - pic_irq = piix4_dev->config[PIIX_PIRQCA + irq_num]; > + pic_irq = s->dev.config[PIIX_PIRQCA + irq_num]; > if (pic_irq < 16) { > /* The pic level is the logical OR of all the PCI irqs mapped to it. */ > pic_level = 0; > for (i = 0; i < 4; i++) { > - if (pic_irq == piix4_dev->config[PIIX_PIRQCA + i]) { > + if (pic_irq == s->dev.config[PIIX_PIRQCA + i]) { > pic_level |= pci_bus_get_irq_level(bus, i); > } > } > @@ -219,8 +217,6 @@ static void piix4_realize(PCIDevice *dev, Error **errp) > return; > } > isa_init_irq(ISA_DEVICE(&s->rtc), &s->rtc.irq, RTC_ISA_IRQ); > - > - piix4_dev = dev; > } > > static void piix4_init(Object *obj) > diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h > index 6387f2b612..f63f83e5c6 100644 > --- a/include/hw/southbridge/piix.h > +++ b/include/hw/southbridge/piix.h > @@ -70,8 +70,6 @@ typedef struct PIIXState PIIX3State; > DECLARE_INSTANCE_CHECKER(PIIX3State, PIIX3_PCI_DEVICE, > TYPE_PIIX3_PCI_DEVICE) > > -extern PCIDevice *piix4_dev; > - > PIIX3State *piix3_create(PCIBus *pci_bus, ISABus **isa_bus); > > DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus, I2CBus **smbus); > -- > 2.35.1