From: David Miller <dmiller423@gmail.com>
To: qemu-s390x@nongnu.org, qemu-devel@nongnu.org
Cc: thuth@redhat.com, david@redhat.com, cohuck@redhat.com,
richard.henderson@linaro.org, farman@linux.ibm.com,
David Miller <dmiller423@gmail.com>,
pasic@linux.ibm.com, borntraeger@linux.ibm.com
Subject: [PATCH v6 4/4] tests/tcg/s390x: changed to using .insn for tests requiring z15
Date: Thu, 17 Feb 2022 18:17:28 -0500 [thread overview]
Message-ID: <20220217231728.13932-5-dmiller423@gmail.com> (raw)
In-Reply-To: <20220217231728.13932-1-dmiller423@gmail.com>
Signed-off-by: David Miller <dmiller423@gmail.com>
---
tests/tcg/s390x/mie3-compl.c | 21 +++++++++++----------
tests/tcg/s390x/mie3-mvcrl.c | 2 +-
tests/tcg/s390x/mie3-sel.c | 6 +++---
3 files changed, 15 insertions(+), 14 deletions(-)
diff --git a/tests/tcg/s390x/mie3-compl.c b/tests/tcg/s390x/mie3-compl.c
index 98281ee683..31820e4a2a 100644
--- a/tests/tcg/s390x/mie3-compl.c
+++ b/tests/tcg/s390x/mie3-compl.c
@@ -14,25 +14,26 @@
#define FbinOp(S, ASM) uint64_t S(uint64_t a, uint64_t b) \
{ uint64_t res = 0; F_PRO; ASM; return res; }
+
/* AND WITH COMPLEMENT */
-FbinOp(_ncrk, asm("ncrk %%r0, %%r3, %%r2\n" F_EPI))
-FbinOp(_ncgrk, asm("ncgrk %%r0, %%r3, %%r2\n" F_EPI))
+FbinOp(_ncrk, asm(".insn rrf, 0xB9F50000, %%r0, %%r3, %%r2, 0\n" F_EPI))
+FbinOp(_ncgrk, asm(".insn rrf, 0xB9E50000, %%r0, %%r3, %%r2, 0\n" F_EPI))
/* NAND */
-FbinOp(_nnrk, asm("nnrk %%r0, %%r3, %%r2\n" F_EPI))
-FbinOp(_nngrk, asm("nngrk %%r0, %%r3, %%r2\n" F_EPI))
+FbinOp(_nnrk, asm(".insn rrf, 0xB9740000, %%r0, %%r3, %%r2, 0\n" F_EPI))
+FbinOp(_nngrk, asm(".insn rrf, 0xB9640000, %%r0, %%r3, %%r2, 0\n" F_EPI))
/* NOT XOR */
-FbinOp(_nxrk, asm("nxrk %%r0, %%r3, %%r2\n" F_EPI))
-FbinOp(_nxgrk, asm("nxgrk %%r0, %%r3, %%r2\n" F_EPI))
+FbinOp(_nxrk, asm(".insn rrf, 0xB9770000, %%r0, %%r3, %%r2, 0\n" F_EPI))
+FbinOp(_nxgrk, asm(".insn rrf, 0xB9670000, %%r0, %%r3, %%r2, 0\n" F_EPI))
/* NOR */
-FbinOp(_nork, asm("nork %%r0, %%r3, %%r2\n" F_EPI))
-FbinOp(_nogrk, asm("nogrk %%r0, %%r3, %%r2\n" F_EPI))
+FbinOp(_nork, asm(".insn rrf, 0xB9760000, %%r0, %%r3, %%r2, 0\n" F_EPI))
+FbinOp(_nogrk, asm(".insn rrf, 0xB9660000, %%r0, %%r3, %%r2, 0\n" F_EPI))
/* OR WITH COMPLEMENT */
-FbinOp(_ocrk, asm("ocrk %%r0, %%r3, %%r2\n" F_EPI))
-FbinOp(_ocgrk, asm("ocgrk %%r0, %%r3, %%r2\n" F_EPI))
+FbinOp(_ocrk, asm(".insn rrf, 0xB9750000, %%r0, %%r3, %%r2, 0\n" F_EPI))
+FbinOp(_ocgrk, asm(".insn rrf, 0xB9650000, %%r0, %%r3, %%r2, 0\n" F_EPI))
int main(int argc, char *argv[])
diff --git a/tests/tcg/s390x/mie3-mvcrl.c b/tests/tcg/s390x/mie3-mvcrl.c
index 81cf3ad702..f0be83b197 100644
--- a/tests/tcg/s390x/mie3-mvcrl.c
+++ b/tests/tcg/s390x/mie3-mvcrl.c
@@ -6,7 +6,7 @@ static inline void mvcrl_8(const char *dst, const char *src)
{
asm volatile (
"llill %%r0, 8\n"
- "mvcrl 0(%[dst]), 0(%[src])\n"
+ ".insn sse, 0xE50A00000000, 0(%[dst]), 0(%[src])"
: : [dst] "d" (dst), [src] "d" (src)
: "memory");
}
diff --git a/tests/tcg/s390x/mie3-sel.c b/tests/tcg/s390x/mie3-sel.c
index d6b7b0933b..32d434b01a 100644
--- a/tests/tcg/s390x/mie3-sel.c
+++ b/tests/tcg/s390x/mie3-sel.c
@@ -19,9 +19,9 @@
{ uint64_t res = 0; F_PRO ; ASM ; return res; }
-Fi3 (_selre, asm("selre %%r0, %%r3, %%r2\n" F_EPI))
-Fi3 (_selgrz, asm("selgrz %%r0, %%r3, %%r2\n" F_EPI))
-Fi3 (_selfhrnz, asm("selfhrnz %%r0, %%r3, %%r2\n" F_EPI))
+Fi3 (_selre, asm(".insn rrf, 0xB9F00000, %%r0, %%r3, %%r2, 8\n" F_EPI))
+Fi3 (_selgrz, asm(".insn rrf, 0xB9E30000, %%r0, %%r3, %%r2, 8\n" F_EPI))
+Fi3 (_selfhrnz, asm(".insn rrf, 0xB9C00000, %%r0, %%r3, %%r2, 7\n" F_EPI))
int main(int argc, char *argv[])
--
2.32.0
next prev parent reply other threads:[~2022-02-17 23:21 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-02-17 23:17 [PATCH v6 0/4] s390x: Add partial z15 support and tests David Miller
2022-02-17 23:17 ` [PATCH v6 1/4] s390x/tcg: Implement Miscellaneous-Instruction-Extensions Facility 3 for the s390x David Miller
2022-02-23 13:40 ` Christian Borntraeger
2022-02-23 22:29 ` David Miller
2022-02-24 7:04 ` Christian Borntraeger
2022-02-23 19:40 ` Richard Henderson
2022-02-23 21:11 ` David Miller
2022-02-17 23:17 ` [PATCH v6 2/4] s390x/cpumodel: Bump up QEMU model to a stripped-down IBM z15 GA1 David Miller
2022-02-17 23:17 ` [PATCH v6 3/4] tests/tcg/s390x: Tests for Miscellaneous-Instruction-Extensions Facility 3 David Miller
2022-02-23 19:45 ` Richard Henderson
2022-02-23 20:17 ` David Miller
2022-02-17 23:17 ` David Miller [this message]
2022-02-23 10:44 ` [PATCH v6 4/4] tests/tcg/s390x: changed to using .insn for tests requiring z15 Thomas Huth
2022-02-23 10:54 ` David Hildenbrand
2022-02-23 11:49 ` Thomas Huth
2022-02-23 11:51 ` David Hildenbrand
2022-02-23 11:52 ` Thomas Huth
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20220217231728.13932-5-dmiller423@gmail.com \
--to=dmiller423@gmail.com \
--cc=borntraeger@linux.ibm.com \
--cc=cohuck@redhat.com \
--cc=david@redhat.com \
--cc=farman@linux.ibm.com \
--cc=pasic@linux.ibm.com \
--cc=qemu-devel@nongnu.org \
--cc=qemu-s390x@nongnu.org \
--cc=richard.henderson@linaro.org \
--cc=thuth@redhat.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).