* [PATCH v2] hw: riscv: opentitan: fixup SPI addresses
@ 2022-02-18 6:38 Alistair Francis
2022-02-18 8:58 ` Bin Meng
2022-02-21 7:14 ` Alistair Francis
0 siblings, 2 replies; 3+ messages in thread
From: Alistair Francis @ 2022-02-18 6:38 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: bmeng.cn, palmer, alistair.francis, alistair23, wilfred.mallawa
From: Wilfred Mallawa <wilfred.mallawa@wdc.com>
This patch updates the SPI_DEVICE, SPI_HOST0, SPI_HOST1
base addresses. Also adds these as unimplemented devices.
The address references can be found [1].
[1] https://github.com/lowRISC/opentitan/blob/6c317992fbd646818b34f2a2dbf44bc850e461e4/hw/top_earlgrey/sw/autogen/top_earlgrey_memory.h#L107
Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
v2: arranged base addrs in sorted order
hw/riscv/opentitan.c | 12 +++++++++---
include/hw/riscv/opentitan.h | 4 +++-
2 files changed, 12 insertions(+), 4 deletions(-)
diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
index aec7cfa33f..833624d66c 100644
--- a/hw/riscv/opentitan.c
+++ b/hw/riscv/opentitan.c
@@ -34,13 +34,15 @@ static const MemMapEntry ibex_memmap[] = {
[IBEX_DEV_FLASH] = { 0x20000000, 0x80000 },
[IBEX_DEV_UART] = { 0x40000000, 0x1000 },
[IBEX_DEV_GPIO] = { 0x40040000, 0x1000 },
- [IBEX_DEV_SPI] = { 0x40050000, 0x1000 },
+ [IBEX_DEV_SPI_DEVICE] = { 0x40050000, 0x1000 },
[IBEX_DEV_I2C] = { 0x40080000, 0x1000 },
[IBEX_DEV_PATTGEN] = { 0x400e0000, 0x1000 },
[IBEX_DEV_TIMER] = { 0x40100000, 0x1000 },
[IBEX_DEV_SENSOR_CTRL] = { 0x40110000, 0x1000 },
[IBEX_DEV_OTP_CTRL] = { 0x40130000, 0x4000 },
[IBEX_DEV_USBDEV] = { 0x40150000, 0x1000 },
+ [IBEX_DEV_SPI_HOST0] = { 0x40300000, 0x1000 },
+ [IBEX_DEV_SPI_HOST1] = { 0x40310000, 0x1000 },
[IBEX_DEV_PWRMGR] = { 0x40400000, 0x1000 },
[IBEX_DEV_RSTMGR] = { 0x40410000, 0x1000 },
[IBEX_DEV_CLKMGR] = { 0x40420000, 0x1000 },
@@ -209,8 +211,12 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
create_unimplemented_device("riscv.lowrisc.ibex.gpio",
memmap[IBEX_DEV_GPIO].base, memmap[IBEX_DEV_GPIO].size);
- create_unimplemented_device("riscv.lowrisc.ibex.spi",
- memmap[IBEX_DEV_SPI].base, memmap[IBEX_DEV_SPI].size);
+ create_unimplemented_device("riscv.lowrisc.ibex.spi_device",
+ memmap[IBEX_DEV_SPI_DEVICE].base, memmap[IBEX_DEV_SPI_DEVICE].size);
+ create_unimplemented_device("riscv.lowrisc.ibex.spi_host0",
+ memmap[IBEX_DEV_SPI_HOST0].base, memmap[IBEX_DEV_SPI_HOST0].size);
+ create_unimplemented_device("riscv.lowrisc.ibex.spi_host1",
+ memmap[IBEX_DEV_SPI_HOST1].base, memmap[IBEX_DEV_SPI_HOST1].size);
create_unimplemented_device("riscv.lowrisc.ibex.i2c",
memmap[IBEX_DEV_I2C].base, memmap[IBEX_DEV_I2C].size);
create_unimplemented_device("riscv.lowrisc.ibex.pattgen",
diff --git a/include/hw/riscv/opentitan.h b/include/hw/riscv/opentitan.h
index eac35ef590..00da9ded43 100644
--- a/include/hw/riscv/opentitan.h
+++ b/include/hw/riscv/opentitan.h
@@ -57,8 +57,10 @@ enum {
IBEX_DEV_FLASH,
IBEX_DEV_FLASH_VIRTUAL,
IBEX_DEV_UART,
+ IBEX_DEV_SPI_DEVICE,
+ IBEX_DEV_SPI_HOST0,
+ IBEX_DEV_SPI_HOST1,
IBEX_DEV_GPIO,
- IBEX_DEV_SPI,
IBEX_DEV_I2C,
IBEX_DEV_PATTGEN,
IBEX_DEV_TIMER,
--
2.35.1
^ permalink raw reply related [flat|nested] 3+ messages in thread* Re: [PATCH v2] hw: riscv: opentitan: fixup SPI addresses
2022-02-18 6:38 [PATCH v2] hw: riscv: opentitan: fixup SPI addresses Alistair Francis
@ 2022-02-18 8:58 ` Bin Meng
2022-02-21 7:14 ` Alistair Francis
1 sibling, 0 replies; 3+ messages in thread
From: Bin Meng @ 2022-02-18 8:58 UTC (permalink / raw)
To: Alistair Francis
Cc: open list:RISC-V, wilfred.mallawa,
qemu-devel@nongnu.org Developers, Palmer Dabbelt,
Alistair Francis, Alistair Francis
On Fri, Feb 18, 2022 at 2:38 PM Alistair Francis
<alistair.francis@opensource.wdc.com> wrote:
>
> From: Wilfred Mallawa <wilfred.mallawa@wdc.com>
>
> This patch updates the SPI_DEVICE, SPI_HOST0, SPI_HOST1
> base addresses. Also adds these as unimplemented devices.
>
> The address references can be found [1].
>
> [1] https://github.com/lowRISC/opentitan/blob/6c317992fbd646818b34f2a2dbf44bc850e461e4/hw/top_earlgrey/sw/autogen/top_earlgrey_memory.h#L107
>
> Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
> ---
> v2: arranged base addrs in sorted order
>
> hw/riscv/opentitan.c | 12 +++++++++---
> include/hw/riscv/opentitan.h | 4 +++-
> 2 files changed, 12 insertions(+), 4 deletions(-)
>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH v2] hw: riscv: opentitan: fixup SPI addresses
2022-02-18 6:38 [PATCH v2] hw: riscv: opentitan: fixup SPI addresses Alistair Francis
2022-02-18 8:58 ` Bin Meng
@ 2022-02-21 7:14 ` Alistair Francis
1 sibling, 0 replies; 3+ messages in thread
From: Alistair Francis @ 2022-02-21 7:14 UTC (permalink / raw)
To: Alistair Francis
Cc: open list:RISC-V, wilfred.mallawa,
qemu-devel@nongnu.org Developers, Palmer Dabbelt,
Alistair Francis, Bin Meng
On Fri, Feb 18, 2022 at 4:38 PM Alistair Francis
<alistair.francis@opensource.wdc.com> wrote:
>
> From: Wilfred Mallawa <wilfred.mallawa@wdc.com>
>
> This patch updates the SPI_DEVICE, SPI_HOST0, SPI_HOST1
> base addresses. Also adds these as unimplemented devices.
>
> The address references can be found [1].
>
> [1] https://github.com/lowRISC/opentitan/blob/6c317992fbd646818b34f2a2dbf44bc850e461e4/hw/top_earlgrey/sw/autogen/top_earlgrey_memory.h#L107
>
> Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Thanks!
Applied to riscv-to-apply.next
Alistair
> ---
> v2: arranged base addrs in sorted order
>
> hw/riscv/opentitan.c | 12 +++++++++---
> include/hw/riscv/opentitan.h | 4 +++-
> 2 files changed, 12 insertions(+), 4 deletions(-)
>
> diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
> index aec7cfa33f..833624d66c 100644
> --- a/hw/riscv/opentitan.c
> +++ b/hw/riscv/opentitan.c
> @@ -34,13 +34,15 @@ static const MemMapEntry ibex_memmap[] = {
> [IBEX_DEV_FLASH] = { 0x20000000, 0x80000 },
> [IBEX_DEV_UART] = { 0x40000000, 0x1000 },
> [IBEX_DEV_GPIO] = { 0x40040000, 0x1000 },
> - [IBEX_DEV_SPI] = { 0x40050000, 0x1000 },
> + [IBEX_DEV_SPI_DEVICE] = { 0x40050000, 0x1000 },
> [IBEX_DEV_I2C] = { 0x40080000, 0x1000 },
> [IBEX_DEV_PATTGEN] = { 0x400e0000, 0x1000 },
> [IBEX_DEV_TIMER] = { 0x40100000, 0x1000 },
> [IBEX_DEV_SENSOR_CTRL] = { 0x40110000, 0x1000 },
> [IBEX_DEV_OTP_CTRL] = { 0x40130000, 0x4000 },
> [IBEX_DEV_USBDEV] = { 0x40150000, 0x1000 },
> + [IBEX_DEV_SPI_HOST0] = { 0x40300000, 0x1000 },
> + [IBEX_DEV_SPI_HOST1] = { 0x40310000, 0x1000 },
> [IBEX_DEV_PWRMGR] = { 0x40400000, 0x1000 },
> [IBEX_DEV_RSTMGR] = { 0x40410000, 0x1000 },
> [IBEX_DEV_CLKMGR] = { 0x40420000, 0x1000 },
> @@ -209,8 +211,12 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
>
> create_unimplemented_device("riscv.lowrisc.ibex.gpio",
> memmap[IBEX_DEV_GPIO].base, memmap[IBEX_DEV_GPIO].size);
> - create_unimplemented_device("riscv.lowrisc.ibex.spi",
> - memmap[IBEX_DEV_SPI].base, memmap[IBEX_DEV_SPI].size);
> + create_unimplemented_device("riscv.lowrisc.ibex.spi_device",
> + memmap[IBEX_DEV_SPI_DEVICE].base, memmap[IBEX_DEV_SPI_DEVICE].size);
> + create_unimplemented_device("riscv.lowrisc.ibex.spi_host0",
> + memmap[IBEX_DEV_SPI_HOST0].base, memmap[IBEX_DEV_SPI_HOST0].size);
> + create_unimplemented_device("riscv.lowrisc.ibex.spi_host1",
> + memmap[IBEX_DEV_SPI_HOST1].base, memmap[IBEX_DEV_SPI_HOST1].size);
> create_unimplemented_device("riscv.lowrisc.ibex.i2c",
> memmap[IBEX_DEV_I2C].base, memmap[IBEX_DEV_I2C].size);
> create_unimplemented_device("riscv.lowrisc.ibex.pattgen",
> diff --git a/include/hw/riscv/opentitan.h b/include/hw/riscv/opentitan.h
> index eac35ef590..00da9ded43 100644
> --- a/include/hw/riscv/opentitan.h
> +++ b/include/hw/riscv/opentitan.h
> @@ -57,8 +57,10 @@ enum {
> IBEX_DEV_FLASH,
> IBEX_DEV_FLASH_VIRTUAL,
> IBEX_DEV_UART,
> + IBEX_DEV_SPI_DEVICE,
> + IBEX_DEV_SPI_HOST0,
> + IBEX_DEV_SPI_HOST1,
> IBEX_DEV_GPIO,
> - IBEX_DEV_SPI,
> IBEX_DEV_I2C,
> IBEX_DEV_PATTGEN,
> IBEX_DEV_TIMER,
> --
> 2.35.1
>
^ permalink raw reply [flat|nested] 3+ messages in thread
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2022-02-18 6:38 [PATCH v2] hw: riscv: opentitan: fixup SPI addresses Alistair Francis
2022-02-18 8:58 ` Bin Meng
2022-02-21 7:14 ` Alistair Francis
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