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* [PATCH 1/2] pci-bridge/xio3130_upstream: Fix error handling
@ 2022-02-18 10:23 Jonathan Cameron via
  2022-02-18 10:23 ` [PATCH 2/2] pci-bridge/xio3130_downstream: " Jonathan Cameron via
  2022-02-18 10:31 ` [PATCH 1/2] pci-bridge/xio3130_upstream: " Jonathan Cameron via
  0 siblings, 2 replies; 3+ messages in thread
From: Jonathan Cameron via @ 2022-02-18 10:23 UTC (permalink / raw)
  To: qemu-devel, Marcel Apfelbaum,
	Michael S . Tsirkin --cc=linuxarm @ huawei . com

Goto label is incorrect so msi cleanup would not occur if there is
an error in the ssvid initialization.

Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
Noticed whilst working on equivalent CXL upstream switch port.

 hw/pci-bridge/xio3130_upstream.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/pci-bridge/xio3130_upstream.c b/hw/pci-bridge/xio3130_upstream.c
index 5cd3af4fbc..5ff46ef050 100644
--- a/hw/pci-bridge/xio3130_upstream.c
+++ b/hw/pci-bridge/xio3130_upstream.c
@@ -75,7 +75,7 @@ static void xio3130_upstream_realize(PCIDevice *d, Error **errp)
                                XIO3130_SSVID_SVID, XIO3130_SSVID_SSID,
                                errp);
     if (rc < 0) {
-        goto err_bridge;
+        goto err_msi;
     }
 
     rc = pcie_cap_init(d, XIO3130_EXP_OFFSET, PCI_EXP_TYPE_UPSTREAM,
-- 
2.32.0



^ permalink raw reply related	[flat|nested] 3+ messages in thread

* [PATCH 2/2] pci-bridge/xio3130_downstream: Fix error handling
  2022-02-18 10:23 [PATCH 1/2] pci-bridge/xio3130_upstream: Fix error handling Jonathan Cameron via
@ 2022-02-18 10:23 ` Jonathan Cameron via
  2022-02-18 10:31 ` [PATCH 1/2] pci-bridge/xio3130_upstream: " Jonathan Cameron via
  1 sibling, 0 replies; 3+ messages in thread
From: Jonathan Cameron via @ 2022-02-18 10:23 UTC (permalink / raw)
  To: qemu-devel, Marcel Apfelbaum,
	Michael S . Tsirkin --cc=linuxarm @ huawei . com

Wrong goto label, so msi cleanup would not occur if there is
an error in the ssvid initialization.

Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
 hw/pci-bridge/xio3130_downstream.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/pci-bridge/xio3130_downstream.c b/hw/pci-bridge/xio3130_downstream.c
index 04aae72cd6..080a6613fe 100644
--- a/hw/pci-bridge/xio3130_downstream.c
+++ b/hw/pci-bridge/xio3130_downstream.c
@@ -84,7 +84,7 @@ static void xio3130_downstream_realize(PCIDevice *d, Error **errp)
                                XIO3130_SSVID_SVID, XIO3130_SSVID_SSID,
                                errp);
     if (rc < 0) {
-        goto err_bridge;
+        goto err_msi;
     }
 
     rc = pcie_cap_init(d, XIO3130_EXP_OFFSET, PCI_EXP_TYPE_DOWNSTREAM,
-- 
2.32.0



^ permalink raw reply related	[flat|nested] 3+ messages in thread

* Re: [PATCH 1/2] pci-bridge/xio3130_upstream: Fix error handling
  2022-02-18 10:23 [PATCH 1/2] pci-bridge/xio3130_upstream: Fix error handling Jonathan Cameron via
  2022-02-18 10:23 ` [PATCH 2/2] pci-bridge/xio3130_downstream: " Jonathan Cameron via
@ 2022-02-18 10:31 ` Jonathan Cameron via
  1 sibling, 0 replies; 3+ messages in thread
From: Jonathan Cameron via @ 2022-02-18 10:31 UTC (permalink / raw)
  To: Jonathan Cameron via
  Cc: Jonathan Cameron, Marcel Apfelbaum, Michael S . Tsirkin, linuxarm

On Fri, 18 Feb 2022 10:23:02 +0000
Jonathan Cameron via <qemu-devel@nongnu.org> wrote:

> Goto label is incorrect so msi cleanup would not occur if there is
> an error in the ssvid initialization.
> 
> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>

+Cc: Linuxarm@huawei.com  Turns out you get a weird result if you miss
a space in your git send-email command.  Apologies to Michael for scrambling
his email address as a result!

> ---
> Noticed whilst working on equivalent CXL upstream switch port.
> 
>  hw/pci-bridge/xio3130_upstream.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/hw/pci-bridge/xio3130_upstream.c b/hw/pci-bridge/xio3130_upstream.c
> index 5cd3af4fbc..5ff46ef050 100644
> --- a/hw/pci-bridge/xio3130_upstream.c
> +++ b/hw/pci-bridge/xio3130_upstream.c
> @@ -75,7 +75,7 @@ static void xio3130_upstream_realize(PCIDevice *d, Error **errp)
>                                 XIO3130_SSVID_SVID, XIO3130_SSVID_SSID,
>                                 errp);
>      if (rc < 0) {
> -        goto err_bridge;
> +        goto err_msi;
>      }
>  
>      rc = pcie_cap_init(d, XIO3130_EXP_OFFSET, PCI_EXP_TYPE_UPSTREAM,



^ permalink raw reply	[flat|nested] 3+ messages in thread

end of thread, other threads:[~2022-02-18 10:33 UTC | newest]

Thread overview: 3+ messages (download: mbox.gz follow: Atom feed
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2022-02-18 10:23 [PATCH 1/2] pci-bridge/xio3130_upstream: Fix error handling Jonathan Cameron via
2022-02-18 10:23 ` [PATCH 2/2] pci-bridge/xio3130_downstream: " Jonathan Cameron via
2022-02-18 10:31 ` [PATCH 1/2] pci-bridge/xio3130_upstream: " Jonathan Cameron via

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