* [PULL 01/39] nvdimm: Add realize, unrealize callbacks to NVDIMMDevice class
2022-02-18 10:37 [PULL 00/39] ppc queue Cédric Le Goater
@ 2022-02-18 10:37 ` Cédric Le Goater
2022-02-18 10:37 ` [PULL 02/39] spapr: nvdimm: Implement H_SCM_FLUSH hcall Cédric Le Goater
` (38 subsequent siblings)
39 siblings, 0 replies; 41+ messages in thread
From: Cédric Le Goater @ 2022-02-18 10:37 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Daniel Henrique Barboza, Cédric Le Goater,
Shivaprasad G Bhat
From: Shivaprasad G Bhat <sbhat@linux.ibm.com>
A new subclass inheriting NVDIMMDevice is going to be introduced in
subsequent patches. The new subclass uses the realize and unrealize
callbacks. Add them on NVDIMMClass to appropriately call them as part
of plug-unplug.
Signed-off-by: Shivaprasad G Bhat <sbhat@linux.ibm.com>
Acked-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <164396253158.109112.1926755104259023743.stgit@ltczzess4.aus.stglabs.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
include/hw/mem/nvdimm.h | 2 ++
include/hw/mem/pc-dimm.h | 1 +
hw/mem/nvdimm.c | 16 ++++++++++++++++
hw/mem/pc-dimm.c | 5 +++++
4 files changed, 24 insertions(+)
diff --git a/include/hw/mem/nvdimm.h b/include/hw/mem/nvdimm.h
index bcf62f825c74..cf8f59be44f9 100644
--- a/include/hw/mem/nvdimm.h
+++ b/include/hw/mem/nvdimm.h
@@ -103,6 +103,8 @@ struct NVDIMMClass {
/* write @size bytes from @buf to NVDIMM label data at @offset. */
void (*write_label_data)(NVDIMMDevice *nvdimm, const void *buf,
uint64_t size, uint64_t offset);
+ void (*realize)(NVDIMMDevice *nvdimm, Error **errp);
+ void (*unrealize)(NVDIMMDevice *nvdimm);
};
#define NVDIMM_DSM_MEM_FILE "etc/acpi/nvdimm-mem"
diff --git a/include/hw/mem/pc-dimm.h b/include/hw/mem/pc-dimm.h
index 1473e6db6254..322bebe555b5 100644
--- a/include/hw/mem/pc-dimm.h
+++ b/include/hw/mem/pc-dimm.h
@@ -63,6 +63,7 @@ struct PCDIMMDeviceClass {
/* public */
void (*realize)(PCDIMMDevice *dimm, Error **errp);
+ void (*unrealize)(PCDIMMDevice *dimm);
};
void pc_dimm_pre_plug(PCDIMMDevice *dimm, MachineState *machine,
diff --git a/hw/mem/nvdimm.c b/hw/mem/nvdimm.c
index 7397b6715652..59959d556337 100644
--- a/hw/mem/nvdimm.c
+++ b/hw/mem/nvdimm.c
@@ -181,10 +181,25 @@ static MemoryRegion *nvdimm_md_get_memory_region(MemoryDeviceState *md,
static void nvdimm_realize(PCDIMMDevice *dimm, Error **errp)
{
NVDIMMDevice *nvdimm = NVDIMM(dimm);
+ NVDIMMClass *ndc = NVDIMM_GET_CLASS(nvdimm);
if (!nvdimm->nvdimm_mr) {
nvdimm_prepare_memory_region(nvdimm, errp);
}
+
+ if (ndc->realize) {
+ ndc->realize(nvdimm, errp);
+ }
+}
+
+static void nvdimm_unrealize(PCDIMMDevice *dimm)
+{
+ NVDIMMDevice *nvdimm = NVDIMM(dimm);
+ NVDIMMClass *ndc = NVDIMM_GET_CLASS(nvdimm);
+
+ if (ndc->unrealize) {
+ ndc->unrealize(nvdimm);
+ }
}
/*
@@ -240,6 +255,7 @@ static void nvdimm_class_init(ObjectClass *oc, void *data)
DeviceClass *dc = DEVICE_CLASS(oc);
ddc->realize = nvdimm_realize;
+ ddc->unrealize = nvdimm_unrealize;
mdc->get_memory_region = nvdimm_md_get_memory_region;
device_class_set_props(dc, nvdimm_properties);
diff --git a/hw/mem/pc-dimm.c b/hw/mem/pc-dimm.c
index 48b913aba677..03bd0dd60e5c 100644
--- a/hw/mem/pc-dimm.c
+++ b/hw/mem/pc-dimm.c
@@ -216,6 +216,11 @@ static void pc_dimm_realize(DeviceState *dev, Error **errp)
static void pc_dimm_unrealize(DeviceState *dev)
{
PCDIMMDevice *dimm = PC_DIMM(dev);
+ PCDIMMDeviceClass *ddc = PC_DIMM_GET_CLASS(dimm);
+
+ if (ddc->unrealize) {
+ ddc->unrealize(dimm);
+ }
host_memory_backend_set_mapped(dimm->hostmem, false);
}
--
2.34.1
^ permalink raw reply related [flat|nested] 41+ messages in thread* [PULL 02/39] spapr: nvdimm: Implement H_SCM_FLUSH hcall
2022-02-18 10:37 [PULL 00/39] ppc queue Cédric Le Goater
2022-02-18 10:37 ` [PULL 01/39] nvdimm: Add realize, unrealize callbacks to NVDIMMDevice class Cédric Le Goater
@ 2022-02-18 10:37 ` Cédric Le Goater
2022-02-18 10:37 ` [PULL 03/39] spapr: nvdimm: Introduce spapr-nvdimm device Cédric Le Goater
` (37 subsequent siblings)
39 siblings, 0 replies; 41+ messages in thread
From: Cédric Le Goater @ 2022-02-18 10:37 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Daniel Henrique Barboza, Cédric Le Goater,
Shivaprasad G Bhat
From: Shivaprasad G Bhat <sbhat@linux.ibm.com>
The patch adds support for the SCM flush hcall for the nvdimm devices.
To be available for exploitation by guest through the next patch. The
hcall is applicable only for new SPAPR specific device class which is
also introduced in this patch.
The hcall expects the semantics such that the flush to return with
H_LONG_BUSY_ORDER_10_MSEC when the operation is expected to take longer
time along with a continue_token. The hcall to be called again by providing
the continue_token to get the status. So, all fresh requests are put into
a 'pending' list and flush worker is submitted to the thread pool. The
thread pool completion callbacks move the requests to 'completed' list,
which are cleaned up after collecting the return status for the guest
in subsequent hcall from the guest.
The semantics makes it necessary to preserve the continue_tokens and
their return status across migrations. So, the completed flush states
are forwarded to the destination and the pending ones are restarted
at the destination in post_load. The necessary nvdimm flush specific
vmstate structures are also introduced in this patch which are to be
saved in the new SPAPR specific nvdimm device to be introduced in the
following patch.
Signed-off-by: Shivaprasad G Bhat <sbhat@linux.ibm.com>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <164396254862.109112.16675611182159105748.stgit@ltczzess4.aus.stglabs.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
include/hw/ppc/spapr.h | 4 +-
include/hw/ppc/spapr_nvdimm.h | 1 +
hw/ppc/spapr.c | 2 +
hw/ppc/spapr_nvdimm.c | 260 ++++++++++++++++++++++++++++++++++
4 files changed, 266 insertions(+), 1 deletion(-)
diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h
index ee7504b9760b..727b2a0e7fc9 100644
--- a/include/hw/ppc/spapr.h
+++ b/include/hw/ppc/spapr.h
@@ -341,6 +341,7 @@ struct SpaprMachineState {
#define H_P7 -60
#define H_P8 -61
#define H_P9 -62
+#define H_UNSUPPORTED -67
#define H_OVERLAP -68
#define H_UNSUPPORTED_FLAG -256
#define H_MULTI_THREADS_ACTIVE -9005
@@ -559,8 +560,9 @@ struct SpaprMachineState {
#define H_SCM_UNBIND_ALL 0x3FC
#define H_SCM_HEALTH 0x400
#define H_RPT_INVALIDATE 0x448
+#define H_SCM_FLUSH 0x44C
-#define MAX_HCALL_OPCODE H_RPT_INVALIDATE
+#define MAX_HCALL_OPCODE H_SCM_FLUSH
/* The hcalls above are standardized in PAPR and implemented by pHyp
* as well.
diff --git a/include/hw/ppc/spapr_nvdimm.h b/include/hw/ppc/spapr_nvdimm.h
index 764f999f5471..e9436cb6ef61 100644
--- a/include/hw/ppc/spapr_nvdimm.h
+++ b/include/hw/ppc/spapr_nvdimm.h
@@ -21,5 +21,6 @@ void spapr_dt_persistent_memory(SpaprMachineState *spapr, void *fdt);
bool spapr_nvdimm_validate(HotplugHandler *hotplug_dev, NVDIMMDevice *nvdimm,
uint64_t size, Error **errp);
void spapr_add_nvdimm(DeviceState *dev, uint64_t slot);
+void spapr_nvdimm_finish_flushes(void);
#endif
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index 3d6ec309dd21..92639856635a 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -1634,6 +1634,8 @@ static void spapr_machine_reset(MachineState *machine)
spapr->ov5_cas = spapr_ovec_clone(spapr->ov5);
}
+ spapr_nvdimm_finish_flushes();
+
/* DRC reset may cause a device to be unplugged. This will cause troubles
* if this device is used by another device (eg, a running vhost backend
* will crash QEMU if the DIMM holding the vring goes away). To avoid such
diff --git a/hw/ppc/spapr_nvdimm.c b/hw/ppc/spapr_nvdimm.c
index 91de1052f233..ac44e0015317 100644
--- a/hw/ppc/spapr_nvdimm.c
+++ b/hw/ppc/spapr_nvdimm.c
@@ -22,6 +22,7 @@
* THE SOFTWARE.
*/
#include "qemu/osdep.h"
+#include "qemu/cutils.h"
#include "qapi/error.h"
#include "hw/ppc/spapr_drc.h"
#include "hw/ppc/spapr_nvdimm.h"
@@ -30,6 +31,9 @@
#include "hw/ppc/fdt.h"
#include "qemu/range.h"
#include "hw/ppc/spapr_numa.h"
+#include "block/thread-pool.h"
+#include "migration/vmstate.h"
+#include "qemu/pmem.h"
/* DIMM health bitmap bitmap indicators. Taken from kernel's papr_scm.c */
/* SCM device is unable to persist memory contents */
@@ -47,6 +51,14 @@
/* Have an explicit check for alignment */
QEMU_BUILD_BUG_ON(SPAPR_MINIMUM_SCM_BLOCK_SIZE % SPAPR_MEMORY_BLOCK_SIZE);
+#define TYPE_SPAPR_NVDIMM "spapr-nvdimm"
+OBJECT_DECLARE_TYPE(SpaprNVDIMMDevice, SPAPRNVDIMMClass, SPAPR_NVDIMM)
+
+struct SPAPRNVDIMMClass {
+ /* private */
+ NVDIMMClass parent_class;
+};
+
bool spapr_nvdimm_validate(HotplugHandler *hotplug_dev, NVDIMMDevice *nvdimm,
uint64_t size, Error **errp)
{
@@ -375,6 +387,253 @@ static target_ulong h_scm_bind_mem(PowerPCCPU *cpu, SpaprMachineState *spapr,
return H_SUCCESS;
}
+typedef struct SpaprNVDIMMDeviceFlushState {
+ uint64_t continue_token;
+ int64_t hcall_ret;
+ uint32_t drcidx;
+
+ QLIST_ENTRY(SpaprNVDIMMDeviceFlushState) node;
+} SpaprNVDIMMDeviceFlushState;
+
+typedef struct SpaprNVDIMMDevice SpaprNVDIMMDevice;
+struct SpaprNVDIMMDevice {
+ NVDIMMDevice parent_obj;
+
+ uint64_t nvdimm_flush_token;
+ QLIST_HEAD(, SpaprNVDIMMDeviceFlushState) pending_nvdimm_flush_states;
+ QLIST_HEAD(, SpaprNVDIMMDeviceFlushState) completed_nvdimm_flush_states;
+};
+
+static int flush_worker_cb(void *opaque)
+{
+ SpaprNVDIMMDeviceFlushState *state = opaque;
+ SpaprDrc *drc = spapr_drc_by_index(state->drcidx);
+ PCDIMMDevice *dimm = PC_DIMM(drc->dev);
+ HostMemoryBackend *backend = MEMORY_BACKEND(dimm->hostmem);
+ int backend_fd = memory_region_get_fd(&backend->mr);
+
+ if (object_property_get_bool(OBJECT(backend), "pmem", NULL)) {
+ MemoryRegion *mr = host_memory_backend_get_memory(dimm->hostmem);
+ void *ptr = memory_region_get_ram_ptr(mr);
+ size_t size = object_property_get_uint(OBJECT(dimm), PC_DIMM_SIZE_PROP,
+ NULL);
+
+ /* flush pmem backend */
+ pmem_persist(ptr, size);
+ } else {
+ /* flush raw backing image */
+ if (qemu_fdatasync(backend_fd) < 0) {
+ error_report("papr_scm: Could not sync nvdimm to backend file: %s",
+ strerror(errno));
+ return H_HARDWARE;
+ }
+ }
+
+ return H_SUCCESS;
+}
+
+static void spapr_nvdimm_flush_completion_cb(void *opaque, int hcall_ret)
+{
+ SpaprNVDIMMDeviceFlushState *state = opaque;
+ SpaprDrc *drc = spapr_drc_by_index(state->drcidx);
+ SpaprNVDIMMDevice *s_nvdimm = SPAPR_NVDIMM(drc->dev);
+
+ state->hcall_ret = hcall_ret;
+ QLIST_REMOVE(state, node);
+ QLIST_INSERT_HEAD(&s_nvdimm->completed_nvdimm_flush_states, state, node);
+}
+
+static int spapr_nvdimm_flush_post_load(void *opaque, int version_id)
+{
+ SpaprNVDIMMDevice *s_nvdimm = (SpaprNVDIMMDevice *)opaque;
+ SpaprNVDIMMDeviceFlushState *state;
+ ThreadPool *pool = aio_get_thread_pool(qemu_get_aio_context());
+
+ QLIST_FOREACH(state, &s_nvdimm->pending_nvdimm_flush_states, node) {
+ thread_pool_submit_aio(pool, flush_worker_cb, state,
+ spapr_nvdimm_flush_completion_cb, state);
+ }
+
+ return 0;
+}
+
+static const VMStateDescription vmstate_spapr_nvdimm_flush_state = {
+ .name = "spapr_nvdimm_flush_state",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT64(continue_token, SpaprNVDIMMDeviceFlushState),
+ VMSTATE_INT64(hcall_ret, SpaprNVDIMMDeviceFlushState),
+ VMSTATE_UINT32(drcidx, SpaprNVDIMMDeviceFlushState),
+ VMSTATE_END_OF_LIST()
+ },
+};
+
+const VMStateDescription vmstate_spapr_nvdimm_states = {
+ .name = "spapr_nvdimm_states",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .post_load = spapr_nvdimm_flush_post_load,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT64(nvdimm_flush_token, SpaprNVDIMMDevice),
+ VMSTATE_QLIST_V(completed_nvdimm_flush_states, SpaprNVDIMMDevice, 1,
+ vmstate_spapr_nvdimm_flush_state,
+ SpaprNVDIMMDeviceFlushState, node),
+ VMSTATE_QLIST_V(pending_nvdimm_flush_states, SpaprNVDIMMDevice, 1,
+ vmstate_spapr_nvdimm_flush_state,
+ SpaprNVDIMMDeviceFlushState, node),
+ VMSTATE_END_OF_LIST()
+ },
+};
+
+/*
+ * Assign a token and reserve it for the new flush state.
+ */
+static SpaprNVDIMMDeviceFlushState *spapr_nvdimm_init_new_flush_state(
+ SpaprNVDIMMDevice *spapr_nvdimm)
+{
+ SpaprNVDIMMDeviceFlushState *state;
+
+ state = g_malloc0(sizeof(*state));
+
+ spapr_nvdimm->nvdimm_flush_token++;
+ /* Token zero is presumed as no job pending. Assert on overflow to zero */
+ g_assert(spapr_nvdimm->nvdimm_flush_token != 0);
+
+ state->continue_token = spapr_nvdimm->nvdimm_flush_token;
+
+ QLIST_INSERT_HEAD(&spapr_nvdimm->pending_nvdimm_flush_states, state, node);
+
+ return state;
+}
+
+/*
+ * spapr_nvdimm_finish_flushes
+ * Waits for all pending flush requests to complete
+ * their execution and free the states
+ */
+void spapr_nvdimm_finish_flushes(void)
+{
+ SpaprNVDIMMDeviceFlushState *state, *next;
+ GSList *list, *nvdimms;
+
+ /*
+ * Called on reset path, the main loop thread which calls
+ * the pending BHs has gotten out running in the reset path,
+ * finally reaching here. Other code path being guest
+ * h_client_architecture_support, thats early boot up.
+ */
+ nvdimms = nvdimm_get_device_list();
+ for (list = nvdimms; list; list = list->next) {
+ NVDIMMDevice *nvdimm = list->data;
+ if (object_dynamic_cast(OBJECT(nvdimm), TYPE_SPAPR_NVDIMM)) {
+ SpaprNVDIMMDevice *s_nvdimm = SPAPR_NVDIMM(nvdimm);
+ while (!QLIST_EMPTY(&s_nvdimm->pending_nvdimm_flush_states)) {
+ aio_poll(qemu_get_aio_context(), true);
+ }
+
+ QLIST_FOREACH_SAFE(state, &s_nvdimm->completed_nvdimm_flush_states,
+ node, next) {
+ QLIST_REMOVE(state, node);
+ g_free(state);
+ }
+ }
+ }
+ g_slist_free(nvdimms);
+}
+
+/*
+ * spapr_nvdimm_get_flush_status
+ * Fetches the status of the hcall worker and returns
+ * H_LONG_BUSY_ORDER_10_MSEC if the worker is still running.
+ */
+static int spapr_nvdimm_get_flush_status(SpaprNVDIMMDevice *s_nvdimm,
+ uint64_t token)
+{
+ SpaprNVDIMMDeviceFlushState *state, *node;
+
+ QLIST_FOREACH(state, &s_nvdimm->pending_nvdimm_flush_states, node) {
+ if (state->continue_token == token) {
+ return H_LONG_BUSY_ORDER_10_MSEC;
+ }
+ }
+
+ QLIST_FOREACH_SAFE(state, &s_nvdimm->completed_nvdimm_flush_states,
+ node, node) {
+ if (state->continue_token == token) {
+ int ret = state->hcall_ret;
+ QLIST_REMOVE(state, node);
+ g_free(state);
+ return ret;
+ }
+ }
+
+ /* If not found in complete list too, invalid token */
+ return H_P2;
+}
+
+/*
+ * H_SCM_FLUSH
+ * Input: drc_index, continue-token
+ * Out: continue-token
+ * Return Value: H_SUCCESS, H_Parameter, H_P2, H_LONG_BUSY_ORDER_10_MSEC,
+ * H_UNSUPPORTED
+ *
+ * Given a DRC Index Flush the data to backend NVDIMM device. The hcall returns
+ * H_LONG_BUSY_ORDER_10_MSEC when the flush takes longer time and the hcall
+ * needs to be issued multiple times in order to be completely serviced. The
+ * continue-token from the output to be passed in the argument list of
+ * subsequent hcalls until the hcall is completely serviced at which point
+ * H_SUCCESS or other error is returned.
+ */
+static target_ulong h_scm_flush(PowerPCCPU *cpu, SpaprMachineState *spapr,
+ target_ulong opcode, target_ulong *args)
+{
+ int ret;
+ uint32_t drc_index = args[0];
+ uint64_t continue_token = args[1];
+ SpaprDrc *drc = spapr_drc_by_index(drc_index);
+ PCDIMMDevice *dimm;
+ HostMemoryBackend *backend = NULL;
+ SpaprNVDIMMDeviceFlushState *state;
+ ThreadPool *pool = aio_get_thread_pool(qemu_get_aio_context());
+ int fd;
+
+ if (!drc || !drc->dev ||
+ spapr_drc_type(drc) != SPAPR_DR_CONNECTOR_TYPE_PMEM) {
+ return H_PARAMETER;
+ }
+
+ dimm = PC_DIMM(drc->dev);
+ if (continue_token == 0) {
+ backend = MEMORY_BACKEND(dimm->hostmem);
+ fd = memory_region_get_fd(&backend->mr);
+
+ if (fd < 0) {
+ return H_UNSUPPORTED;
+ }
+
+ state = spapr_nvdimm_init_new_flush_state(SPAPR_NVDIMM(dimm));
+ if (!state) {
+ return H_HARDWARE;
+ }
+
+ state->drcidx = drc_index;
+
+ thread_pool_submit_aio(pool, flush_worker_cb, state,
+ spapr_nvdimm_flush_completion_cb, state);
+
+ continue_token = state->continue_token;
+ }
+
+ ret = spapr_nvdimm_get_flush_status(SPAPR_NVDIMM(dimm), continue_token);
+ if (H_IS_LONG_BUSY(ret)) {
+ args[0] = continue_token;
+ }
+
+ return ret;
+}
+
static target_ulong h_scm_unbind_mem(PowerPCCPU *cpu, SpaprMachineState *spapr,
target_ulong opcode, target_ulong *args)
{
@@ -523,6 +782,7 @@ static void spapr_scm_register_types(void)
spapr_register_hypercall(H_SCM_UNBIND_MEM, h_scm_unbind_mem);
spapr_register_hypercall(H_SCM_UNBIND_ALL, h_scm_unbind_all);
spapr_register_hypercall(H_SCM_HEALTH, h_scm_health);
+ spapr_register_hypercall(H_SCM_FLUSH, h_scm_flush);
}
type_init(spapr_scm_register_types)
--
2.34.1
^ permalink raw reply related [flat|nested] 41+ messages in thread* [PULL 03/39] spapr: nvdimm: Introduce spapr-nvdimm device
2022-02-18 10:37 [PULL 00/39] ppc queue Cédric Le Goater
2022-02-18 10:37 ` [PULL 01/39] nvdimm: Add realize, unrealize callbacks to NVDIMMDevice class Cédric Le Goater
2022-02-18 10:37 ` [PULL 02/39] spapr: nvdimm: Implement H_SCM_FLUSH hcall Cédric Le Goater
@ 2022-02-18 10:37 ` Cédric Le Goater
2022-02-18 10:37 ` [PULL 04/39] target/ppc: raise HV interrupts for partition table entry problems Cédric Le Goater
` (36 subsequent siblings)
39 siblings, 0 replies; 41+ messages in thread
From: Cédric Le Goater @ 2022-02-18 10:37 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Daniel Henrique Barboza, Cédric Le Goater,
Shivaprasad G Bhat
From: Shivaprasad G Bhat <sbhat@linux.ibm.com>
If the device backend is not persistent memory for the nvdimm, there is
need for explicit IO flushes on the backend to ensure persistence.
On SPAPR, the issue is addressed by adding a new hcall to request for
an explicit flush from the guest when the backend is not pmem. So, the
approach here is to convey when the hcall flush is required in a device
tree property. The guest once it knows the device backend is not pmem,
makes the hcall whenever flush is required.
To set the device tree property, a new PAPR specific device type inheriting
the nvdimm device is implemented. When the backend doesn't have pmem=on
the device tree property "ibm,hcall-flush-required" is set, and the guest
makes hcall H_SCM_FLUSH requesting for an explicit flush. The new device
has boolean property pmem-override which when "on" advertises the device
tree property even when pmem=on for the backend. The flush function
invokes the fdatasync or pmem_persist() based on the type of backend.
The vmstate structures are made part of the spapr-nvdimm device object.
The patch attempts to keep the migration compatibility between source and
destination while rejecting the incompatibles ones with failures.
Signed-off-by: Shivaprasad G Bhat <sbhat@linux.ibm.com>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <164396256092.109112.17933240273840803354.stgit@ltczzess4.aus.stglabs.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/ppc/spapr_nvdimm.c | 132 ++++++++++++++++++++++++++++++++++++++++++
1 file changed, 132 insertions(+)
diff --git a/hw/ppc/spapr_nvdimm.c b/hw/ppc/spapr_nvdimm.c
index ac44e0015317..c4c97da5de98 100644
--- a/hw/ppc/spapr_nvdimm.c
+++ b/hw/ppc/spapr_nvdimm.c
@@ -34,6 +34,7 @@
#include "block/thread-pool.h"
#include "migration/vmstate.h"
#include "qemu/pmem.h"
+#include "hw/qdev-properties.h"
/* DIMM health bitmap bitmap indicators. Taken from kernel's papr_scm.c */
/* SCM device is unable to persist memory contents */
@@ -57,6 +58,10 @@ OBJECT_DECLARE_TYPE(SpaprNVDIMMDevice, SPAPRNVDIMMClass, SPAPR_NVDIMM)
struct SPAPRNVDIMMClass {
/* private */
NVDIMMClass parent_class;
+
+ /* public */
+ void (*realize)(NVDIMMDevice *dimm, Error **errp);
+ void (*unrealize)(NVDIMMDevice *dimm, Error **errp);
};
bool spapr_nvdimm_validate(HotplugHandler *hotplug_dev, NVDIMMDevice *nvdimm,
@@ -64,6 +69,8 @@ bool spapr_nvdimm_validate(HotplugHandler *hotplug_dev, NVDIMMDevice *nvdimm,
{
const MachineClass *mc = MACHINE_GET_CLASS(hotplug_dev);
const MachineState *ms = MACHINE(hotplug_dev);
+ PCDIMMDevice *dimm = PC_DIMM(nvdimm);
+ MemoryRegion *mr = host_memory_backend_get_memory(dimm->hostmem);
g_autofree char *uuidstr = NULL;
QemuUUID uuid;
int ret;
@@ -101,6 +108,14 @@ bool spapr_nvdimm_validate(HotplugHandler *hotplug_dev, NVDIMMDevice *nvdimm,
return false;
}
+ if (object_dynamic_cast(OBJECT(nvdimm), TYPE_SPAPR_NVDIMM) &&
+ (memory_region_get_fd(mr) < 0)) {
+ error_setg(errp, "spapr-nvdimm device requires the "
+ "memdev %s to be of memory-backend-file type",
+ object_get_canonical_path_component(OBJECT(dimm->hostmem)));
+ return false;
+ }
+
return true;
}
@@ -172,6 +187,20 @@ static int spapr_dt_nvdimm(SpaprMachineState *spapr, void *fdt,
"operating-system")));
_FDT(fdt_setprop(fdt, child_offset, "ibm,cache-flush-required", NULL, 0));
+ if (object_dynamic_cast(OBJECT(nvdimm), TYPE_SPAPR_NVDIMM)) {
+ bool is_pmem = false, pmem_override = false;
+ PCDIMMDevice *dimm = PC_DIMM(nvdimm);
+ HostMemoryBackend *hostmem = dimm->hostmem;
+
+ is_pmem = object_property_get_bool(OBJECT(hostmem), "pmem", NULL);
+ pmem_override = object_property_get_bool(OBJECT(nvdimm),
+ "pmem-override", NULL);
+ if (!is_pmem || pmem_override) {
+ _FDT(fdt_setprop(fdt, child_offset, "ibm,hcall-flush-required",
+ NULL, 0));
+ }
+ }
+
return child_offset;
}
@@ -397,11 +426,21 @@ typedef struct SpaprNVDIMMDeviceFlushState {
typedef struct SpaprNVDIMMDevice SpaprNVDIMMDevice;
struct SpaprNVDIMMDevice {
+ /* private */
NVDIMMDevice parent_obj;
+ bool hcall_flush_required;
uint64_t nvdimm_flush_token;
QLIST_HEAD(, SpaprNVDIMMDeviceFlushState) pending_nvdimm_flush_states;
QLIST_HEAD(, SpaprNVDIMMDeviceFlushState) completed_nvdimm_flush_states;
+
+ /* public */
+
+ /*
+ * The 'on' value for this property forced the qemu to enable the hcall
+ * flush for the nvdimm device even if the backend is a pmem
+ */
+ bool pmem_override;
};
static int flush_worker_cb(void *opaque)
@@ -448,6 +487,24 @@ static int spapr_nvdimm_flush_post_load(void *opaque, int version_id)
SpaprNVDIMMDevice *s_nvdimm = (SpaprNVDIMMDevice *)opaque;
SpaprNVDIMMDeviceFlushState *state;
ThreadPool *pool = aio_get_thread_pool(qemu_get_aio_context());
+ HostMemoryBackend *backend = MEMORY_BACKEND(PC_DIMM(s_nvdimm)->hostmem);
+ bool is_pmem = object_property_get_bool(OBJECT(backend), "pmem", NULL);
+ bool pmem_override = object_property_get_bool(OBJECT(s_nvdimm),
+ "pmem-override", NULL);
+ bool dest_hcall_flush_required = pmem_override || !is_pmem;
+
+ if (!s_nvdimm->hcall_flush_required && dest_hcall_flush_required) {
+ error_report("The file backend for the spapr-nvdimm device %s at "
+ "source is a pmem, use pmem=on and pmem-override=off to "
+ "continue.", DEVICE(s_nvdimm)->id);
+ return -EINVAL;
+ }
+ if (s_nvdimm->hcall_flush_required && !dest_hcall_flush_required) {
+ error_report("The guest expects hcall-flush support for the "
+ "spapr-nvdimm device %s, use pmem_override=on to "
+ "continue.", DEVICE(s_nvdimm)->id);
+ return -EINVAL;
+ }
QLIST_FOREACH(state, &s_nvdimm->pending_nvdimm_flush_states, node) {
thread_pool_submit_aio(pool, flush_worker_cb, state,
@@ -475,6 +532,7 @@ const VMStateDescription vmstate_spapr_nvdimm_states = {
.minimum_version_id = 1,
.post_load = spapr_nvdimm_flush_post_load,
.fields = (VMStateField[]) {
+ VMSTATE_BOOL(hcall_flush_required, SpaprNVDIMMDevice),
VMSTATE_UINT64(nvdimm_flush_token, SpaprNVDIMMDevice),
VMSTATE_QLIST_V(completed_nvdimm_flush_states, SpaprNVDIMMDevice, 1,
vmstate_spapr_nvdimm_flush_state,
@@ -605,7 +663,11 @@ static target_ulong h_scm_flush(PowerPCCPU *cpu, SpaprMachineState *spapr,
}
dimm = PC_DIMM(drc->dev);
+ if (!object_dynamic_cast(OBJECT(dimm), TYPE_SPAPR_NVDIMM)) {
+ return H_PARAMETER;
+ }
if (continue_token == 0) {
+ bool is_pmem = false, pmem_override = false;
backend = MEMORY_BACKEND(dimm->hostmem);
fd = memory_region_get_fd(&backend->mr);
@@ -613,6 +675,13 @@ static target_ulong h_scm_flush(PowerPCCPU *cpu, SpaprMachineState *spapr,
return H_UNSUPPORTED;
}
+ is_pmem = object_property_get_bool(OBJECT(backend), "pmem", NULL);
+ pmem_override = object_property_get_bool(OBJECT(dimm),
+ "pmem-override", NULL);
+ if (is_pmem && !pmem_override) {
+ return H_UNSUPPORTED;
+ }
+
state = spapr_nvdimm_init_new_flush_state(SPAPR_NVDIMM(dimm));
if (!state) {
return H_HARDWARE;
@@ -786,3 +855,66 @@ static void spapr_scm_register_types(void)
}
type_init(spapr_scm_register_types)
+
+static void spapr_nvdimm_realize(NVDIMMDevice *dimm, Error **errp)
+{
+ SpaprNVDIMMDevice *s_nvdimm = SPAPR_NVDIMM(dimm);
+ HostMemoryBackend *backend = MEMORY_BACKEND(PC_DIMM(dimm)->hostmem);
+ bool is_pmem = object_property_get_bool(OBJECT(backend), "pmem", NULL);
+ bool pmem_override = object_property_get_bool(OBJECT(dimm), "pmem-override",
+ NULL);
+ if (!is_pmem || pmem_override) {
+ s_nvdimm->hcall_flush_required = true;
+ }
+
+ vmstate_register(NULL, VMSTATE_INSTANCE_ID_ANY,
+ &vmstate_spapr_nvdimm_states, dimm);
+}
+
+static void spapr_nvdimm_unrealize(NVDIMMDevice *dimm)
+{
+ vmstate_unregister(NULL, &vmstate_spapr_nvdimm_states, dimm);
+}
+
+static Property spapr_nvdimm_properties[] = {
+#ifdef CONFIG_LIBPMEM
+ DEFINE_PROP_BOOL("pmem-override", SpaprNVDIMMDevice, pmem_override, false),
+#endif
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void spapr_nvdimm_class_init(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+ NVDIMMClass *nvc = NVDIMM_CLASS(oc);
+
+ nvc->realize = spapr_nvdimm_realize;
+ nvc->unrealize = spapr_nvdimm_unrealize;
+
+ device_class_set_props(dc, spapr_nvdimm_properties);
+}
+
+static void spapr_nvdimm_init(Object *obj)
+{
+ SpaprNVDIMMDevice *s_nvdimm = SPAPR_NVDIMM(obj);
+
+ s_nvdimm->hcall_flush_required = false;
+ QLIST_INIT(&s_nvdimm->pending_nvdimm_flush_states);
+ QLIST_INIT(&s_nvdimm->completed_nvdimm_flush_states);
+}
+
+static TypeInfo spapr_nvdimm_info = {
+ .name = TYPE_SPAPR_NVDIMM,
+ .parent = TYPE_NVDIMM,
+ .class_init = spapr_nvdimm_class_init,
+ .class_size = sizeof(SPAPRNVDIMMClass),
+ .instance_size = sizeof(SpaprNVDIMMDevice),
+ .instance_init = spapr_nvdimm_init,
+};
+
+static void spapr_nvdimm_register_types(void)
+{
+ type_register_static(&spapr_nvdimm_info);
+}
+
+type_init(spapr_nvdimm_register_types)
--
2.34.1
^ permalink raw reply related [flat|nested] 41+ messages in thread* [PULL 04/39] target/ppc: raise HV interrupts for partition table entry problems
2022-02-18 10:37 [PULL 00/39] ppc queue Cédric Le Goater
` (2 preceding siblings ...)
2022-02-18 10:37 ` [PULL 03/39] spapr: nvdimm: Introduce spapr-nvdimm device Cédric Le Goater
@ 2022-02-18 10:37 ` Cédric Le Goater
2022-02-18 10:37 ` [PULL 05/39] spapr: prevent hdec timer being set up under virtual hypervisor Cédric Le Goater
` (35 subsequent siblings)
39 siblings, 0 replies; 41+ messages in thread
From: Cédric Le Goater @ 2022-02-18 10:37 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Daniel Henrique Barboza, Cédric Le Goater,
Nicholas Piggin, Fabiano Rosas
From: Nicholas Piggin <npiggin@gmail.com>
Invalid or missing partition table entry exceptions should cause HV
interrupts. HDSISR is set to bad MMU config, which is consistent with
the ISA and experimentally matches what POWER9 generates.
Reviewed-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
[ clg: checkpatch fixes ]
Message-Id: <20220216102545.1808018-2-npiggin@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/mmu-radix64.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/target/ppc/mmu-radix64.c b/target/ppc/mmu-radix64.c
index d4e16bd7db50..274494903244 100644
--- a/target/ppc/mmu-radix64.c
+++ b/target/ppc/mmu-radix64.c
@@ -556,13 +556,15 @@ static bool ppc_radix64_xlate_impl(PowerPCCPU *cpu, vaddr eaddr,
} else {
if (!ppc64_v3_get_pate(cpu, lpid, &pate)) {
if (guest_visible) {
- ppc_radix64_raise_si(cpu, access_type, eaddr, DSISR_NOPTE);
+ ppc_radix64_raise_hsi(cpu, access_type, eaddr, eaddr,
+ DSISR_R_BADCONFIG);
}
return false;
}
if (!validate_pate(cpu, lpid, &pate)) {
if (guest_visible) {
- ppc_radix64_raise_si(cpu, access_type, eaddr, DSISR_R_BADCONFIG);
+ ppc_radix64_raise_hsi(cpu, access_type, eaddr, eaddr,
+ DSISR_R_BADCONFIG);
}
return false;
}
--
2.34.1
^ permalink raw reply related [flat|nested] 41+ messages in thread* [PULL 05/39] spapr: prevent hdec timer being set up under virtual hypervisor
2022-02-18 10:37 [PULL 00/39] ppc queue Cédric Le Goater
` (3 preceding siblings ...)
2022-02-18 10:37 ` [PULL 04/39] target/ppc: raise HV interrupts for partition table entry problems Cédric Le Goater
@ 2022-02-18 10:37 ` Cédric Le Goater
2022-02-18 10:37 ` [PULL 06/39] ppc: allow the hdecr timer to be created/destroyed Cédric Le Goater
` (34 subsequent siblings)
39 siblings, 0 replies; 41+ messages in thread
From: Cédric Le Goater @ 2022-02-18 10:37 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Daniel Henrique Barboza, Cédric Le Goater,
Nicholas Piggin
From: Nicholas Piggin <npiggin@gmail.com>
The spapr virtual hypervisor does not require the hdecr timer.
Remove it.
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Message-Id: <20220216102545.1808018-3-npiggin@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/ppc/ppc.c | 2 +-
hw/ppc/spapr_cpu_core.c | 6 +++---
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/ppc/ppc.c b/hw/ppc/ppc.c
index ba7fa0f3b53a..c6dfc5975f5f 100644
--- a/hw/ppc/ppc.c
+++ b/hw/ppc/ppc.c
@@ -1072,7 +1072,7 @@ clk_setup_cb cpu_ppc_tb_init (CPUPPCState *env, uint32_t freq)
}
/* Create new timer */
tb_env->decr_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &cpu_ppc_decr_cb, cpu);
- if (env->has_hv_mode) {
+ if (env->has_hv_mode && !cpu->vhyp) {
tb_env->hdecr_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &cpu_ppc_hdecr_cb,
cpu);
} else {
diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c
index a781e97f8d1d..ed847139602f 100644
--- a/hw/ppc/spapr_cpu_core.c
+++ b/hw/ppc/spapr_cpu_core.c
@@ -261,12 +261,12 @@ static bool spapr_realize_vcpu(PowerPCCPU *cpu, SpaprMachineState *spapr,
return false;
}
- /* Set time-base frequency to 512 MHz */
- cpu_ppc_tb_init(env, SPAPR_TIMEBASE_FREQ);
-
cpu_ppc_set_vhyp(cpu, PPC_VIRTUAL_HYPERVISOR(spapr));
kvmppc_set_papr(cpu);
+ /* Set time-base frequency to 512 MHz. vhyp must be set first. */
+ cpu_ppc_tb_init(env, SPAPR_TIMEBASE_FREQ);
+
if (spapr_irq_cpu_intc_create(spapr, cpu, errp) < 0) {
qdev_unrealize(DEVICE(cpu));
return false;
--
2.34.1
^ permalink raw reply related [flat|nested] 41+ messages in thread* [PULL 06/39] ppc: allow the hdecr timer to be created/destroyed
2022-02-18 10:37 [PULL 00/39] ppc queue Cédric Le Goater
` (4 preceding siblings ...)
2022-02-18 10:37 ` [PULL 05/39] spapr: prevent hdec timer being set up under virtual hypervisor Cédric Le Goater
@ 2022-02-18 10:37 ` Cédric Le Goater
2022-02-18 10:37 ` [PULL 07/39] target/ppc: add vhyp addressing mode helper for radix MMU Cédric Le Goater
` (33 subsequent siblings)
39 siblings, 0 replies; 41+ messages in thread
From: Cédric Le Goater @ 2022-02-18 10:37 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Cédric Le Goater, Nicholas Piggin
From: Nicholas Piggin <npiggin@gmail.com>
Machines which don't emulate the HDEC facility are able to use the
timer for something else. Provide functions to start and stop the
hdecr timer.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
[ clg: checkpatch fixes ]
Message-Id: <20220216102545.1808018-4-npiggin@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
include/hw/ppc/ppc.h | 3 +++
hw/ppc/ppc.c | 21 +++++++++++++++++++++
2 files changed, 24 insertions(+)
diff --git a/include/hw/ppc/ppc.h b/include/hw/ppc/ppc.h
index 93e614cffd03..b0ba4bd6b978 100644
--- a/include/hw/ppc/ppc.h
+++ b/include/hw/ppc/ppc.h
@@ -54,6 +54,9 @@ struct ppc_tb_t {
uint64_t cpu_ppc_get_tb(ppc_tb_t *tb_env, uint64_t vmclk, int64_t tb_offset);
clk_setup_cb cpu_ppc_tb_init (CPUPPCState *env, uint32_t freq);
+void cpu_ppc_hdecr_init(CPUPPCState *env);
+void cpu_ppc_hdecr_exit(CPUPPCState *env);
+
/* Embedded PowerPC DCR management */
typedef uint32_t (*dcr_read_cb)(void *opaque, int dcrn);
typedef void (*dcr_write_cb)(void *opaque, int dcrn, uint32_t val);
diff --git a/hw/ppc/ppc.c b/hw/ppc/ppc.c
index c6dfc5975f5f..9e99625ea93e 100644
--- a/hw/ppc/ppc.c
+++ b/hw/ppc/ppc.c
@@ -1083,6 +1083,27 @@ clk_setup_cb cpu_ppc_tb_init (CPUPPCState *env, uint32_t freq)
return &cpu_ppc_set_tb_clk;
}
+/* cpu_ppc_hdecr_init may be used if the timer is not used by HDEC emulation */
+void cpu_ppc_hdecr_init(CPUPPCState *env)
+{
+ PowerPCCPU *cpu = env_archcpu(env);
+
+ assert(env->tb_env->hdecr_timer == NULL);
+
+ env->tb_env->hdecr_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
+ &cpu_ppc_hdecr_cb, cpu);
+}
+
+void cpu_ppc_hdecr_exit(CPUPPCState *env)
+{
+ PowerPCCPU *cpu = env_archcpu(env);
+
+ timer_free(env->tb_env->hdecr_timer);
+ env->tb_env->hdecr_timer = NULL;
+
+ cpu_ppc_hdecr_lower(cpu);
+}
+
/*****************************************************************************/
/* PowerPC 40x timers */
--
2.34.1
^ permalink raw reply related [flat|nested] 41+ messages in thread* [PULL 07/39] target/ppc: add vhyp addressing mode helper for radix MMU
2022-02-18 10:37 [PULL 00/39] ppc queue Cédric Le Goater
` (5 preceding siblings ...)
2022-02-18 10:37 ` [PULL 06/39] ppc: allow the hdecr timer to be created/destroyed Cédric Le Goater
@ 2022-02-18 10:37 ` Cédric Le Goater
2022-02-18 10:37 ` [PULL 08/39] target/ppc: make vhyp get_pate method take lpid and return success Cédric Le Goater
` (32 subsequent siblings)
39 siblings, 0 replies; 41+ messages in thread
From: Cédric Le Goater @ 2022-02-18 10:37 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Cédric Le Goater, Nicholas Piggin
From: Nicholas Piggin <npiggin@gmail.com>
The radix on vhyp MMU uses a single-level radix table walk, with the
partition scope mapping provided by the flat QEMU machine memory.
A subsequent change will use the two-level radix walk on vhyp in some
situations, so provide a helper which can abstract that logic.
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Message-Id: <20220216102545.1808018-5-npiggin@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/mmu-radix64.c | 19 +++++++++++++++----
1 file changed, 15 insertions(+), 4 deletions(-)
diff --git a/target/ppc/mmu-radix64.c b/target/ppc/mmu-radix64.c
index 274494903244..04690b64828f 100644
--- a/target/ppc/mmu-radix64.c
+++ b/target/ppc/mmu-radix64.c
@@ -354,6 +354,17 @@ static int ppc_radix64_partition_scoped_xlate(PowerPCCPU *cpu,
return 0;
}
+/*
+ * The spapr vhc has a flat partition scope provided by qemu memory.
+ */
+static bool vhyp_flat_addressing(PowerPCCPU *cpu)
+{
+ if (cpu->vhyp) {
+ return true;
+ }
+ return false;
+}
+
static int ppc_radix64_process_scoped_xlate(PowerPCCPU *cpu,
MMUAccessType access_type,
vaddr eaddr, uint64_t pid,
@@ -385,7 +396,7 @@ static int ppc_radix64_process_scoped_xlate(PowerPCCPU *cpu,
}
prtbe_addr = (pate.dw1 & PATE1_R_PRTB) + offset;
- if (cpu->vhyp) {
+ if (vhyp_flat_addressing(cpu)) {
prtbe0 = ldq_phys(cs->as, prtbe_addr);
} else {
/*
@@ -411,7 +422,7 @@ static int ppc_radix64_process_scoped_xlate(PowerPCCPU *cpu,
*g_page_size = PRTBE_R_GET_RTS(prtbe0);
base_addr = prtbe0 & PRTBE_R_RPDB;
nls = prtbe0 & PRTBE_R_RPDS;
- if (msr_hv || cpu->vhyp) {
+ if (msr_hv || vhyp_flat_addressing(cpu)) {
/*
* Can treat process table addresses as real addresses
*/
@@ -515,7 +526,7 @@ static bool ppc_radix64_xlate_impl(PowerPCCPU *cpu, vaddr eaddr,
relocation = !mmuidx_real(mmu_idx);
/* HV or virtual hypervisor Real Mode Access */
- if (!relocation && (mmuidx_hv(mmu_idx) || cpu->vhyp)) {
+ if (!relocation && (mmuidx_hv(mmu_idx) || vhyp_flat_addressing(cpu))) {
/* In real mode top 4 effective addr bits (mostly) ignored */
*raddr = eaddr & 0x0FFFFFFFFFFFFFFFULL;
@@ -594,7 +605,7 @@ static bool ppc_radix64_xlate_impl(PowerPCCPU *cpu, vaddr eaddr,
g_raddr = eaddr & R_EADDR_MASK;
}
- if (cpu->vhyp) {
+ if (vhyp_flat_addressing(cpu)) {
*raddr = g_raddr;
} else {
/*
--
2.34.1
^ permalink raw reply related [flat|nested] 41+ messages in thread* [PULL 08/39] target/ppc: make vhyp get_pate method take lpid and return success
2022-02-18 10:37 [PULL 00/39] ppc queue Cédric Le Goater
` (6 preceding siblings ...)
2022-02-18 10:37 ` [PULL 07/39] target/ppc: add vhyp addressing mode helper for radix MMU Cédric Le Goater
@ 2022-02-18 10:37 ` Cédric Le Goater
2022-02-18 10:37 ` [PULL 09/39] target/ppc: add helper for books vhyp hypercall handler Cédric Le Goater
` (31 subsequent siblings)
39 siblings, 0 replies; 41+ messages in thread
From: Cédric Le Goater @ 2022-02-18 10:37 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Cédric Le Goater, Nicholas Piggin
From: Nicholas Piggin <npiggin@gmail.com>
In prepartion for implementing a full partition table option for
vhyp, update the get_pate method to take an lpid and return a
success/fail indicator.
The spapr implementation currently just asserts lpid is always 0
and always return success.
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
[ clg: checkpatch fixes ]
Message-Id: <20220216102545.1808018-6-npiggin@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/cpu.h | 3 ++-
hw/ppc/spapr.c | 7 ++++++-
target/ppc/mmu-radix64.c | 8 +++++++-
3 files changed, 15 insertions(+), 3 deletions(-)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 555c6b924576..c79ae74f10de 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -1320,7 +1320,8 @@ struct PPCVirtualHypervisorClass {
hwaddr ptex, int n);
void (*hpte_set_c)(PPCVirtualHypervisor *vhyp, hwaddr ptex, uint64_t pte1);
void (*hpte_set_r)(PPCVirtualHypervisor *vhyp, hwaddr ptex, uint64_t pte1);
- void (*get_pate)(PPCVirtualHypervisor *vhyp, ppc_v3_pate_t *entry);
+ bool (*get_pate)(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu,
+ target_ulong lpid, ppc_v3_pate_t *entry);
target_ulong (*encode_hpt_for_kvm_pr)(PPCVirtualHypervisor *vhyp);
void (*cpu_exec_enter)(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu);
void (*cpu_exec_exit)(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu);
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index 92639856635a..4fdff12a9625 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -1309,13 +1309,18 @@ void spapr_set_all_lpcrs(target_ulong value, target_ulong mask)
}
}
-static void spapr_get_pate(PPCVirtualHypervisor *vhyp, ppc_v3_pate_t *entry)
+static bool spapr_get_pate(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu,
+ target_ulong lpid, ppc_v3_pate_t *entry)
{
SpaprMachineState *spapr = SPAPR_MACHINE(vhyp);
+ assert(lpid == 0);
+
/* Copy PATE1:GR into PATE0:HR */
entry->dw0 = spapr->patb_entry & PATE0_HR;
entry->dw1 = spapr->patb_entry;
+
+ return true;
}
#define HPTE(_table, _i) (void *)(((uint64_t *)(_table)) + ((_i) * 2))
diff --git a/target/ppc/mmu-radix64.c b/target/ppc/mmu-radix64.c
index 04690b64828f..9c557c6de97a 100644
--- a/target/ppc/mmu-radix64.c
+++ b/target/ppc/mmu-radix64.c
@@ -563,7 +563,13 @@ static bool ppc_radix64_xlate_impl(PowerPCCPU *cpu, vaddr eaddr,
if (cpu->vhyp) {
PPCVirtualHypervisorClass *vhc;
vhc = PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
- vhc->get_pate(cpu->vhyp, &pate);
+ if (!vhc->get_pate(cpu->vhyp, cpu, lpid, &pate)) {
+ if (guest_visible) {
+ ppc_radix64_raise_hsi(cpu, access_type, eaddr, eaddr,
+ DSISR_R_BADCONFIG);
+ }
+ return false;
+ }
} else {
if (!ppc64_v3_get_pate(cpu, lpid, &pate)) {
if (guest_visible) {
--
2.34.1
^ permalink raw reply related [flat|nested] 41+ messages in thread* [PULL 09/39] target/ppc: add helper for books vhyp hypercall handler
2022-02-18 10:37 [PULL 00/39] ppc queue Cédric Le Goater
` (7 preceding siblings ...)
2022-02-18 10:37 ` [PULL 08/39] target/ppc: make vhyp get_pate method take lpid and return success Cédric Le Goater
@ 2022-02-18 10:37 ` Cédric Le Goater
2022-02-18 10:37 ` [PULL 10/39] target/ppc: Add powerpc_reset_excp_state helper Cédric Le Goater
` (30 subsequent siblings)
39 siblings, 0 replies; 41+ messages in thread
From: Cédric Le Goater @ 2022-02-18 10:37 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Cédric Le Goater, Nicholas Piggin
From: Nicholas Piggin <npiggin@gmail.com>
The virtual hypervisor currently always intercepts and handles
hypercalls but with a future change this will not always be the case.
Add a helper for the test so the logic is abstracted from the mechanism.
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Message-Id: <20220216102545.1808018-7-npiggin@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/excp_helper.c | 14 +++++++++++++-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index fcc83a77015f..6b6ec71bc22a 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -1278,6 +1278,18 @@ static void powerpc_excp_booke(PowerPCCPU *cpu, int excp)
}
#ifdef TARGET_PPC64
+/*
+ * When running under vhyp, hcalls are always intercepted and sent to the
+ * vhc->hypercall handler.
+ */
+static bool books_vhyp_handles_hcall(PowerPCCPU *cpu)
+{
+ if (cpu->vhyp) {
+ return true;
+ }
+ return false;
+}
+
static void powerpc_excp_books(PowerPCCPU *cpu, int excp)
{
CPUState *cs = CPU(cpu);
@@ -1439,7 +1451,7 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int excp)
env->nip += 4;
/* "PAPR mode" built-in hypercall emulation */
- if ((lev == 1) && cpu->vhyp) {
+ if ((lev == 1) && books_vhyp_handles_hcall(cpu)) {
PPCVirtualHypervisorClass *vhc =
PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
vhc->hypercall(cpu->vhyp, cpu);
--
2.34.1
^ permalink raw reply related [flat|nested] 41+ messages in thread* [PULL 10/39] target/ppc: Add powerpc_reset_excp_state helper
2022-02-18 10:37 [PULL 00/39] ppc queue Cédric Le Goater
` (8 preceding siblings ...)
2022-02-18 10:37 ` [PULL 09/39] target/ppc: add helper for books vhyp hypercall handler Cédric Le Goater
@ 2022-02-18 10:37 ` Cédric Le Goater
2022-02-18 10:37 ` [PULL 11/39] target/ppc: Introduce a vhyp framework for nested HV support Cédric Le Goater
` (29 subsequent siblings)
39 siblings, 0 replies; 41+ messages in thread
From: Cédric Le Goater @ 2022-02-18 10:37 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Cédric Le Goater, Nicholas Piggin
From: Nicholas Piggin <npiggin@gmail.com>
This moves the logic to reset the QEMU exception state into its own
function.
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
[ clg: checkpatch fixes ]
Message-Id: <20220216102545.1808018-8-npiggin@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/excp_helper.c | 42 +++++++++++++++++++++-------------------
1 file changed, 22 insertions(+), 20 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 6b6ec71bc22a..7499fa187f6f 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -360,12 +360,21 @@ static void ppc_excp_apply_ail(PowerPCCPU *cpu, int excp, target_ulong msr,
}
#endif
-static void powerpc_set_excp_state(PowerPCCPU *cpu,
- target_ulong vector, target_ulong msr)
+static void powerpc_reset_excp_state(PowerPCCPU *cpu)
{
CPUState *cs = CPU(cpu);
CPUPPCState *env = &cpu->env;
+ /* Reset exception state */
+ cs->exception_index = POWERPC_EXCP_NONE;
+ env->error_code = 0;
+}
+
+static void powerpc_set_excp_state(PowerPCCPU *cpu, target_ulong vector,
+ target_ulong msr)
+{
+ CPUPPCState *env = &cpu->env;
+
assert((msr & env->msr_mask) == msr);
/*
@@ -376,21 +385,20 @@ static void powerpc_set_excp_state(PowerPCCPU *cpu,
* will prevent setting of the HV bit which some exceptions might need
* to do.
*/
+ env->nip = vector;
env->msr = msr;
hreg_compute_hflags(env);
- env->nip = vector;
- /* Reset exception state */
- cs->exception_index = POWERPC_EXCP_NONE;
- env->error_code = 0;
- /* Reset the reservation */
- env->reserve_addr = -1;
+ powerpc_reset_excp_state(cpu);
/*
* Any interrupt is context synchronizing, check if TCG TLB needs
* a delayed flush on ppc64
*/
check_tlb_flush(env, false);
+
+ /* Reset the reservation */
+ env->reserve_addr = -1;
}
static void powerpc_excp_40x(PowerPCCPU *cpu, int excp)
@@ -471,8 +479,7 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int excp)
case POWERPC_EXCP_FP:
if ((msr_fe0 == 0 && msr_fe1 == 0) || msr_fp == 0) {
trace_ppc_excp_fp_ignore();
- cs->exception_index = POWERPC_EXCP_NONE;
- env->error_code = 0;
+ powerpc_reset_excp_state(cpu);
return;
}
env->spr[SPR_40x_ESR] = ESR_FP;
@@ -609,8 +616,7 @@ static void powerpc_excp_6xx(PowerPCCPU *cpu, int excp)
case POWERPC_EXCP_FP:
if ((msr_fe0 == 0 && msr_fe1 == 0) || msr_fp == 0) {
trace_ppc_excp_fp_ignore();
- cs->exception_index = POWERPC_EXCP_NONE;
- env->error_code = 0;
+ powerpc_reset_excp_state(cpu);
return;
}
@@ -783,8 +789,7 @@ static void powerpc_excp_7xx(PowerPCCPU *cpu, int excp)
case POWERPC_EXCP_FP:
if ((msr_fe0 == 0 && msr_fe1 == 0) || msr_fp == 0) {
trace_ppc_excp_fp_ignore();
- cs->exception_index = POWERPC_EXCP_NONE;
- env->error_code = 0;
+ powerpc_reset_excp_state(cpu);
return;
}
@@ -969,8 +974,7 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int excp)
case POWERPC_EXCP_FP:
if ((msr_fe0 == 0 && msr_fe1 == 0) || msr_fp == 0) {
trace_ppc_excp_fp_ignore();
- cs->exception_index = POWERPC_EXCP_NONE;
- env->error_code = 0;
+ powerpc_reset_excp_state(cpu);
return;
}
@@ -1168,8 +1172,7 @@ static void powerpc_excp_booke(PowerPCCPU *cpu, int excp)
case POWERPC_EXCP_FP:
if ((msr_fe0 == 0 && msr_fe1 == 0) || msr_fp == 0) {
trace_ppc_excp_fp_ignore();
- cs->exception_index = POWERPC_EXCP_NONE;
- env->error_code = 0;
+ powerpc_reset_excp_state(cpu);
return;
}
@@ -1406,8 +1409,7 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int excp)
case POWERPC_EXCP_FP:
if ((msr_fe0 == 0 && msr_fe1 == 0) || msr_fp == 0) {
trace_ppc_excp_fp_ignore();
- cs->exception_index = POWERPC_EXCP_NONE;
- env->error_code = 0;
+ powerpc_reset_excp_state(cpu);
return;
}
--
2.34.1
^ permalink raw reply related [flat|nested] 41+ messages in thread* [PULL 11/39] target/ppc: Introduce a vhyp framework for nested HV support
2022-02-18 10:37 [PULL 00/39] ppc queue Cédric Le Goater
` (9 preceding siblings ...)
2022-02-18 10:37 ` [PULL 10/39] target/ppc: Add powerpc_reset_excp_state helper Cédric Le Goater
@ 2022-02-18 10:37 ` Cédric Le Goater
2022-02-18 10:38 ` [PULL 12/39] spapr: implement nested-hv capability for the virtual hypervisor Cédric Le Goater
` (28 subsequent siblings)
39 siblings, 0 replies; 41+ messages in thread
From: Cédric Le Goater @ 2022-02-18 10:37 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Cédric Le Goater, Nicholas Piggin,
Fabiano Rosas
From: Nicholas Piggin <npiggin@gmail.com>
Introduce virtual hypervisor methods that can support a "Nested KVM HV"
implementation using the bare metal 2-level radix MMU, and using HV
exceptions to return from H_ENTER_NESTED (rather than cause interrupts).
HV exceptions can now be raised in the TCG spapr machine when running a
nested KVM HV guest. The main ones are the lev==1 syscall, the hdecr,
hdsi and hisi, hv fu, and hv emu, and h_virt external interrupts.
HV exceptions are intercepted in the exception handler code and instead
of causing interrupts in the guest and switching the machine to HV mode,
they go to the vhyp where it may exit the H_ENTER_NESTED hcall with the
interrupt vector numer as return value as required by the hcall API.
Address translation is provided by the 2-level page table walker that is
implemented for the bare metal radix MMU. The partition scope page table
is pointed to the L1's partition scope by the get_pate vhc method.
Reviewed-by: Fabiano Rosas <farosas@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220216102545.1808018-9-npiggin@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/cpu.h | 7 +++++
hw/ppc/pegasos2.c | 6 ++++
hw/ppc/spapr.c | 6 ++++
target/ppc/excp_helper.c | 64 +++++++++++++++++++++++++++++++++-------
target/ppc/mmu-radix64.c | 11 +++++--
5 files changed, 81 insertions(+), 13 deletions(-)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index c79ae74f10de..2baa750729fd 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -1311,6 +1311,8 @@ PowerPCCPUClass *ppc_cpu_get_family_class(PowerPCCPUClass *pcc);
#ifndef CONFIG_USER_ONLY
struct PPCVirtualHypervisorClass {
InterfaceClass parent;
+ bool (*cpu_in_nested)(PowerPCCPU *cpu);
+ void (*deliver_hv_excp)(PowerPCCPU *cpu, int excp);
void (*hypercall)(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu);
hwaddr (*hpt_mask)(PPCVirtualHypervisor *vhyp);
const ppc_hash_pte64_t *(*map_hptes)(PPCVirtualHypervisor *vhyp,
@@ -1330,6 +1332,11 @@ struct PPCVirtualHypervisorClass {
#define TYPE_PPC_VIRTUAL_HYPERVISOR "ppc-virtual-hypervisor"
DECLARE_OBJ_CHECKERS(PPCVirtualHypervisor, PPCVirtualHypervisorClass,
PPC_VIRTUAL_HYPERVISOR, TYPE_PPC_VIRTUAL_HYPERVISOR)
+
+static inline bool vhyp_cpu_in_nested(PowerPCCPU *cpu)
+{
+ return PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp)->cpu_in_nested(cpu);
+}
#endif /* CONFIG_USER_ONLY */
void ppc_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
diff --git a/hw/ppc/pegasos2.c b/hw/ppc/pegasos2.c
index 298e6b93e2dd..d45008ac7131 100644
--- a/hw/ppc/pegasos2.c
+++ b/hw/ppc/pegasos2.c
@@ -449,6 +449,11 @@ static target_ulong pegasos2_rtas(PowerPCCPU *cpu, Pegasos2MachineState *pm,
}
}
+static bool pegasos2_cpu_in_nested(PowerPCCPU *cpu)
+{
+ return false;
+}
+
static void pegasos2_hypercall(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu)
{
Pegasos2MachineState *pm = PEGASOS2_MACHINE(vhyp);
@@ -504,6 +509,7 @@ static void pegasos2_machine_class_init(ObjectClass *oc, void *data)
mc->default_ram_id = "pegasos2.ram";
mc->default_ram_size = 512 * MiB;
+ vhc->cpu_in_nested = pegasos2_cpu_in_nested;
vhc->hypercall = pegasos2_hypercall;
vhc->cpu_exec_enter = vhyp_nop;
vhc->cpu_exec_exit = vhyp_nop;
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index 4fdff12a9625..51ba8615f281 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -4472,6 +4472,11 @@ PowerPCCPU *spapr_find_cpu(int vcpu_id)
return NULL;
}
+static bool spapr_cpu_in_nested(PowerPCCPU *cpu)
+{
+ return false;
+}
+
static void spapr_cpu_exec_enter(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu)
{
SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu);
@@ -4580,6 +4585,7 @@ static void spapr_machine_class_init(ObjectClass *oc, void *data)
fwc->get_dev_path = spapr_get_fw_dev_path;
nc->nmi_monitor_handler = spapr_nmi;
smc->phb_placement = spapr_phb_placement;
+ vhc->cpu_in_nested = spapr_cpu_in_nested;
vhc->hypercall = emulate_spapr_hypercall;
vhc->hpt_mask = spapr_hpt_mask;
vhc->map_hptes = spapr_map_hptes;
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 7499fa187f6f..f44b9da2a53c 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -1280,6 +1280,18 @@ static void powerpc_excp_booke(PowerPCCPU *cpu, int excp)
powerpc_set_excp_state(cpu, vector, new_msr);
}
+/*
+ * When running a nested HV guest under vhyp, external interrupts are
+ * delivered as HVIRT.
+ */
+static bool books_vhyp_promotes_external_to_hvirt(PowerPCCPU *cpu)
+{
+ if (cpu->vhyp) {
+ return vhyp_cpu_in_nested(cpu);
+ }
+ return false;
+}
+
#ifdef TARGET_PPC64
/*
* When running under vhyp, hcalls are always intercepted and sent to the
@@ -1288,7 +1300,21 @@ static void powerpc_excp_booke(PowerPCCPU *cpu, int excp)
static bool books_vhyp_handles_hcall(PowerPCCPU *cpu)
{
if (cpu->vhyp) {
- return true;
+ return !vhyp_cpu_in_nested(cpu);
+ }
+ return false;
+}
+
+/*
+ * When running a nested KVM HV guest under vhyp, HV exceptions are not
+ * delivered to the guest (because there is no concept of HV support), but
+ * rather they are sent tothe vhyp to exit from the L2 back to the L1 and
+ * return from the H_ENTER_NESTED hypercall.
+ */
+static bool books_vhyp_handles_hv_excp(PowerPCCPU *cpu)
+{
+ if (cpu->vhyp) {
+ return vhyp_cpu_in_nested(cpu);
}
return false;
}
@@ -1541,12 +1567,6 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int excp)
break;
}
- /* Sanity check */
- if (!(env->msr_mask & MSR_HVB) && srr0 == SPR_HSRR0) {
- cpu_abort(cs, "Trying to deliver HV exception (HSRR) %d with "
- "no HV support\n", excp);
- }
-
/*
* Sort out endianness of interrupt, this differs depending on the
* CPU, the HV mode, etc...
@@ -1565,10 +1585,26 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int excp)
env->spr[srr1] = msr;
}
- /* This can update new_msr and vector if AIL applies */
- ppc_excp_apply_ail(cpu, excp, msr, &new_msr, &vector);
+ if ((new_msr & MSR_HVB) && books_vhyp_handles_hv_excp(cpu)) {
+ PPCVirtualHypervisorClass *vhc =
+ PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
+ /* Deliver interrupt to L1 by returning from the H_ENTER_NESTED call */
+ vhc->deliver_hv_excp(cpu, excp);
- powerpc_set_excp_state(cpu, vector, new_msr);
+ powerpc_reset_excp_state(cpu);
+
+ } else {
+ /* Sanity check */
+ if (!(env->msr_mask & MSR_HVB) && srr0 == SPR_HSRR0) {
+ cpu_abort(cs, "Trying to deliver HV exception (HSRR) %d with "
+ "no HV support\n", excp);
+ }
+
+ /* This can update new_msr and vector if AIL applies */
+ ppc_excp_apply_ail(cpu, excp, msr, &new_msr, &vector);
+
+ powerpc_set_excp_state(cpu, vector, new_msr);
+ }
}
#else
static inline void powerpc_excp_books(PowerPCCPU *cpu, int excp)
@@ -1688,7 +1724,11 @@ static void ppc_hw_interrupt(CPUPPCState *env)
/* HEIC blocks delivery to the hypervisor */
if ((async_deliver && !(heic && msr_hv && !msr_pr)) ||
(env->has_hv_mode && msr_hv == 0 && !lpes0)) {
- powerpc_excp(cpu, POWERPC_EXCP_EXTERNAL);
+ if (books_vhyp_promotes_external_to_hvirt(cpu)) {
+ powerpc_excp(cpu, POWERPC_EXCP_HVIRT);
+ } else {
+ powerpc_excp(cpu, POWERPC_EXCP_EXTERNAL);
+ }
return;
}
}
@@ -1798,6 +1838,8 @@ void ppc_cpu_do_fwnmi_machine_check(CPUState *cs, target_ulong vector)
msr |= (1ULL << MSR_LE);
}
+ /* Anything for nested required here? MSR[HV] bit? */
+
powerpc_set_excp_state(cpu, vector, msr);
}
diff --git a/target/ppc/mmu-radix64.c b/target/ppc/mmu-radix64.c
index 9c557c6de97a..67c38f065ba2 100644
--- a/target/ppc/mmu-radix64.c
+++ b/target/ppc/mmu-radix64.c
@@ -355,12 +355,19 @@ static int ppc_radix64_partition_scoped_xlate(PowerPCCPU *cpu,
}
/*
- * The spapr vhc has a flat partition scope provided by qemu memory.
+ * The spapr vhc has a flat partition scope provided by qemu memory when
+ * not nested.
+ *
+ * When running a nested guest, the addressing is 2-level radix on top of the
+ * vhc memory, so it works practically identically to the bare metal 2-level
+ * radix. So that code is selected directly. A cleaner and more flexible nested
+ * hypervisor implementation would allow the vhc to provide a ->nested_xlate()
+ * function but that is not required for the moment.
*/
static bool vhyp_flat_addressing(PowerPCCPU *cpu)
{
if (cpu->vhyp) {
- return true;
+ return !vhyp_cpu_in_nested(cpu);
}
return false;
}
--
2.34.1
^ permalink raw reply related [flat|nested] 41+ messages in thread* [PULL 12/39] spapr: implement nested-hv capability for the virtual hypervisor
2022-02-18 10:37 [PULL 00/39] ppc queue Cédric Le Goater
` (10 preceding siblings ...)
2022-02-18 10:37 ` [PULL 11/39] target/ppc: Introduce a vhyp framework for nested HV support Cédric Le Goater
@ 2022-02-18 10:38 ` Cédric Le Goater
2022-02-18 10:38 ` [PULL 13/39] target/ppc: cpu_init: Remove not implemented comments Cédric Le Goater
` (27 subsequent siblings)
39 siblings, 0 replies; 41+ messages in thread
From: Cédric Le Goater @ 2022-02-18 10:38 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Cédric Le Goater, Nicholas Piggin,
Fabiano Rosas
From: Nicholas Piggin <npiggin@gmail.com>
This implements the Nested KVM HV hcall API for spapr under TCG.
The L2 is switched in when the H_ENTER_NESTED hcall is made, and the
L1 is switched back in returned from the hcall when a HV exception
is sent to the vhyp. Register state is copied in and out according to
the nested KVM HV hcall API specification.
The hdecr timer is started when the L2 is switched in, and it provides
the HDEC / 0x980 return to L1.
The MMU re-uses the bare metal radix 2-level page table walker by
using the get_pate method to point the MMU to the nested partition
table entry. MMU faults due to partition scope errors raise HV
exceptions and accordingly are routed back to the L1.
The MMU does not tag translations for the L1 (direct) vs L2 (nested)
guests, so the TLB is flushed on any L1<->L2 transition (hcall entry
and exit).
Reviewed-by: Fabiano Rosas <farosas@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
[ clg: checkpatch fixes ]
Message-Id: <20220216102545.1808018-10-npiggin@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
include/hw/ppc/spapr.h | 74 ++++++-
include/hw/ppc/spapr_cpu_core.h | 5 +
hw/ppc/spapr.c | 37 +++-
hw/ppc/spapr_caps.c | 14 +-
hw/ppc/spapr_hcall.c | 333 ++++++++++++++++++++++++++++++++
5 files changed, 452 insertions(+), 11 deletions(-)
diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h
index 727b2a0e7fc9..f5c33dcc8616 100644
--- a/include/hw/ppc/spapr.h
+++ b/include/hw/ppc/spapr.h
@@ -197,6 +197,9 @@ struct SpaprMachineState {
bool has_graphics;
uint32_t vsmt; /* Virtual SMT mode (KVM's "core stride") */
+ /* Nested HV support (TCG only) */
+ uint64_t nested_ptcr;
+
Notifier epow_notifier;
QTAILQ_HEAD(, SpaprEventLogEntry) pending_events;
bool use_hotplug_event_source;
@@ -579,7 +582,14 @@ struct SpaprMachineState {
#define KVMPPC_H_UPDATE_DT (KVMPPC_HCALL_BASE + 0x3)
/* 0x4 was used for KVMPPC_H_UPDATE_PHANDLE in SLOF */
#define KVMPPC_H_VOF_CLIENT (KVMPPC_HCALL_BASE + 0x5)
-#define KVMPPC_HCALL_MAX KVMPPC_H_VOF_CLIENT
+
+/* Platform-specific hcalls used for nested HV KVM */
+#define KVMPPC_H_SET_PARTITION_TABLE (KVMPPC_HCALL_BASE + 0x800)
+#define KVMPPC_H_ENTER_NESTED (KVMPPC_HCALL_BASE + 0x804)
+#define KVMPPC_H_TLB_INVALIDATE (KVMPPC_HCALL_BASE + 0x808)
+#define KVMPPC_H_COPY_TOFROM_GUEST (KVMPPC_HCALL_BASE + 0x80C)
+
+#define KVMPPC_HCALL_MAX KVMPPC_H_COPY_TOFROM_GUEST
/*
* The hcall range 0xEF00 to 0xEF80 is reserved for use in facilitating
@@ -589,6 +599,65 @@ struct SpaprMachineState {
#define SVM_H_TPM_COMM 0xEF10
#define SVM_HCALL_MAX SVM_H_TPM_COMM
+/*
+ * Register state for entering a nested guest with H_ENTER_NESTED.
+ * New member must be added at the end.
+ */
+struct kvmppc_hv_guest_state {
+ uint64_t version; /* version of this structure layout, must be first */
+ uint32_t lpid;
+ uint32_t vcpu_token;
+ /* These registers are hypervisor privileged (at least for writing) */
+ uint64_t lpcr;
+ uint64_t pcr;
+ uint64_t amor;
+ uint64_t dpdes;
+ uint64_t hfscr;
+ int64_t tb_offset;
+ uint64_t dawr0;
+ uint64_t dawrx0;
+ uint64_t ciabr;
+ uint64_t hdec_expiry;
+ uint64_t purr;
+ uint64_t spurr;
+ uint64_t ic;
+ uint64_t vtb;
+ uint64_t hdar;
+ uint64_t hdsisr;
+ uint64_t heir;
+ uint64_t asdr;
+ /* These are OS privileged but need to be set late in guest entry */
+ uint64_t srr0;
+ uint64_t srr1;
+ uint64_t sprg[4];
+ uint64_t pidr;
+ uint64_t cfar;
+ uint64_t ppr;
+ /* Version 1 ends here */
+ uint64_t dawr1;
+ uint64_t dawrx1;
+ /* Version 2 ends here */
+};
+
+/* Latest version of hv_guest_state structure */
+#define HV_GUEST_STATE_VERSION 2
+
+/* Linux 64-bit powerpc pt_regs struct, used by nested HV */
+struct kvmppc_pt_regs {
+ uint64_t gpr[32];
+ uint64_t nip;
+ uint64_t msr;
+ uint64_t orig_gpr3; /* Used for restarting system calls */
+ uint64_t ctr;
+ uint64_t link;
+ uint64_t xer;
+ uint64_t ccr;
+ uint64_t softe; /* Soft enabled/disabled */
+ uint64_t trap; /* Reason for being here */
+ uint64_t dar; /* Fault registers */
+ uint64_t dsisr; /* on 4xx/Book-E used for ESR */
+ uint64_t result; /* Result of a system call */
+};
typedef struct SpaprDeviceTreeUpdateHeader {
uint32_t version_id;
@@ -606,6 +675,9 @@ typedef target_ulong (*spapr_hcall_fn)(PowerPCCPU *cpu, SpaprMachineState *sm,
void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn);
target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode,
target_ulong *args);
+
+void spapr_exit_nested(PowerPCCPU *cpu, int excp);
+
target_ulong softmmu_resize_hpt_prepare(PowerPCCPU *cpu, SpaprMachineState *spapr,
target_ulong shift);
target_ulong softmmu_resize_hpt_commit(PowerPCCPU *cpu, SpaprMachineState *spapr,
diff --git a/include/hw/ppc/spapr_cpu_core.h b/include/hw/ppc/spapr_cpu_core.h
index dab3dfc76c0a..b560514560df 100644
--- a/include/hw/ppc/spapr_cpu_core.h
+++ b/include/hw/ppc/spapr_cpu_core.h
@@ -48,6 +48,11 @@ typedef struct SpaprCpuState {
bool prod; /* not migrated, only used to improve dispatch latencies */
struct ICPState *icp;
struct XiveTCTX *tctx;
+
+ /* Fields for nested-HV support */
+ bool in_nested; /* true while the L2 is executing */
+ CPUPPCState *nested_host_state; /* holds the L1 state while L2 executes */
+ int64_t nested_tb_offset; /* L1->L2 TB offset */
} SpaprCpuState;
static inline SpaprCpuState *spapr_cpu_state(PowerPCCPU *cpu)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index 51ba8615f281..f0b75b22bb61 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -1270,6 +1270,8 @@ static void emulate_spapr_hypercall(PPCVirtualHypervisor *vhyp,
/* The TCG path should also be holding the BQL at this point */
g_assert(qemu_mutex_iothread_locked());
+ g_assert(!vhyp_cpu_in_nested(cpu));
+
if (msr_pr) {
hcall_dprintf("Hypercall made with MSR[PR]=1\n");
env->gpr[3] = H_PRIVILEGE;
@@ -1313,12 +1315,34 @@ static bool spapr_get_pate(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu,
target_ulong lpid, ppc_v3_pate_t *entry)
{
SpaprMachineState *spapr = SPAPR_MACHINE(vhyp);
+ SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu);
- assert(lpid == 0);
+ if (!spapr_cpu->in_nested) {
+ assert(lpid == 0);
- /* Copy PATE1:GR into PATE0:HR */
- entry->dw0 = spapr->patb_entry & PATE0_HR;
- entry->dw1 = spapr->patb_entry;
+ /* Copy PATE1:GR into PATE0:HR */
+ entry->dw0 = spapr->patb_entry & PATE0_HR;
+ entry->dw1 = spapr->patb_entry;
+
+ } else {
+ uint64_t patb, pats;
+
+ assert(lpid != 0);
+
+ patb = spapr->nested_ptcr & PTCR_PATB;
+ pats = spapr->nested_ptcr & PTCR_PATS;
+
+ /* Calculate number of entries */
+ pats = 1ull << (pats + 12 - 4);
+ if (pats <= lpid) {
+ return false;
+ }
+
+ /* Grab entry */
+ patb += 16 * lpid;
+ entry->dw0 = ldq_phys(CPU(cpu)->as, patb);
+ entry->dw1 = ldq_phys(CPU(cpu)->as, patb + 8);
+ }
return true;
}
@@ -4474,7 +4498,9 @@ PowerPCCPU *spapr_find_cpu(int vcpu_id)
static bool spapr_cpu_in_nested(PowerPCCPU *cpu)
{
- return false;
+ SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu);
+
+ return spapr_cpu->in_nested;
}
static void spapr_cpu_exec_enter(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu)
@@ -4586,6 +4612,7 @@ static void spapr_machine_class_init(ObjectClass *oc, void *data)
nc->nmi_monitor_handler = spapr_nmi;
smc->phb_placement = spapr_phb_placement;
vhc->cpu_in_nested = spapr_cpu_in_nested;
+ vhc->deliver_hv_excp = spapr_exit_nested;
vhc->hypercall = emulate_spapr_hypercall;
vhc->hpt_mask = spapr_hpt_mask;
vhc->map_hptes = spapr_map_hptes;
diff --git a/hw/ppc/spapr_caps.c b/hw/ppc/spapr_caps.c
index ed7c077a0d90..616743127164 100644
--- a/hw/ppc/spapr_caps.c
+++ b/hw/ppc/spapr_caps.c
@@ -444,19 +444,23 @@ static void cap_nested_kvm_hv_apply(SpaprMachineState *spapr,
{
ERRP_GUARD();
PowerPCCPU *cpu = POWERPC_CPU(first_cpu);
+ CPUPPCState *env = &cpu->env;
if (!val) {
/* capability disabled by default */
return;
}
- if (tcg_enabled()) {
- error_setg(errp, "No Nested KVM-HV support in TCG");
+ if (!(env->insns_flags2 & PPC2_ISA300)) {
+ error_setg(errp, "Nested-HV only supported on POWER9 and later");
error_append_hint(errp, "Try appending -machine cap-nested-hv=off\n");
- } else if (kvm_enabled()) {
+ return;
+ }
+
+ if (kvm_enabled()) {
if (!ppc_check_compat(cpu, CPU_POWERPC_LOGICAL_3_00, 0,
spapr->max_compat_pvr)) {
- error_setg(errp, "Nested KVM-HV only supported on POWER9");
+ error_setg(errp, "Nested-HV only supported on POWER9 and later");
error_append_hint(errp,
"Try appending -machine max-cpu-compat=power9\n");
return;
@@ -464,7 +468,7 @@ static void cap_nested_kvm_hv_apply(SpaprMachineState *spapr,
if (!kvmppc_has_cap_nested_kvm_hv()) {
error_setg(errp,
- "KVM implementation does not support Nested KVM-HV");
+ "KVM implementation does not support Nested-HV");
error_append_hint(errp,
"Try appending -machine cap-nested-hv=off\n");
} else if (kvmppc_set_cap_nested_kvm_hv(val) < 0) {
diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c
index 222c1b6bbdb6..f0082907872c 100644
--- a/hw/ppc/spapr_hcall.c
+++ b/hw/ppc/spapr_hcall.c
@@ -9,6 +9,7 @@
#include "qemu/error-report.h"
#include "exec/exec-all.h"
#include "helper_regs.h"
+#include "hw/ppc/ppc.h"
#include "hw/ppc/spapr.h"
#include "hw/ppc/spapr_cpu_core.h"
#include "mmu-hash64.h"
@@ -1497,6 +1498,333 @@ static void hypercall_register_softmmu(void)
}
#endif
+/* TCG only */
+#define PRTS_MASK 0x1f
+
+static target_ulong h_set_ptbl(PowerPCCPU *cpu,
+ SpaprMachineState *spapr,
+ target_ulong opcode,
+ target_ulong *args)
+{
+ target_ulong ptcr = args[0];
+
+ if (!spapr_get_cap(spapr, SPAPR_CAP_NESTED_KVM_HV)) {
+ return H_FUNCTION;
+ }
+
+ if ((ptcr & PRTS_MASK) + 12 - 4 > 12) {
+ return H_PARAMETER;
+ }
+
+ spapr->nested_ptcr = ptcr; /* Save new partition table */
+
+ return H_SUCCESS;
+}
+
+static target_ulong h_tlb_invalidate(PowerPCCPU *cpu,
+ SpaprMachineState *spapr,
+ target_ulong opcode,
+ target_ulong *args)
+{
+ /*
+ * The spapr virtual hypervisor nested HV implementation retains no L2
+ * translation state except for TLB. And the TLB is always invalidated
+ * across L1<->L2 transitions, so nothing is required here.
+ */
+
+ return H_SUCCESS;
+}
+
+static target_ulong h_copy_tofrom_guest(PowerPCCPU *cpu,
+ SpaprMachineState *spapr,
+ target_ulong opcode,
+ target_ulong *args)
+{
+ /*
+ * This HCALL is not required, L1 KVM will take a slow path and walk the
+ * page tables manually to do the data copy.
+ */
+ return H_FUNCTION;
+}
+
+/*
+ * When this handler returns, the environment is switched to the L2 guest
+ * and TCG begins running that. spapr_exit_nested() performs the switch from
+ * L2 back to L1 and returns from the H_ENTER_NESTED hcall.
+ */
+static target_ulong h_enter_nested(PowerPCCPU *cpu,
+ SpaprMachineState *spapr,
+ target_ulong opcode,
+ target_ulong *args)
+{
+ PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
+ CPUState *cs = CPU(cpu);
+ CPUPPCState *env = &cpu->env;
+ SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu);
+ target_ulong hv_ptr = args[0];
+ target_ulong regs_ptr = args[1];
+ target_ulong hdec, now = cpu_ppc_load_tbl(env);
+ target_ulong lpcr, lpcr_mask;
+ struct kvmppc_hv_guest_state *hvstate;
+ struct kvmppc_hv_guest_state hv_state;
+ struct kvmppc_pt_regs *regs;
+ hwaddr len;
+ uint64_t cr;
+ int i;
+
+ if (spapr->nested_ptcr == 0) {
+ return H_NOT_AVAILABLE;
+ }
+
+ len = sizeof(*hvstate);
+ hvstate = address_space_map(CPU(cpu)->as, hv_ptr, &len, false,
+ MEMTXATTRS_UNSPECIFIED);
+ if (len != sizeof(*hvstate)) {
+ address_space_unmap(CPU(cpu)->as, hvstate, len, 0, false);
+ return H_PARAMETER;
+ }
+
+ memcpy(&hv_state, hvstate, len);
+
+ address_space_unmap(CPU(cpu)->as, hvstate, len, len, false);
+
+ /*
+ * We accept versions 1 and 2. Version 2 fields are unused because TCG
+ * does not implement DAWR*.
+ */
+ if (hv_state.version > HV_GUEST_STATE_VERSION) {
+ return H_PARAMETER;
+ }
+
+ spapr_cpu->nested_host_state = g_try_malloc(sizeof(CPUPPCState));
+ if (!spapr_cpu->nested_host_state) {
+ return H_NO_MEM;
+ }
+
+ memcpy(spapr_cpu->nested_host_state, env, sizeof(CPUPPCState));
+
+ len = sizeof(*regs);
+ regs = address_space_map(CPU(cpu)->as, regs_ptr, &len, false,
+ MEMTXATTRS_UNSPECIFIED);
+ if (!regs || len != sizeof(*regs)) {
+ address_space_unmap(CPU(cpu)->as, regs, len, 0, false);
+ g_free(spapr_cpu->nested_host_state);
+ return H_P2;
+ }
+
+ len = sizeof(env->gpr);
+ assert(len == sizeof(regs->gpr));
+ memcpy(env->gpr, regs->gpr, len);
+
+ env->lr = regs->link;
+ env->ctr = regs->ctr;
+ cpu_write_xer(env, regs->xer);
+
+ cr = regs->ccr;
+ for (i = 7; i >= 0; i--) {
+ env->crf[i] = cr & 15;
+ cr >>= 4;
+ }
+
+ env->msr = regs->msr;
+ env->nip = regs->nip;
+
+ address_space_unmap(CPU(cpu)->as, regs, len, len, false);
+
+ env->cfar = hv_state.cfar;
+
+ assert(env->spr[SPR_LPIDR] == 0);
+ env->spr[SPR_LPIDR] = hv_state.lpid;
+
+ lpcr_mask = LPCR_DPFD | LPCR_ILE | LPCR_AIL | LPCR_LD | LPCR_MER;
+ lpcr = (env->spr[SPR_LPCR] & ~lpcr_mask) | (hv_state.lpcr & lpcr_mask);
+ lpcr |= LPCR_HR | LPCR_UPRT | LPCR_GTSE | LPCR_HVICE | LPCR_HDICE;
+ lpcr &= ~LPCR_LPES0;
+ env->spr[SPR_LPCR] = lpcr & pcc->lpcr_mask;
+
+ env->spr[SPR_PCR] = hv_state.pcr;
+ /* hv_state.amor is not used */
+ env->spr[SPR_DPDES] = hv_state.dpdes;
+ env->spr[SPR_HFSCR] = hv_state.hfscr;
+ hdec = hv_state.hdec_expiry - now;
+ spapr_cpu->nested_tb_offset = hv_state.tb_offset;
+ /* TCG does not implement DAWR*, CIABR, PURR, SPURR, IC, VTB, HEIR SPRs*/
+ env->spr[SPR_SRR0] = hv_state.srr0;
+ env->spr[SPR_SRR1] = hv_state.srr1;
+ env->spr[SPR_SPRG0] = hv_state.sprg[0];
+ env->spr[SPR_SPRG1] = hv_state.sprg[1];
+ env->spr[SPR_SPRG2] = hv_state.sprg[2];
+ env->spr[SPR_SPRG3] = hv_state.sprg[3];
+ env->spr[SPR_BOOKS_PID] = hv_state.pidr;
+ env->spr[SPR_PPR] = hv_state.ppr;
+
+ cpu_ppc_hdecr_init(env);
+ cpu_ppc_store_hdecr(env, hdec);
+
+ /*
+ * The hv_state.vcpu_token is not needed. It is used by the KVM
+ * implementation to remember which L2 vCPU last ran on which physical
+ * CPU so as to invalidate process scope translations if it is moved
+ * between physical CPUs. For now TLBs are always flushed on L1<->L2
+ * transitions so this is not a problem.
+ *
+ * Could validate that the same vcpu_token does not attempt to run on
+ * different L1 vCPUs at the same time, but that would be a L1 KVM bug
+ * and it's not obviously worth a new data structure to do it.
+ */
+
+ env->tb_env->tb_offset += spapr_cpu->nested_tb_offset;
+ spapr_cpu->in_nested = true;
+
+ hreg_compute_hflags(env);
+ tlb_flush(cs);
+ env->reserve_addr = -1; /* Reset the reservation */
+
+ /*
+ * The spapr hcall helper sets env->gpr[3] to the return value, but at
+ * this point the L1 is not returning from the hcall but rather we
+ * start running the L2, so r3 must not be clobbered, so return env->gpr[3]
+ * to leave it unchanged.
+ */
+ return env->gpr[3];
+}
+
+void spapr_exit_nested(PowerPCCPU *cpu, int excp)
+{
+ CPUState *cs = CPU(cpu);
+ CPUPPCState *env = &cpu->env;
+ SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu);
+ target_ulong r3_return = env->excp_vectors[excp]; /* hcall return value */
+ target_ulong hv_ptr = spapr_cpu->nested_host_state->gpr[4];
+ target_ulong regs_ptr = spapr_cpu->nested_host_state->gpr[5];
+ struct kvmppc_hv_guest_state *hvstate;
+ struct kvmppc_pt_regs *regs;
+ hwaddr len;
+ uint64_t cr;
+ int i;
+
+ assert(spapr_cpu->in_nested);
+
+ cpu_ppc_hdecr_exit(env);
+
+ len = sizeof(*hvstate);
+ hvstate = address_space_map(CPU(cpu)->as, hv_ptr, &len, true,
+ MEMTXATTRS_UNSPECIFIED);
+ if (len != sizeof(*hvstate)) {
+ address_space_unmap(CPU(cpu)->as, hvstate, len, 0, true);
+ r3_return = H_PARAMETER;
+ goto out_restore_l1;
+ }
+
+ hvstate->cfar = env->cfar;
+ hvstate->lpcr = env->spr[SPR_LPCR];
+ hvstate->pcr = env->spr[SPR_PCR];
+ hvstate->dpdes = env->spr[SPR_DPDES];
+ hvstate->hfscr = env->spr[SPR_HFSCR];
+
+ if (excp == POWERPC_EXCP_HDSI) {
+ hvstate->hdar = env->spr[SPR_HDAR];
+ hvstate->hdsisr = env->spr[SPR_HDSISR];
+ hvstate->asdr = env->spr[SPR_ASDR];
+ } else if (excp == POWERPC_EXCP_HISI) {
+ hvstate->asdr = env->spr[SPR_ASDR];
+ }
+
+ /* HEIR should be implemented for HV mode and saved here. */
+ hvstate->srr0 = env->spr[SPR_SRR0];
+ hvstate->srr1 = env->spr[SPR_SRR1];
+ hvstate->sprg[0] = env->spr[SPR_SPRG0];
+ hvstate->sprg[1] = env->spr[SPR_SPRG1];
+ hvstate->sprg[2] = env->spr[SPR_SPRG2];
+ hvstate->sprg[3] = env->spr[SPR_SPRG3];
+ hvstate->pidr = env->spr[SPR_BOOKS_PID];
+ hvstate->ppr = env->spr[SPR_PPR];
+
+ /* Is it okay to specify write length larger than actual data written? */
+ address_space_unmap(CPU(cpu)->as, hvstate, len, len, true);
+
+ len = sizeof(*regs);
+ regs = address_space_map(CPU(cpu)->as, regs_ptr, &len, true,
+ MEMTXATTRS_UNSPECIFIED);
+ if (!regs || len != sizeof(*regs)) {
+ address_space_unmap(CPU(cpu)->as, regs, len, 0, true);
+ r3_return = H_P2;
+ goto out_restore_l1;
+ }
+
+ len = sizeof(env->gpr);
+ assert(len == sizeof(regs->gpr));
+ memcpy(regs->gpr, env->gpr, len);
+
+ regs->link = env->lr;
+ regs->ctr = env->ctr;
+ regs->xer = cpu_read_xer(env);
+
+ cr = 0;
+ for (i = 0; i < 8; i++) {
+ cr |= (env->crf[i] & 15) << (4 * (7 - i));
+ }
+ regs->ccr = cr;
+
+ if (excp == POWERPC_EXCP_MCHECK ||
+ excp == POWERPC_EXCP_RESET ||
+ excp == POWERPC_EXCP_SYSCALL) {
+ regs->nip = env->spr[SPR_SRR0];
+ regs->msr = env->spr[SPR_SRR1] & env->msr_mask;
+ } else {
+ regs->nip = env->spr[SPR_HSRR0];
+ regs->msr = env->spr[SPR_HSRR1] & env->msr_mask;
+ }
+
+ /* Is it okay to specify write length larger than actual data written? */
+ address_space_unmap(CPU(cpu)->as, regs, len, len, true);
+
+out_restore_l1:
+ memcpy(env->gpr, spapr_cpu->nested_host_state->gpr, sizeof(env->gpr));
+ env->lr = spapr_cpu->nested_host_state->lr;
+ env->ctr = spapr_cpu->nested_host_state->ctr;
+ memcpy(env->crf, spapr_cpu->nested_host_state->crf, sizeof(env->crf));
+ env->cfar = spapr_cpu->nested_host_state->cfar;
+ env->xer = spapr_cpu->nested_host_state->xer;
+ env->so = spapr_cpu->nested_host_state->so;
+ env->ov = spapr_cpu->nested_host_state->ov;
+ env->ov32 = spapr_cpu->nested_host_state->ov32;
+ env->ca32 = spapr_cpu->nested_host_state->ca32;
+ env->msr = spapr_cpu->nested_host_state->msr;
+ env->nip = spapr_cpu->nested_host_state->nip;
+
+ assert(env->spr[SPR_LPIDR] != 0);
+ env->spr[SPR_LPCR] = spapr_cpu->nested_host_state->spr[SPR_LPCR];
+ env->spr[SPR_LPIDR] = spapr_cpu->nested_host_state->spr[SPR_LPIDR];
+ env->spr[SPR_PCR] = spapr_cpu->nested_host_state->spr[SPR_PCR];
+ env->spr[SPR_DPDES] = 0;
+ env->spr[SPR_HFSCR] = spapr_cpu->nested_host_state->spr[SPR_HFSCR];
+ env->spr[SPR_SRR0] = spapr_cpu->nested_host_state->spr[SPR_SRR0];
+ env->spr[SPR_SRR1] = spapr_cpu->nested_host_state->spr[SPR_SRR1];
+ env->spr[SPR_SPRG0] = spapr_cpu->nested_host_state->spr[SPR_SPRG0];
+ env->spr[SPR_SPRG1] = spapr_cpu->nested_host_state->spr[SPR_SPRG1];
+ env->spr[SPR_SPRG2] = spapr_cpu->nested_host_state->spr[SPR_SPRG2];
+ env->spr[SPR_SPRG3] = spapr_cpu->nested_host_state->spr[SPR_SPRG3];
+ env->spr[SPR_BOOKS_PID] = spapr_cpu->nested_host_state->spr[SPR_BOOKS_PID];
+ env->spr[SPR_PPR] = spapr_cpu->nested_host_state->spr[SPR_PPR];
+
+ /*
+ * Return the interrupt vector address from H_ENTER_NESTED to the L1
+ * (or error code).
+ */
+ env->gpr[3] = r3_return;
+
+ env->tb_env->tb_offset -= spapr_cpu->nested_tb_offset;
+ spapr_cpu->in_nested = false;
+
+ hreg_compute_hflags(env);
+ tlb_flush(cs);
+ env->reserve_addr = -1; /* Reset the reservation */
+
+ g_free(spapr_cpu->nested_host_state);
+ spapr_cpu->nested_host_state = NULL;
+}
+
static void hypercall_register_types(void)
{
hypercall_register_softmmu();
@@ -1552,6 +1880,11 @@ static void hypercall_register_types(void)
spapr_register_hypercall(KVMPPC_H_CAS, h_client_architecture_support);
spapr_register_hypercall(KVMPPC_H_UPDATE_DT, h_update_dt);
+
+ spapr_register_hypercall(KVMPPC_H_SET_PARTITION_TABLE, h_set_ptbl);
+ spapr_register_hypercall(KVMPPC_H_ENTER_NESTED, h_enter_nested);
+ spapr_register_hypercall(KVMPPC_H_TLB_INVALIDATE, h_tlb_invalidate);
+ spapr_register_hypercall(KVMPPC_H_COPY_TOFROM_GUEST, h_copy_tofrom_guest);
}
type_init(hypercall_register_types)
--
2.34.1
^ permalink raw reply related [flat|nested] 41+ messages in thread* [PULL 13/39] target/ppc: cpu_init: Remove not implemented comments
2022-02-18 10:37 [PULL 00/39] ppc queue Cédric Le Goater
` (11 preceding siblings ...)
2022-02-18 10:38 ` [PULL 12/39] spapr: implement nested-hv capability for the virtual hypervisor Cédric Le Goater
@ 2022-02-18 10:38 ` Cédric Le Goater
2022-02-18 10:38 ` [PULL 14/39] target/ppc: cpu_init: Remove G2LE init code Cédric Le Goater
` (26 subsequent siblings)
39 siblings, 0 replies; 41+ messages in thread
From: Cédric Le Goater @ 2022-02-18 10:38 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, David Gibson, Cédric Le Goater, Fabiano Rosas
From: Fabiano Rosas <farosas@linux.ibm.com>
The /* XXX : not implemented */ comments all over cpu_init are
confusing and ambiguous.
Do they mean not implemented by QEMU, not implemented in a specific
access mode? Not implemented by the CPU? Do they apply to just the
register right after or to a whole block? Do they mean we have an
action to take in the future to implement these? Are they only
informative?
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <20220216162426.1885923-2-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/cpu_init.c | 582 ++++++++++++++++++------------------------
1 file changed, 253 insertions(+), 329 deletions(-)
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index d97f7183549f..767994fb8f99 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -466,95 +466,91 @@ static void register_G2_755_sprs(CPUPPCState *env)
static void register_7xx_sprs(CPUPPCState *env)
{
/* Breakpoints */
- /* XXX : not implemented */
spr_register_kvm(env, SPR_DABR, "DABR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
KVM_REG_PPC_DABR, 0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_IABR, "IABR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
/* Cache management */
- /* XXX : not implemented */
spr_register(env, SPR_ICTC, "ICTC",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
/* Performance monitors */
- /* XXX : not implemented */
spr_register(env, SPR_7XX_MMCR0, "MMCR0",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_7XX_MMCR1, "MMCR1",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_7XX_PMC1, "PMC1",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_7XX_PMC2, "PMC2",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_7XX_PMC3, "PMC3",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_7XX_PMC4, "PMC4",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_7XX_SIAR, "SIAR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, SPR_NOACCESS,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_7XX_UMMCR0, "UMMCR0",
&spr_read_ureg, SPR_NOACCESS,
&spr_read_ureg, SPR_NOACCESS,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_7XX_UMMCR1, "UMMCR1",
&spr_read_ureg, SPR_NOACCESS,
&spr_read_ureg, SPR_NOACCESS,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_7XX_UPMC1, "UPMC1",
&spr_read_ureg, SPR_NOACCESS,
&spr_read_ureg, SPR_NOACCESS,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_7XX_UPMC2, "UPMC2",
&spr_read_ureg, SPR_NOACCESS,
&spr_read_ureg, SPR_NOACCESS,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_7XX_UPMC3, "UPMC3",
&spr_read_ureg, SPR_NOACCESS,
&spr_read_ureg, SPR_NOACCESS,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_7XX_UPMC4, "UPMC4",
&spr_read_ureg, SPR_NOACCESS,
&spr_read_ureg, SPR_NOACCESS,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_7XX_USIAR, "USIAR",
&spr_read_ureg, SPR_NOACCESS,
&spr_read_ureg, SPR_NOACCESS,
0x00000000);
/* External access control */
- /* XXX : not implemented */
spr_register(env, SPR_EAR, "EAR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
@@ -609,17 +605,16 @@ static void register_iamr_sprs(CPUPPCState *env)
static void register_thrm_sprs(CPUPPCState *env)
{
/* Thermal management */
- /* XXX : not implemented */
spr_register(env, SPR_THRM1, "THRM1",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_thrm, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_THRM2, "THRM2",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_thrm, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_THRM3, "THRM3",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_thrm, &spr_write_generic,
@@ -635,44 +630,41 @@ static void register_604_sprs(CPUPPCState *env)
&spr_read_generic, &spr_write_pir,
0x00000000);
/* Breakpoints */
- /* XXX : not implemented */
spr_register(env, SPR_IABR, "IABR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register_kvm(env, SPR_DABR, "DABR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
KVM_REG_PPC_DABR, 0x00000000);
/* Performance counters */
- /* XXX : not implemented */
spr_register(env, SPR_7XX_MMCR0, "MMCR0",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_7XX_PMC1, "PMC1",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_7XX_PMC2, "PMC2",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_7XX_SIAR, "SIAR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, SPR_NOACCESS,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_SDA, "SDA",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, SPR_NOACCESS,
0x00000000);
/* External access control */
- /* XXX : not implemented */
spr_register(env, SPR_EAR, "EAR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
@@ -683,13 +675,11 @@ static void register_604_sprs(CPUPPCState *env)
static void register_603_sprs(CPUPPCState *env)
{
/* External access control */
- /* XXX : not implemented */
spr_register(env, SPR_EAR, "EAR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
/* Breakpoints */
- /* XXX : not implemented */
spr_register(env, SPR_IABR, "IABR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
@@ -702,7 +692,6 @@ static void register_G2_sprs(CPUPPCState *env)
{
/* Memory base address */
/* MBAR */
- /* XXX : not implemented */
spr_register(env, SPR_MBAR, "MBAR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
@@ -717,32 +706,31 @@ static void register_G2_sprs(CPUPPCState *env)
&spr_read_generic, &spr_write_generic,
0x00000000);
/* Breakpoints */
- /* XXX : not implemented */
spr_register(env, SPR_DABR, "DABR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_DABR2, "DABR2",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_IABR, "IABR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_IABR2, "IABR2",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_IBCR, "IBCR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_DBCR, "DBCR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
@@ -756,33 +744,32 @@ static void register_74xx_sprs(CPUPPCState *env)
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_pir,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_74XX_MMCR2, "MMCR2",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_74XX_UMMCR2, "UMMCR2",
&spr_read_ureg, SPR_NOACCESS,
&spr_read_ureg, SPR_NOACCESS,
0x00000000);
- /* XXX: not implemented */
+
spr_register(env, SPR_BAMR, "BAMR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_MSSCR0, "MSSCR0",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
/* Hardware implementation registers */
- /* XXX : not implemented */
spr_register(env, SPR_HID0, "HID0",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_HID1, "HID1",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
@@ -792,7 +779,7 @@ static void register_74xx_sprs(CPUPPCState *env)
&spr_read_generic, &spr_write_generic,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_L2CR, "L2CR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, spr_access_nop,
@@ -802,19 +789,16 @@ static void register_74xx_sprs(CPUPPCState *env)
static void register_l3_ctrl(CPUPPCState *env)
{
/* L3CR */
- /* XXX : not implemented */
spr_register(env, SPR_L3CR, "L3CR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
/* L3ITCR0 */
- /* XXX : not implemented */
spr_register(env, SPR_L3ITCR0, "L3ITCR0",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
/* L3PM */
- /* XXX : not implemented */
spr_register(env, SPR_L3PM, "L3PM",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
@@ -901,37 +885,36 @@ static void register_BookE_sprs(CPUPPCState *env, uint64_t ivor_mask)
&spr_read_generic, &spr_write_generic,
0x00000000);
/* Debug */
- /* XXX : not implemented */
spr_register(env, SPR_BOOKE_IAC1, "IAC1",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_BOOKE_IAC2, "IAC2",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_BOOKE_DAC1, "DAC1",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_BOOKE_DAC2, "DAC2",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_BOOKE_DBCR0, "DBCR0",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_40x_dbcr0,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_BOOKE_DBCR1, "DBCR1",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_BOOKE_DBCR2, "DBCR2",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
@@ -944,7 +927,7 @@ static void register_BookE_sprs(CPUPPCState *env, uint64_t ivor_mask)
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_BOOKE_DBSR, "DBSR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_clear,
@@ -1053,7 +1036,6 @@ static void register_BookE206_sprs(CPUPPCState *env, uint32_t mas_mask,
int i;
/* TLB assist registers */
- /* XXX : not implemented */
for (i = 0; i < 8; i++) {
if (mas_mask & (1 << i)) {
spr_register(env, mas_sprn[i], mas_names[i],
@@ -1065,14 +1047,12 @@ static void register_BookE206_sprs(CPUPPCState *env, uint32_t mas_mask,
}
}
if (env->nb_pids > 1) {
- /* XXX : not implemented */
spr_register(env, SPR_BOOKE_PID1, "PID1",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_booke_pid,
0x00000000);
}
if (env->nb_pids > 2) {
- /* XXX : not implemented */
spr_register(env, SPR_BOOKE_PID2, "PID2",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_booke_pid,
@@ -1088,7 +1068,6 @@ static void register_BookE206_sprs(CPUPPCState *env, uint32_t mas_mask,
&spr_read_generic, &spr_write_epsc,
0x00000000);
- /* XXX : not implemented */
spr_register(env, SPR_MMUCFG, "MMUCFG",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, SPR_NOACCESS,
@@ -1131,123 +1110,121 @@ static void register_BookE206_sprs(CPUPPCState *env, uint32_t mas_mask,
static void register_440_sprs(CPUPPCState *env)
{
/* Cache control */
- /* XXX : not implemented */
spr_register(env, SPR_440_DNV0, "DNV0",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_440_DNV1, "DNV1",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_440_DNV2, "DNV2",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_440_DNV3, "DNV3",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_440_DTV0, "DTV0",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_440_DTV1, "DTV1",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_440_DTV2, "DTV2",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_440_DTV3, "DTV3",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_440_DVLIM, "DVLIM",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_440_INV0, "INV0",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_440_INV1, "INV1",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_440_INV2, "INV2",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_440_INV3, "INV3",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_440_ITV0, "ITV0",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_440_ITV1, "ITV1",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_440_ITV2, "ITV2",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_440_ITV3, "ITV3",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_440_IVLIM, "IVLIM",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
/* Cache debug */
- /* XXX : not implemented */
spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, SPR_NOACCESS,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, SPR_NOACCESS,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, SPR_NOACCESS,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, SPR_NOACCESS,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, SPR_NOACCESS,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_440_DBDR, "DBDR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
@@ -1336,23 +1313,22 @@ static void register_405_sprs(CPUPPCState *env)
&spr_read_generic, &spr_write_generic,
0x00700000);
/* Debug interface */
- /* XXX : not implemented */
spr_register(env, SPR_40x_DBCR0, "DBCR0",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_40x_dbcr0,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_405_DBCR1, "DBCR1",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_40x_DBSR, "DBSR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_clear,
/* Last reset was system reset */
0x00000300);
- /* XXX : not implemented */
+
spr_register(env, SPR_40x_DAC1, "DAC1",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
@@ -1361,17 +1337,17 @@ static void register_405_sprs(CPUPPCState *env)
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_405_DVC1, "DVC1",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_405_DVC2, "DVC2",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_40x_IAC1, "IAC1",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
@@ -1380,18 +1356,17 @@ static void register_405_sprs(CPUPPCState *env)
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_405_IAC3, "IAC3",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_405_IAC4, "IAC4",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
/* Storage control */
- /* XXX: TODO: not implemented */
spr_register(env, SPR_405_SLER, "SLER",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_40x_sler,
@@ -1400,7 +1375,7 @@ static void register_405_sprs(CPUPPCState *env)
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_405_SU0R, "SU0R",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
@@ -1446,102 +1421,102 @@ static void register_5xx_8xx_sprs(CPUPPCState *env)
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_decr, &spr_write_decr,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_MPC_EIE, "EIE",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_MPC_EID, "EID",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_MPC_NRI, "NRI",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_MPC_CMPA, "CMPA",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_MPC_CMPB, "CMPB",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_MPC_CMPC, "CMPC",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_MPC_CMPD, "CMPD",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_MPC_ECR, "ECR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_MPC_DER, "DER",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_MPC_COUNTA, "COUNTA",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_MPC_COUNTB, "COUNTB",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_MPC_CMPE, "CMPE",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_MPC_CMPF, "CMPF",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_MPC_CMPG, "CMPG",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_MPC_CMPH, "CMPH",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_MPC_LCTRL1, "LCTRL1",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_MPC_LCTRL2, "LCTRL2",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_MPC_BAR, "BAR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_MPC_DPDR, "DPDR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_MPC_IMMR, "IMMR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
@@ -1550,107 +1525,106 @@ static void register_5xx_8xx_sprs(CPUPPCState *env)
static void register_5xx_sprs(CPUPPCState *env)
{
- /* XXX : not implemented */
spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_RCPU_L2U_RBA0, "L2U_RBA0",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_RCPU_L2U_RBA1, "L2U_RBA1",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_RCPU_L2U_RBA2, "L2U_RBA2",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_RCPU_L2U_RBA3, "L2U_RBA3",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_RCPU_MI_RA0, "MI_RA0",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_RCPU_MI_RA1, "MI_RA1",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_RCPU_MI_RA2, "MI_RA2",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_RCPU_MI_RA3, "MI_RA3",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_RCPU_L2U_RA0, "L2U_RA0",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_RCPU_L2U_RA1, "L2U_RA1",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_RCPU_L2U_RA2, "L2U_RA2",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_RCPU_L2U_RA3, "L2U_RA3",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_RCPU_FPECR, "FPECR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
@@ -1659,127 +1633,127 @@ static void register_5xx_sprs(CPUPPCState *env)
static void register_8xx_sprs(CPUPPCState *env)
{
- /* XXX : not implemented */
+
spr_register(env, SPR_MPC_IC_CST, "IC_CST",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_MPC_IC_ADR, "IC_ADR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_MPC_IC_DAT, "IC_DAT",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_MPC_DC_CST, "DC_CST",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_MPC_DC_ADR, "DC_ADR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_MPC_DC_DAT, "DC_DAT",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_MPC_MI_CTR, "MI_CTR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_MPC_MI_AP, "MI_AP",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_MPC_MI_EPN, "MI_EPN",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_MPC_MI_TWC, "MI_TWC",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_MPC_MI_RPN, "MI_RPN",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_MPC_MI_DBCAM, "MI_DBCAM",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_MPC_MI_DBRAM1, "MI_DBRAM1",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_MPC_MD_CTR, "MD_CTR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_MPC_MD_CASID, "MD_CASID",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_MPC_MD_AP, "MD_AP",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_MPC_MD_EPN, "MD_EPN",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_MPC_MD_TWB, "MD_TWB",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_MPC_MD_TWC, "MD_TWC",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_MPC_MD_RPN, "MD_RPN",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_MPC_MD_TW, "MD_TW",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_MPC_MD_DBCAM, "MD_DBCAM",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_MPC_MD_DBRAM0, "MD_DBRAM0",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_MPC_MD_DBRAM1, "MD_DBRAM1",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
@@ -2393,27 +2367,27 @@ static void init_proc_440EP(CPUPPCState *env)
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_pir,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_BOOKE_IAC3, "IAC3",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_BOOKE_IAC4, "IAC4",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_BOOKE_DVC1, "DVC1",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_BOOKE_DVC2, "DVC2",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_BOOKE_MCSR, "MCSR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
@@ -2426,7 +2400,7 @@ static void init_proc_440EP(CPUPPCState *env)
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_440_CCR1, "CCR1",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
@@ -2535,22 +2509,22 @@ static void init_proc_440GP(CPUPPCState *env)
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_pir,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_BOOKE_IAC3, "IAC3",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_BOOKE_IAC4, "IAC4",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_BOOKE_DVC1, "DVC1",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_BOOKE_DVC2, "DVC2",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
@@ -2618,27 +2592,27 @@ static void init_proc_440x5(CPUPPCState *env)
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_pir,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_BOOKE_IAC3, "IAC3",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_BOOKE_IAC4, "IAC4",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_BOOKE_DVC1, "DVC1",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_BOOKE_DVC2, "DVC2",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_BOOKE_MCSR, "MCSR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
@@ -2651,7 +2625,7 @@ static void init_proc_440x5(CPUPPCState *env)
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_440_CCR1, "CCR1",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
@@ -2843,23 +2817,21 @@ static void init_proc_G2(CPUPPCState *env)
/* Time base */
register_tbl(env);
/* External access control */
- /* XXX : not implemented */
spr_register(env, SPR_EAR, "EAR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
/* Hardware implementation register */
- /* XXX : not implemented */
spr_register(env, SPR_HID0, "HID0",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_HID1, "HID1",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_HID2, "HID2",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
@@ -2922,23 +2894,21 @@ static void init_proc_G2LE(CPUPPCState *env)
/* Time base */
register_tbl(env);
/* External access control */
- /* XXX : not implemented */
spr_register(env, SPR_EAR, "EAR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
/* Hardware implementation register */
- /* XXX : not implemented */
spr_register(env, SPR_HID0, "HID0",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_HID1, "HID1",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_HID2, "HID2",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
@@ -3000,84 +2970,84 @@ static void init_proc_e200(CPUPPCState *env)
/* Time base */
register_tbl(env);
register_BookE_sprs(env, 0x000000070000FFFFULL);
- /* XXX : not implemented */
+
spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
&spr_read_spefscr, &spr_write_spefscr,
&spr_read_spefscr, &spr_write_spefscr,
0x00000000);
/* Memory management */
register_BookE206_sprs(env, 0x0000005D, NULL, 0);
- /* XXX : not implemented */
+
spr_register(env, SPR_HID0, "HID0",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_HID1, "HID1",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_Exxx_ALTCTXCR, "ALTCTXCR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_Exxx_CTXCR, "CTXCR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_Exxx_DBCNT, "DBCNT",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_Exxx_DBCR3, "DBCR3",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
&spr_read_generic, SPR_NOACCESS,
&spr_read_generic, SPR_NOACCESS,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_Exxx_L1FINV0, "L1FINV0",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_BOOKE_IAC3, "IAC3",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_BOOKE_IAC4, "IAC4",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_MMUCSR0, "MMUCSR0",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
@@ -3158,43 +3128,41 @@ static void init_proc_e300(CPUPPCState *env)
/* Time base */
register_tbl(env);
/* hardware implementation registers */
- /* XXX : not implemented */
spr_register(env, SPR_HID0, "HID0",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_HID1, "HID1",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_HID2, "HID2",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
/* Breakpoints */
- /* XXX : not implemented */
spr_register(env, SPR_DABR, "DABR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_DABR2, "DABR2",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_IABR2, "IABR2",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_IBCR, "IBCR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_DBCR, "DBCR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
@@ -3300,7 +3268,7 @@ static void init_proc_e500(CPUPPCState *env, int version)
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_pir,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
&spr_read_spefscr, &spr_write_spefscr,
&spr_read_spefscr, &spr_write_spefscr,
@@ -3360,47 +3328,47 @@ static void init_proc_e500(CPUPPCState *env, int version)
env->spr[SPR_PVR]);
}
register_BookE206_sprs(env, 0x000000DF, tlbncfg, mmucfg);
- /* XXX : not implemented */
+
spr_register(env, SPR_HID0, "HID0",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_HID1, "HID1",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_Exxx_BBEAR, "BBEAR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_Exxx_BBTAR, "BBTAR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_Exxx_MCAR, "MCAR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_BOOKE_MCSR, "MCSR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_Exxx_NPIDR, "NPIDR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
&spr_read_generic, SPR_NOACCESS,
&spr_read_generic, SPR_NOACCESS,
@@ -3720,12 +3688,11 @@ static void init_proc_603(CPUPPCState *env)
/* Time base */
register_tbl(env);
/* hardware implementation registers */
- /* XXX : not implemented */
spr_register(env, SPR_HID0, "HID0",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_HID1, "HID1",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
@@ -3826,7 +3793,6 @@ static void init_proc_604(CPUPPCState *env)
/* Time base */
register_tbl(env);
/* Hardware implementation registers */
- /* XXX : not implemented */
spr_register(env, SPR_HID0, "HID0",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
@@ -3884,17 +3850,17 @@ static void init_proc_604E(CPUPPCState *env)
register_ne_601_sprs(env);
register_sdr1_sprs(env);
register_604_sprs(env);
- /* XXX : not implemented */
+
spr_register(env, SPR_7XX_MMCR1, "MMCR1",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_7XX_PMC3, "PMC3",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_7XX_PMC4, "PMC4",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
@@ -3902,12 +3868,11 @@ static void init_proc_604E(CPUPPCState *env)
/* Time base */
register_tbl(env);
/* Hardware implementation registers */
- /* XXX : not implemented */
spr_register(env, SPR_HID0, "HID0",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_HID1, "HID1",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
@@ -3970,12 +3935,11 @@ static void init_proc_740(CPUPPCState *env)
/* Thermal management */
register_thrm_sprs(env);
/* Hardware implementation registers */
- /* XXX : not implemented */
spr_register(env, SPR_HID0, "HID0",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_HID1, "HID1",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
@@ -4033,7 +3997,7 @@ static void init_proc_750(CPUPPCState *env)
register_ne_601_sprs(env);
register_sdr1_sprs(env);
register_7xx_sprs(env);
- /* XXX : not implemented */
+
spr_register(env, SPR_L2CR, "L2CR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, spr_access_nop,
@@ -4043,12 +4007,11 @@ static void init_proc_750(CPUPPCState *env)
/* Thermal management */
register_thrm_sprs(env);
/* Hardware implementation registers */
- /* XXX : not implemented */
spr_register(env, SPR_HID0, "HID0",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_HID1, "HID1",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
@@ -4110,7 +4073,7 @@ static void init_proc_750cl(CPUPPCState *env)
register_ne_601_sprs(env);
register_sdr1_sprs(env);
register_7xx_sprs(env);
- /* XXX : not implemented */
+
spr_register(env, SPR_L2CR, "L2CR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, spr_access_nop,
@@ -4131,7 +4094,7 @@ static void init_proc_750cl(CPUPPCState *env)
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX: not implemented */
+
spr_register(env, SPR_750_TDCL, "TDCL",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
@@ -4141,7 +4104,6 @@ static void init_proc_750cl(CPUPPCState *env)
&spr_read_generic, &spr_write_generic,
0x00000000);
/* DMA */
- /* XXX : not implemented */
spr_register(env, SPR_750_WPAR, "WPAR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
@@ -4155,63 +4117,61 @@ static void init_proc_750cl(CPUPPCState *env)
&spr_read_generic, &spr_write_generic,
0x00000000);
/* Hardware implementation registers */
- /* XXX : not implemented */
spr_register(env, SPR_HID0, "HID0",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_HID1, "HID1",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_750CL_HID2, "HID2",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_750CL_HID4, "HID4",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
/* Quantization registers */
- /* XXX : not implemented */
spr_register(env, SPR_750_GQR0, "GQR0",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_750_GQR1, "GQR1",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_750_GQR2, "GQR2",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_750_GQR3, "GQR3",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_750_GQR4, "GQR4",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_750_GQR5, "GQR5",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_750_GQR6, "GQR6",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_750_GQR7, "GQR7",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
@@ -4310,7 +4270,7 @@ static void init_proc_750cx(CPUPPCState *env)
register_ne_601_sprs(env);
register_sdr1_sprs(env);
register_7xx_sprs(env);
- /* XXX : not implemented */
+
spr_register(env, SPR_L2CR, "L2CR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, spr_access_nop,
@@ -4319,18 +4279,17 @@ static void init_proc_750cx(CPUPPCState *env)
register_tbl(env);
/* Thermal management */
register_thrm_sprs(env);
- /* This register is not implemented but is present for compatibility */
+
spr_register(env, SPR_SDA, "SDA",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
/* Hardware implementation registers */
- /* XXX : not implemented */
spr_register(env, SPR_HID0, "HID0",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_HID1, "HID1",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
@@ -4390,7 +4349,7 @@ static void init_proc_750fx(CPUPPCState *env)
register_ne_601_sprs(env);
register_sdr1_sprs(env);
register_7xx_sprs(env);
- /* XXX : not implemented */
+
spr_register(env, SPR_L2CR, "L2CR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, spr_access_nop,
@@ -4399,23 +4358,22 @@ static void init_proc_750fx(CPUPPCState *env)
register_tbl(env);
/* Thermal management */
register_thrm_sprs(env);
- /* XXX : not implemented */
+
spr_register(env, SPR_750_THRM4, "THRM4",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
/* Hardware implementation registers */
- /* XXX : not implemented */
spr_register(env, SPR_HID0, "HID0",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_HID1, "HID1",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_750FX_HID2, "HID2",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
@@ -4475,7 +4433,7 @@ static void init_proc_750gx(CPUPPCState *env)
register_ne_601_sprs(env);
register_sdr1_sprs(env);
register_7xx_sprs(env);
- /* XXX : not implemented (XXX: different from 750fx) */
+
spr_register(env, SPR_L2CR, "L2CR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, spr_access_nop,
@@ -4484,23 +4442,22 @@ static void init_proc_750gx(CPUPPCState *env)
register_tbl(env);
/* Thermal management */
register_thrm_sprs(env);
- /* XXX : not implemented */
+
spr_register(env, SPR_750_THRM4, "THRM4",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
/* Hardware implementation registers */
- /* XXX : not implemented (XXX: different from 750fx) */
spr_register(env, SPR_HID0, "HID0",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_HID1, "HID1",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented (XXX: different from 750fx) */
+
spr_register(env, SPR_750FX_HID2, "HID2",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
@@ -4566,17 +4523,16 @@ static void init_proc_745(CPUPPCState *env)
/* Thermal management */
register_thrm_sprs(env);
/* Hardware implementation registers */
- /* XXX : not implemented */
spr_register(env, SPR_HID0, "HID0",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_HID1, "HID1",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_HID2, "HID2",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
@@ -4640,12 +4596,11 @@ static void init_proc_755(CPUPPCState *env)
/* Time base */
register_tbl(env);
/* L2 cache control */
- /* XXX : not implemented */
spr_register(env, SPR_L2CR, "L2CR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, spr_access_nop,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_L2PMCR, "L2PMCR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
@@ -4653,17 +4608,16 @@ static void init_proc_755(CPUPPCState *env)
/* Thermal management */
register_thrm_sprs(env);
/* Hardware implementation registers */
- /* XXX : not implemented */
spr_register(env, SPR_HID0, "HID0",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_HID1, "HID1",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_HID2, "HID2",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
@@ -4728,13 +4682,12 @@ static void init_proc_7400(CPUPPCState *env)
/* 74xx specific SPR */
register_74xx_sprs(env);
vscr_init(env, 0x00010000);
- /* XXX : not implemented */
+
spr_register(env, SPR_UBAMR, "UBAMR",
&spr_read_ureg, SPR_NOACCESS,
&spr_read_ureg, SPR_NOACCESS,
0x00000000);
- /* XXX: this seems not implemented on all revisions. */
- /* XXX : not implemented */
+
spr_register(env, SPR_MSSCR1, "MSSCR1",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
@@ -4805,7 +4758,7 @@ static void init_proc_7410(CPUPPCState *env)
/* 74xx specific SPR */
register_74xx_sprs(env);
vscr_init(env, 0x00010000);
- /* XXX : not implemented */
+
spr_register(env, SPR_UBAMR, "UBAMR",
&spr_read_ureg, SPR_NOACCESS,
&spr_read_ureg, SPR_NOACCESS,
@@ -4813,13 +4766,13 @@ static void init_proc_7410(CPUPPCState *env)
/* Thermal management */
register_thrm_sprs(env);
/* L2PMCR */
- /* XXX : not implemented */
+
spr_register(env, SPR_L2PMCR, "L2PMCR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
/* LDSTDB */
- /* XXX : not implemented */
+
spr_register(env, SPR_LDSTDB, "LDSTDB",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
@@ -4888,46 +4841,42 @@ static void init_proc_7440(CPUPPCState *env)
/* 74xx specific SPR */
register_74xx_sprs(env);
vscr_init(env, 0x00010000);
- /* XXX : not implemented */
+
spr_register(env, SPR_UBAMR, "UBAMR",
&spr_read_ureg, SPR_NOACCESS,
&spr_read_ureg, SPR_NOACCESS,
0x00000000);
/* LDSTCR */
- /* XXX : not implemented */
spr_register(env, SPR_LDSTCR, "LDSTCR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
/* ICTRL */
- /* XXX : not implemented */
spr_register(env, SPR_ICTRL, "ICTRL",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
/* MSSSR0 */
- /* XXX : not implemented */
spr_register(env, SPR_MSSSR0, "MSSSR0",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
/* PMC */
- /* XXX : not implemented */
spr_register(env, SPR_7XX_PMC5, "PMC5",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_7XX_UPMC5, "UPMC5",
&spr_read_ureg, SPR_NOACCESS,
&spr_read_ureg, SPR_NOACCESS,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_7XX_PMC6, "PMC6",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_7XX_UPMC6, "UPMC6",
&spr_read_ureg, SPR_NOACCESS,
&spr_read_ureg, SPR_NOACCESS,
@@ -4999,69 +4948,61 @@ static void init_proc_7450(CPUPPCState *env)
/* Level 3 cache control */
register_l3_ctrl(env);
/* L3ITCR1 */
- /* XXX : not implemented */
spr_register(env, SPR_L3ITCR1, "L3ITCR1",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
/* L3ITCR2 */
- /* XXX : not implemented */
spr_register(env, SPR_L3ITCR2, "L3ITCR2",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
/* L3ITCR3 */
- /* XXX : not implemented */
spr_register(env, SPR_L3ITCR3, "L3ITCR3",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
/* L3OHCR */
- /* XXX : not implemented */
spr_register(env, SPR_L3OHCR, "L3OHCR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_UBAMR, "UBAMR",
&spr_read_ureg, SPR_NOACCESS,
&spr_read_ureg, SPR_NOACCESS,
0x00000000);
/* LDSTCR */
- /* XXX : not implemented */
spr_register(env, SPR_LDSTCR, "LDSTCR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
/* ICTRL */
- /* XXX : not implemented */
spr_register(env, SPR_ICTRL, "ICTRL",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
/* MSSSR0 */
- /* XXX : not implemented */
spr_register(env, SPR_MSSSR0, "MSSSR0",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
/* PMC */
- /* XXX : not implemented */
spr_register(env, SPR_7XX_PMC5, "PMC5",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_7XX_UPMC5, "UPMC5",
&spr_read_ureg, SPR_NOACCESS,
&spr_read_ureg, SPR_NOACCESS,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_7XX_PMC6, "PMC6",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_7XX_UPMC6, "UPMC6",
&spr_read_ureg, SPR_NOACCESS,
&spr_read_ureg, SPR_NOACCESS,
@@ -5131,40 +5072,36 @@ static void init_proc_7445(CPUPPCState *env)
register_74xx_sprs(env);
vscr_init(env, 0x00010000);
/* LDSTCR */
- /* XXX : not implemented */
spr_register(env, SPR_LDSTCR, "LDSTCR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
/* ICTRL */
- /* XXX : not implemented */
spr_register(env, SPR_ICTRL, "ICTRL",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
/* MSSSR0 */
- /* XXX : not implemented */
spr_register(env, SPR_MSSSR0, "MSSSR0",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
/* PMC */
- /* XXX : not implemented */
spr_register(env, SPR_7XX_PMC5, "PMC5",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_7XX_UPMC5, "UPMC5",
&spr_read_ureg, SPR_NOACCESS,
&spr_read_ureg, SPR_NOACCESS,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_7XX_PMC6, "PMC6",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_7XX_UPMC6, "UPMC6",
&spr_read_ureg, SPR_NOACCESS,
&spr_read_ureg, SPR_NOACCESS,
@@ -5270,40 +5207,36 @@ static void init_proc_7455(CPUPPCState *env)
/* Level 3 cache control */
register_l3_ctrl(env);
/* LDSTCR */
- /* XXX : not implemented */
spr_register(env, SPR_LDSTCR, "LDSTCR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
/* ICTRL */
- /* XXX : not implemented */
spr_register(env, SPR_ICTRL, "ICTRL",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
/* MSSSR0 */
- /* XXX : not implemented */
spr_register(env, SPR_MSSSR0, "MSSSR0",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
/* PMC */
- /* XXX : not implemented */
spr_register(env, SPR_7XX_PMC5, "PMC5",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_7XX_UPMC5, "UPMC5",
&spr_read_ureg, SPR_NOACCESS,
&spr_read_ureg, SPR_NOACCESS,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_7XX_PMC6, "PMC6",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_7XX_UPMC6, "UPMC6",
&spr_read_ureg, SPR_NOACCESS,
&spr_read_ureg, SPR_NOACCESS,
@@ -5409,64 +5342,56 @@ static void init_proc_7457(CPUPPCState *env)
/* Level 3 cache control */
register_l3_ctrl(env);
/* L3ITCR1 */
- /* XXX : not implemented */
spr_register(env, SPR_L3ITCR1, "L3ITCR1",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
/* L3ITCR2 */
- /* XXX : not implemented */
spr_register(env, SPR_L3ITCR2, "L3ITCR2",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
/* L3ITCR3 */
- /* XXX : not implemented */
spr_register(env, SPR_L3ITCR3, "L3ITCR3",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
/* L3OHCR */
- /* XXX : not implemented */
spr_register(env, SPR_L3OHCR, "L3OHCR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
/* LDSTCR */
- /* XXX : not implemented */
spr_register(env, SPR_LDSTCR, "LDSTCR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
/* ICTRL */
- /* XXX : not implemented */
spr_register(env, SPR_ICTRL, "ICTRL",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
/* MSSSR0 */
- /* XXX : not implemented */
spr_register(env, SPR_MSSSR0, "MSSSR0",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
/* PMC */
- /* XXX : not implemented */
spr_register(env, SPR_7XX_PMC5, "PMC5",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_7XX_UPMC5, "UPMC5",
&spr_read_ureg, SPR_NOACCESS,
&spr_read_ureg, SPR_NOACCESS,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_7XX_PMC6, "PMC6",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_7XX_UPMC6, "UPMC6",
&spr_read_ureg, SPR_NOACCESS,
&spr_read_ureg, SPR_NOACCESS,
@@ -5569,42 +5494,42 @@ static void init_proc_e600(CPUPPCState *env)
/* 74xx specific SPR */
register_74xx_sprs(env);
vscr_init(env, 0x00010000);
- /* XXX : not implemented */
+
spr_register(env, SPR_UBAMR, "UBAMR",
&spr_read_ureg, SPR_NOACCESS,
&spr_read_ureg, SPR_NOACCESS,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_LDSTCR, "LDSTCR",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_ICTRL, "ICTRL",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_MSSSR0, "MSSSR0",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_7XX_PMC5, "PMC5",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_7XX_UPMC5, "UPMC5",
&spr_read_ureg, SPR_NOACCESS,
&spr_read_ureg, SPR_NOACCESS,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_7XX_PMC6, "PMC6",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* XXX : not implemented */
+
spr_register(env, SPR_7XX_UPMC6, "UPMC6",
&spr_read_ureg, SPR_NOACCESS,
&spr_read_ureg, SPR_NOACCESS,
@@ -5717,7 +5642,6 @@ static int check_pow_970(CPUPPCState *env)
static void register_970_hid_sprs(CPUPPCState *env)
{
/* Hardware implementation registers */
- /* XXX : not implemented */
spr_register(env, SPR_HID0, "HID0",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_clear,
--
2.34.1
^ permalink raw reply related [flat|nested] 41+ messages in thread* [PULL 14/39] target/ppc: cpu_init: Remove G2LE init code
2022-02-18 10:37 [PULL 00/39] ppc queue Cédric Le Goater
` (12 preceding siblings ...)
2022-02-18 10:38 ` [PULL 13/39] target/ppc: cpu_init: Remove not implemented comments Cédric Le Goater
@ 2022-02-18 10:38 ` Cédric Le Goater
2022-02-18 10:38 ` [PULL 15/39] target/ppc: cpu_init: Group registration of generic SPRs Cédric Le Goater
` (25 subsequent siblings)
39 siblings, 0 replies; 41+ messages in thread
From: Cédric Le Goater @ 2022-02-18 10:38 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, David Gibson, Cédric Le Goater, Fabiano Rosas
From: Fabiano Rosas <farosas@linux.ibm.com>
The G2LE CPU initialization code is the same as the G2. Use the latter
for both.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <20220216162426.1885923-3-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/cpu_init.c | 42 +-----------------------------------------
1 file changed, 1 insertion(+), 41 deletions(-)
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 767994fb8f99..ec29ccf473e6 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -2885,53 +2885,13 @@ POWERPC_FAMILY(G2)(ObjectClass *oc, void *data)
POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
}
-static void init_proc_G2LE(CPUPPCState *env)
-{
- register_ne_601_sprs(env);
- register_sdr1_sprs(env);
- register_G2_755_sprs(env);
- register_G2_sprs(env);
- /* Time base */
- register_tbl(env);
- /* External access control */
- spr_register(env, SPR_EAR, "EAR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* Hardware implementation register */
- spr_register(env, SPR_HID0, "HID0",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-
- spr_register(env, SPR_HID1, "HID1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-
- spr_register(env, SPR_HID2, "HID2",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-
- /* Memory management */
- register_low_BATs(env);
- register_high_BATs(env);
- register_6xx_7xx_soft_tlb(env, 64, 2);
- init_excp_G2(env);
- env->dcache_line_size = 32;
- env->icache_line_size = 32;
- /* Allocate hardware IRQ controller */
- ppc6xx_irq_init(env_archcpu(env));
-}
-
POWERPC_FAMILY(G2LE)(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
dc->desc = "PowerPC G2LE";
- pcc->init_proc = init_proc_G2LE;
+ pcc->init_proc = init_proc_G2;
pcc->check_pow = check_pow_hid0;
pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
--
2.34.1
^ permalink raw reply related [flat|nested] 41+ messages in thread* [PULL 15/39] target/ppc: cpu_init: Group registration of generic SPRs
2022-02-18 10:37 [PULL 00/39] ppc queue Cédric Le Goater
` (13 preceding siblings ...)
2022-02-18 10:38 ` [PULL 14/39] target/ppc: cpu_init: Remove G2LE init code Cédric Le Goater
@ 2022-02-18 10:38 ` Cédric Le Goater
2022-02-18 10:38 ` [PULL 16/39] target/ppc: cpu_init: Move Timebase registration into the common function Cédric Le Goater
` (24 subsequent siblings)
39 siblings, 0 replies; 41+ messages in thread
From: Cédric Le Goater @ 2022-02-18 10:38 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, David Gibson, Cédric Le Goater, Fabiano Rosas
From: Fabiano Rosas <farosas@linux.ibm.com>
The top level init_proc calls register_generic_sprs but also registers
some other SPRs outside of that function. Let's group everything into
a single place.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <20220216162426.1885923-4-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/cpu_init.c | 58 ++++++++++++++++++++++++-------------------
1 file changed, 32 insertions(+), 26 deletions(-)
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index ec29ccf473e6..1fb17a5e5112 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -150,8 +150,11 @@ static void _spr_register(CPUPPCState *env, int num, const char *name,
oea_read, oea_write, 0, ival)
/* Generic PowerPC SPRs */
-static void register_generic_sprs(CPUPPCState *env)
+static void register_generic_sprs(PowerPCCPU *cpu)
{
+ PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
+ CPUPPCState *env = &cpu->env;
+
/* Integer processing */
spr_register(env, SPR_XER, "XER",
&spr_read_xer, &spr_write_xer,
@@ -192,6 +195,32 @@ static void register_generic_sprs(CPUPPCState *env)
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
+
+ spr_register(env, SPR_PVR, "PVR",
+ /* Linux permits userspace to read PVR */
+#if defined(CONFIG_LINUX_USER)
+ &spr_read_generic,
+#else
+ SPR_NOACCESS,
+#endif
+ SPR_NOACCESS,
+ &spr_read_generic, SPR_NOACCESS,
+ pcc->pvr);
+
+ /* Register SVR if it's defined to anything else than POWERPC_SVR_NONE */
+ if (pcc->svr != POWERPC_SVR_NONE) {
+ if (pcc->svr & POWERPC_SVR_E500) {
+ spr_register(env, SPR_E500_SVR, "SVR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, SPR_NOACCESS,
+ pcc->svr & ~POWERPC_SVR_E500);
+ } else {
+ spr_register(env, SPR_SVR, "SVR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, SPR_NOACCESS,
+ pcc->svr);
+ }
+ }
}
/* SPR common to all non-embedded PowerPC, including 601 */
@@ -7237,31 +7266,8 @@ static void init_ppc_proc(PowerPCCPU *cpu)
env->tlb_type = TLB_NONE;
#endif
/* Register SPR common to all PowerPC implementations */
- register_generic_sprs(env);
- spr_register(env, SPR_PVR, "PVR",
- /* Linux permits userspace to read PVR */
-#if defined(CONFIG_LINUX_USER)
- &spr_read_generic,
-#else
- SPR_NOACCESS,
-#endif
- SPR_NOACCESS,
- &spr_read_generic, SPR_NOACCESS,
- pcc->pvr);
- /* Register SVR if it's defined to anything else than POWERPC_SVR_NONE */
- if (pcc->svr != POWERPC_SVR_NONE) {
- if (pcc->svr & POWERPC_SVR_E500) {
- spr_register(env, SPR_E500_SVR, "SVR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, SPR_NOACCESS,
- pcc->svr & ~POWERPC_SVR_E500);
- } else {
- spr_register(env, SPR_SVR, "SVR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, SPR_NOACCESS,
- pcc->svr);
- }
- }
+ register_generic_sprs(cpu);
+
/* PowerPC implementation specific initialisations (SPRs, timers, ...) */
(*pcc->init_proc)(env);
--
2.34.1
^ permalink raw reply related [flat|nested] 41+ messages in thread* [PULL 16/39] target/ppc: cpu_init: Move Timebase registration into the common function
2022-02-18 10:37 [PULL 00/39] ppc queue Cédric Le Goater
` (14 preceding siblings ...)
2022-02-18 10:38 ` [PULL 15/39] target/ppc: cpu_init: Group registration of generic SPRs Cédric Le Goater
@ 2022-02-18 10:38 ` Cédric Le Goater
2022-02-18 10:38 ` [PULL 17/39] target/ppc: cpu_init: Avoid nested SPR register functions Cédric Le Goater
` (23 subsequent siblings)
39 siblings, 0 replies; 41+ messages in thread
From: Cédric Le Goater @ 2022-02-18 10:38 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, David Gibson, Cédric Le Goater, Fabiano Rosas
From: Fabiano Rosas <farosas@linux.ibm.com>
Now that the 601 was removed, all of our CPUs have a timebase, so that
can be moved into the common function.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <20220216162426.1885923-5-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/cpu_init.c | 98 ++++++++-----------------------------------
1 file changed, 18 insertions(+), 80 deletions(-)
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 1fb17a5e5112..c6db87fd5c74 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -221,6 +221,24 @@ static void register_generic_sprs(PowerPCCPU *cpu)
pcc->svr);
}
}
+
+ /* Time base */
+ spr_register(env, SPR_VTBL, "TBL",
+ &spr_read_tbl, SPR_NOACCESS,
+ &spr_read_tbl, SPR_NOACCESS,
+ 0x00000000);
+ spr_register(env, SPR_TBL, "TBL",
+ &spr_read_tbl, SPR_NOACCESS,
+ &spr_read_tbl, &spr_write_tbl,
+ 0x00000000);
+ spr_register(env, SPR_VTBU, "TBU",
+ &spr_read_tbu, SPR_NOACCESS,
+ &spr_read_tbu, SPR_NOACCESS,
+ 0x00000000);
+ spr_register(env, SPR_TBU, "TBU",
+ &spr_read_tbu, SPR_NOACCESS,
+ &spr_read_tbu, &spr_write_tbu,
+ 0x00000000);
}
/* SPR common to all non-embedded PowerPC, including 601 */
@@ -409,27 +427,6 @@ static void register_high_BATs(CPUPPCState *env)
#endif
}
-/* Generic PowerPC time base */
-static void register_tbl(CPUPPCState *env)
-{
- spr_register(env, SPR_VTBL, "TBL",
- &spr_read_tbl, SPR_NOACCESS,
- &spr_read_tbl, SPR_NOACCESS,
- 0x00000000);
- spr_register(env, SPR_TBL, "TBL",
- &spr_read_tbl, SPR_NOACCESS,
- &spr_read_tbl, &spr_write_tbl,
- 0x00000000);
- spr_register(env, SPR_VTBU, "TBU",
- &spr_read_tbu, SPR_NOACCESS,
- &spr_read_tbu, SPR_NOACCESS,
- 0x00000000);
- spr_register(env, SPR_TBU, "TBU",
- &spr_read_tbu, SPR_NOACCESS,
- &spr_read_tbu, &spr_write_tbu,
- 0x00000000);
-}
-
/* Softare table search registers */
static void register_6xx_7xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways)
{
@@ -2319,8 +2316,6 @@ static int check_pow_hid0_74xx(CPUPPCState *env)
static void init_proc_405(CPUPPCState *env)
{
- /* Time base */
- register_tbl(env);
register_40x_sprs(env);
register_405_sprs(env);
/* Bus access control */
@@ -2386,8 +2381,6 @@ POWERPC_FAMILY(405)(ObjectClass *oc, void *data)
static void init_proc_440EP(CPUPPCState *env)
{
- /* Time base */
- register_tbl(env);
register_BookE_sprs(env, 0x000000000000FFFFULL);
register_440_sprs(env);
register_usprgh_sprs(env);
@@ -2528,8 +2521,6 @@ POWERPC_FAMILY(460EX)(ObjectClass *oc, void *data)
static void init_proc_440GP(CPUPPCState *env)
{
- /* Time base */
- register_tbl(env);
register_BookE_sprs(env, 0x000000000000FFFFULL);
register_440_sprs(env);
register_usprgh_sprs(env);
@@ -2611,8 +2602,6 @@ POWERPC_FAMILY(440GP)(ObjectClass *oc, void *data)
static void init_proc_440x5(CPUPPCState *env)
{
- /* Time base */
- register_tbl(env);
register_BookE_sprs(env, 0x000000000000FFFFULL);
register_440_sprs(env);
register_usprgh_sprs(env);
@@ -2750,8 +2739,6 @@ POWERPC_FAMILY(440x5wDFPU)(ObjectClass *oc, void *data)
static void init_proc_MPC5xx(CPUPPCState *env)
{
- /* Time base */
- register_tbl(env);
register_5xx_8xx_sprs(env);
register_5xx_sprs(env);
init_excp_MPC5xx(env);
@@ -2794,8 +2781,6 @@ POWERPC_FAMILY(MPC5xx)(ObjectClass *oc, void *data)
static void init_proc_MPC8xx(CPUPPCState *env)
{
- /* Time base */
- register_tbl(env);
register_5xx_8xx_sprs(env);
register_8xx_sprs(env);
init_excp_MPC8xx(env);
@@ -2843,8 +2828,6 @@ static void init_proc_G2(CPUPPCState *env)
register_sdr1_sprs(env);
register_G2_755_sprs(env);
register_G2_sprs(env);
- /* Time base */
- register_tbl(env);
/* External access control */
spr_register(env, SPR_EAR, "EAR",
SPR_NOACCESS, SPR_NOACCESS,
@@ -2956,8 +2939,6 @@ POWERPC_FAMILY(G2LE)(ObjectClass *oc, void *data)
static void init_proc_e200(CPUPPCState *env)
{
- /* Time base */
- register_tbl(env);
register_BookE_sprs(env, 0x000000070000FFFFULL);
spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
@@ -3114,8 +3095,6 @@ static void init_proc_e300(CPUPPCState *env)
register_ne_601_sprs(env);
register_sdr1_sprs(env);
register_603_sprs(env);
- /* Time base */
- register_tbl(env);
/* hardware implementation registers */
spr_register(env, SPR_HID0, "HID0",
SPR_NOACCESS, SPR_NOACCESS,
@@ -3229,8 +3208,6 @@ static void init_proc_e500(CPUPPCState *env, int version)
int i;
#endif
- /* Time base */
- register_tbl(env);
/*
* XXX The e500 doesn't implement IVOR7 and IVOR9, but doesn't
* complain when accessing them.
@@ -3674,8 +3651,6 @@ static void init_proc_603(CPUPPCState *env)
register_ne_601_sprs(env);
register_sdr1_sprs(env);
register_603_sprs(env);
- /* Time base */
- register_tbl(env);
/* hardware implementation registers */
spr_register(env, SPR_HID0, "HID0",
SPR_NOACCESS, SPR_NOACCESS,
@@ -3779,8 +3754,6 @@ static void init_proc_604(CPUPPCState *env)
register_ne_601_sprs(env);
register_sdr1_sprs(env);
register_604_sprs(env);
- /* Time base */
- register_tbl(env);
/* Hardware implementation registers */
spr_register(env, SPR_HID0, "HID0",
SPR_NOACCESS, SPR_NOACCESS,
@@ -3854,8 +3827,6 @@ static void init_proc_604E(CPUPPCState *env)
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* Time base */
- register_tbl(env);
/* Hardware implementation registers */
spr_register(env, SPR_HID0, "HID0",
SPR_NOACCESS, SPR_NOACCESS,
@@ -3919,8 +3890,6 @@ static void init_proc_740(CPUPPCState *env)
register_ne_601_sprs(env);
register_sdr1_sprs(env);
register_7xx_sprs(env);
- /* Time base */
- register_tbl(env);
/* Thermal management */
register_thrm_sprs(env);
/* Hardware implementation registers */
@@ -3991,8 +3960,6 @@ static void init_proc_750(CPUPPCState *env)
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, spr_access_nop,
0x00000000);
- /* Time base */
- register_tbl(env);
/* Thermal management */
register_thrm_sprs(env);
/* Hardware implementation registers */
@@ -4067,8 +4034,6 @@ static void init_proc_750cl(CPUPPCState *env)
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, spr_access_nop,
0x00000000);
- /* Time base */
- register_tbl(env);
/* Thermal management */
/* Those registers are fake on 750CL */
spr_register(env, SPR_THRM1, "THRM1",
@@ -4264,8 +4229,6 @@ static void init_proc_750cx(CPUPPCState *env)
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, spr_access_nop,
0x00000000);
- /* Time base */
- register_tbl(env);
/* Thermal management */
register_thrm_sprs(env);
@@ -4343,8 +4306,6 @@ static void init_proc_750fx(CPUPPCState *env)
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, spr_access_nop,
0x00000000);
- /* Time base */
- register_tbl(env);
/* Thermal management */
register_thrm_sprs(env);
@@ -4427,8 +4388,6 @@ static void init_proc_750gx(CPUPPCState *env)
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, spr_access_nop,
0x00000000);
- /* Time base */
- register_tbl(env);
/* Thermal management */
register_thrm_sprs(env);
@@ -4507,8 +4466,6 @@ static void init_proc_745(CPUPPCState *env)
register_sdr1_sprs(env);
register_7xx_sprs(env);
register_G2_755_sprs(env);
- /* Time base */
- register_tbl(env);
/* Thermal management */
register_thrm_sprs(env);
/* Hardware implementation registers */
@@ -4582,8 +4539,6 @@ static void init_proc_755(CPUPPCState *env)
register_sdr1_sprs(env);
register_7xx_sprs(env);
register_G2_755_sprs(env);
- /* Time base */
- register_tbl(env);
/* L2 cache control */
spr_register(env, SPR_L2CR, "L2CR",
SPR_NOACCESS, SPR_NOACCESS,
@@ -4666,8 +4621,6 @@ static void init_proc_7400(CPUPPCState *env)
register_ne_601_sprs(env);
register_sdr1_sprs(env);
register_7xx_sprs(env);
- /* Time base */
- register_tbl(env);
/* 74xx specific SPR */
register_74xx_sprs(env);
vscr_init(env, 0x00010000);
@@ -4742,8 +4695,6 @@ static void init_proc_7410(CPUPPCState *env)
register_ne_601_sprs(env);
register_sdr1_sprs(env);
register_7xx_sprs(env);
- /* Time base */
- register_tbl(env);
/* 74xx specific SPR */
register_74xx_sprs(env);
vscr_init(env, 0x00010000);
@@ -4825,8 +4776,6 @@ static void init_proc_7440(CPUPPCState *env)
register_ne_601_sprs(env);
register_sdr1_sprs(env);
register_7xx_sprs(env);
- /* Time base */
- register_tbl(env);
/* 74xx specific SPR */
register_74xx_sprs(env);
vscr_init(env, 0x00010000);
@@ -4929,8 +4878,6 @@ static void init_proc_7450(CPUPPCState *env)
register_ne_601_sprs(env);
register_sdr1_sprs(env);
register_7xx_sprs(env);
- /* Time base */
- register_tbl(env);
/* 74xx specific SPR */
register_74xx_sprs(env);
vscr_init(env, 0x00010000);
@@ -5055,8 +5002,6 @@ static void init_proc_7445(CPUPPCState *env)
register_ne_601_sprs(env);
register_sdr1_sprs(env);
register_7xx_sprs(env);
- /* Time base */
- register_tbl(env);
/* 74xx specific SPR */
register_74xx_sprs(env);
vscr_init(env, 0x00010000);
@@ -5188,8 +5133,6 @@ static void init_proc_7455(CPUPPCState *env)
register_ne_601_sprs(env);
register_sdr1_sprs(env);
register_7xx_sprs(env);
- /* Time base */
- register_tbl(env);
/* 74xx specific SPR */
register_74xx_sprs(env);
vscr_init(env, 0x00010000);
@@ -5323,8 +5266,6 @@ static void init_proc_7457(CPUPPCState *env)
register_ne_601_sprs(env);
register_sdr1_sprs(env);
register_7xx_sprs(env);
- /* Time base */
- register_tbl(env);
/* 74xx specific SPR */
register_74xx_sprs(env);
vscr_init(env, 0x00010000);
@@ -5478,8 +5419,6 @@ static void init_proc_e600(CPUPPCState *env)
register_ne_601_sprs(env);
register_sdr1_sprs(env);
register_7xx_sprs(env);
- /* Time base */
- register_tbl(env);
/* 74xx specific SPR */
register_74xx_sprs(env);
vscr_init(env, 0x00010000);
@@ -6303,7 +6242,6 @@ static void init_tcg_pmu_power8(CPUPPCState *env)
static void init_proc_book3s_common(CPUPPCState *env)
{
register_ne_601_sprs(env);
- register_tbl(env);
register_usprg3_sprs(env);
register_book3s_altivec_sprs(env);
register_book3s_pmu_sup_sprs(env);
--
2.34.1
^ permalink raw reply related [flat|nested] 41+ messages in thread* [PULL 17/39] target/ppc: cpu_init: Avoid nested SPR register functions
2022-02-18 10:37 [PULL 00/39] ppc queue Cédric Le Goater
` (15 preceding siblings ...)
2022-02-18 10:38 ` [PULL 16/39] target/ppc: cpu_init: Move Timebase registration into the common function Cédric Le Goater
@ 2022-02-18 10:38 ` Cédric Le Goater
2022-02-18 10:38 ` [PULL 18/39] target/ppc: cpu_init: Move 405 SPRs into register_405_sprs Cédric Le Goater
` (22 subsequent siblings)
39 siblings, 0 replies; 41+ messages in thread
From: Cédric Le Goater @ 2022-02-18 10:38 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, David Gibson, Cédric Le Goater, Fabiano Rosas
From: Fabiano Rosas <farosas@linux.ibm.com>
Make sure that every register_*_sprs function only has calls to
spr_register* to register individual SPRs. Do not allow nesting. This
makes the code easier to follow and a look at init_proc_* should
suffice to know what SPRs a CPU has.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <20220216162426.1885923-6-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/cpu_init.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index c6db87fd5c74..53409a176ac3 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -1128,8 +1128,6 @@ static void register_BookE206_sprs(CPUPPCState *env, uint32_t mas_mask,
break;
}
#endif
-
- register_usprgh_sprs(env);
}
/* SPR specific to PowerPC 440 implementation */
@@ -1427,7 +1425,6 @@ static void register_405_sprs(CPUPPCState *env)
SPR_NOACCESS, SPR_NOACCESS,
spr_read_generic, &spr_write_generic,
0x00000000);
- register_usprgh_sprs(env);
}
@@ -2318,6 +2315,7 @@ static void init_proc_405(CPUPPCState *env)
{
register_40x_sprs(env);
register_405_sprs(env);
+ register_usprgh_sprs(env);
/* Bus access control */
/* not emulated, as QEMU never does speculative access */
spr_register(env, SPR_40x_SGR, "SGR",
@@ -2947,6 +2945,7 @@ static void init_proc_e200(CPUPPCState *env)
0x00000000);
/* Memory management */
register_BookE206_sprs(env, 0x0000005D, NULL, 0);
+ register_usprgh_sprs(env);
spr_register(env, SPR_HID0, "HID0",
SPR_NOACCESS, SPR_NOACCESS,
@@ -3294,6 +3293,7 @@ static void init_proc_e500(CPUPPCState *env, int version)
env->spr[SPR_PVR]);
}
register_BookE206_sprs(env, 0x000000DF, tlbncfg, mmucfg);
+ register_usprgh_sprs(env);
spr_register(env, SPR_HID0, "HID0",
SPR_NOACCESS, SPR_NOACCESS,
--
2.34.1
^ permalink raw reply related [flat|nested] 41+ messages in thread* [PULL 18/39] target/ppc: cpu_init: Move 405 SPRs into register_405_sprs
2022-02-18 10:37 [PULL 00/39] ppc queue Cédric Le Goater
` (16 preceding siblings ...)
2022-02-18 10:38 ` [PULL 17/39] target/ppc: cpu_init: Avoid nested SPR register functions Cédric Le Goater
@ 2022-02-18 10:38 ` Cédric Le Goater
2022-02-18 10:38 ` [PULL 19/39] target/ppc: cpu_init: Move G2 SPRs into register_G2_sprs Cédric Le Goater
` (21 subsequent siblings)
39 siblings, 0 replies; 41+ messages in thread
From: Cédric Le Goater @ 2022-02-18 10:38 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, David Gibson, Cédric Le Goater, Fabiano Rosas
From: Fabiano Rosas <farosas@linux.ibm.com>
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <20220216162426.1885923-7-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/cpu_init.c | 24 +++++++++++++-----------
1 file changed, 13 insertions(+), 11 deletions(-)
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 53409a176ac3..c0990b43a2b3 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -1425,6 +1425,18 @@ static void register_405_sprs(CPUPPCState *env)
SPR_NOACCESS, SPR_NOACCESS,
spr_read_generic, &spr_write_generic,
0x00000000);
+
+ /* Bus access control */
+ /* not emulated, as QEMU never does speculative access */
+ spr_register(env, SPR_40x_SGR, "SGR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0xFFFFFFFF);
+ /* not emulated, as QEMU do not emulate caches */
+ spr_register(env, SPR_40x_DCWR, "DCWR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
}
@@ -2316,17 +2328,7 @@ static void init_proc_405(CPUPPCState *env)
register_40x_sprs(env);
register_405_sprs(env);
register_usprgh_sprs(env);
- /* Bus access control */
- /* not emulated, as QEMU never does speculative access */
- spr_register(env, SPR_40x_SGR, "SGR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0xFFFFFFFF);
- /* not emulated, as QEMU do not emulate caches */
- spr_register(env, SPR_40x_DCWR, "DCWR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
+
/* Memory management */
#if !defined(CONFIG_USER_ONLY)
env->nb_tlb = 64;
--
2.34.1
^ permalink raw reply related [flat|nested] 41+ messages in thread* [PULL 19/39] target/ppc: cpu_init: Move G2 SPRs into register_G2_sprs
2022-02-18 10:37 [PULL 00/39] ppc queue Cédric Le Goater
` (17 preceding siblings ...)
2022-02-18 10:38 ` [PULL 18/39] target/ppc: cpu_init: Move 405 SPRs into register_405_sprs Cédric Le Goater
@ 2022-02-18 10:38 ` Cédric Le Goater
2022-02-18 10:38 ` [PULL 20/39] target/ppc: cpu_init: Decouple G2 SPR registration from 755 Cédric Le Goater
` (20 subsequent siblings)
39 siblings, 0 replies; 41+ messages in thread
From: Cédric Le Goater @ 2022-02-18 10:38 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, David Gibson, Cédric Le Goater, Fabiano Rosas
From: Fabiano Rosas <farosas@linux.ibm.com>
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <20220216162426.1885923-8-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/cpu_init.c | 41 ++++++++++++++++++++++-------------------
1 file changed, 22 insertions(+), 19 deletions(-)
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index c0990b43a2b3..38bcc6b6072e 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -761,6 +761,28 @@ static void register_G2_sprs(CPUPPCState *env)
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
+
+ /* External access control */
+ spr_register(env, SPR_EAR, "EAR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* Hardware implementation register */
+ spr_register(env, SPR_HID0, "HID0",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+
+ spr_register(env, SPR_HID1, "HID1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+
+ spr_register(env, SPR_HID2, "HID2",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+
}
static void register_74xx_sprs(CPUPPCState *env)
@@ -2828,26 +2850,7 @@ static void init_proc_G2(CPUPPCState *env)
register_sdr1_sprs(env);
register_G2_755_sprs(env);
register_G2_sprs(env);
- /* External access control */
- spr_register(env, SPR_EAR, "EAR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* Hardware implementation register */
- spr_register(env, SPR_HID0, "HID0",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-
- spr_register(env, SPR_HID1, "HID1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- spr_register(env, SPR_HID2, "HID2",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
/* Memory management */
register_low_BATs(env);
register_high_BATs(env);
--
2.34.1
^ permalink raw reply related [flat|nested] 41+ messages in thread* [PULL 20/39] target/ppc: cpu_init: Decouple G2 SPR registration from 755
2022-02-18 10:37 [PULL 00/39] ppc queue Cédric Le Goater
` (18 preceding siblings ...)
2022-02-18 10:38 ` [PULL 19/39] target/ppc: cpu_init: Move G2 SPRs into register_G2_sprs Cédric Le Goater
@ 2022-02-18 10:38 ` Cédric Le Goater
2022-02-18 10:38 ` [PULL 21/39] target/ppc: cpu_init: Decouple 74xx SPR registration from 7xx Cédric Le Goater
` (19 subsequent siblings)
39 siblings, 0 replies; 41+ messages in thread
From: Cédric Le Goater @ 2022-02-18 10:38 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, David Gibson, Cédric Le Goater, Fabiano Rosas
From: Fabiano Rosas <farosas@linux.ibm.com>
We're considering these two to be in different CPU families (6xx and
7xx), so keep their SPR registration separate.
The code was copied into register_G2_sprs and the common function was
renamed to apply only to the 755.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <20220216162426.1885923-9-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/cpu_init.c | 25 ++++++++++++++++++++-----
1 file changed, 20 insertions(+), 5 deletions(-)
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 38bcc6b6072e..36d6377a51d2 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -466,8 +466,7 @@ static void register_6xx_7xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways
#endif
}
-/* SPR common to MPC755 and G2 */
-static void register_G2_755_sprs(CPUPPCState *env)
+static void register_755_sprs(CPUPPCState *env)
{
/* SGPRs */
spr_register(env, SPR_SPRG4, "SPRG4",
@@ -783,6 +782,23 @@ static void register_G2_sprs(CPUPPCState *env)
&spr_read_generic, &spr_write_generic,
0x00000000);
+ /* SGPRs */
+ spr_register(env, SPR_SPRG4, "SPRG4",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register(env, SPR_SPRG5, "SPRG5",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register(env, SPR_SPRG6, "SPRG6",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register(env, SPR_SPRG7, "SPRG7",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
}
static void register_74xx_sprs(CPUPPCState *env)
@@ -2848,7 +2864,6 @@ static void init_proc_G2(CPUPPCState *env)
{
register_ne_601_sprs(env);
register_sdr1_sprs(env);
- register_G2_755_sprs(env);
register_G2_sprs(env);
/* Memory management */
@@ -4470,7 +4485,7 @@ static void init_proc_745(CPUPPCState *env)
register_ne_601_sprs(env);
register_sdr1_sprs(env);
register_7xx_sprs(env);
- register_G2_755_sprs(env);
+ register_755_sprs(env);
/* Thermal management */
register_thrm_sprs(env);
/* Hardware implementation registers */
@@ -4543,7 +4558,7 @@ static void init_proc_755(CPUPPCState *env)
register_ne_601_sprs(env);
register_sdr1_sprs(env);
register_7xx_sprs(env);
- register_G2_755_sprs(env);
+ register_755_sprs(env);
/* L2 cache control */
spr_register(env, SPR_L2CR, "L2CR",
SPR_NOACCESS, SPR_NOACCESS,
--
2.34.1
^ permalink raw reply related [flat|nested] 41+ messages in thread* [PULL 21/39] target/ppc: cpu_init: Decouple 74xx SPR registration from 7xx
2022-02-18 10:37 [PULL 00/39] ppc queue Cédric Le Goater
` (19 preceding siblings ...)
2022-02-18 10:38 ` [PULL 20/39] target/ppc: cpu_init: Decouple G2 SPR registration from 755 Cédric Le Goater
@ 2022-02-18 10:38 ` Cédric Le Goater
2022-02-18 10:38 ` [PULL 22/39] target/ppc: cpu_init: Deduplicate 440 SPR registration Cédric Le Goater
` (18 subsequent siblings)
39 siblings, 0 replies; 41+ messages in thread
From: Cédric Le Goater @ 2022-02-18 10:38 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, David Gibson, Cédric Le Goater, Fabiano Rosas
From: Fabiano Rosas <farosas@linux.ibm.com>
We're considering these two to be from different CPU families, so
duplicate some code to keep them separate.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <20220216162426.1885923-10-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/cpu_init.c | 107 +++++++++++++++++++++++++++++++++++-------
1 file changed, 91 insertions(+), 16 deletions(-)
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 36d6377a51d2..5ca0d78dd42f 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -803,6 +803,97 @@ static void register_G2_sprs(CPUPPCState *env)
static void register_74xx_sprs(CPUPPCState *env)
{
+ /* Breakpoints */
+ spr_register_kvm(env, SPR_DABR, "DABR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_DABR, 0x00000000);
+
+ spr_register(env, SPR_IABR, "IABR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* Cache management */
+ spr_register(env, SPR_ICTC, "ICTC",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* Performance monitors */
+ spr_register(env, SPR_7XX_MMCR0, "MMCR0",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+
+ spr_register(env, SPR_7XX_MMCR1, "MMCR1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+
+ spr_register(env, SPR_7XX_PMC1, "PMC1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+
+ spr_register(env, SPR_7XX_PMC2, "PMC2",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+
+ spr_register(env, SPR_7XX_PMC3, "PMC3",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+
+ spr_register(env, SPR_7XX_PMC4, "PMC4",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+
+ spr_register(env, SPR_7XX_SIAR, "SIAR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, SPR_NOACCESS,
+ 0x00000000);
+
+ spr_register(env, SPR_7XX_UMMCR0, "UMMCR0",
+ &spr_read_ureg, SPR_NOACCESS,
+ &spr_read_ureg, SPR_NOACCESS,
+ 0x00000000);
+
+ spr_register(env, SPR_7XX_UMMCR1, "UMMCR1",
+ &spr_read_ureg, SPR_NOACCESS,
+ &spr_read_ureg, SPR_NOACCESS,
+ 0x00000000);
+
+ spr_register(env, SPR_7XX_UPMC1, "UPMC1",
+ &spr_read_ureg, SPR_NOACCESS,
+ &spr_read_ureg, SPR_NOACCESS,
+ 0x00000000);
+
+ spr_register(env, SPR_7XX_UPMC2, "UPMC2",
+ &spr_read_ureg, SPR_NOACCESS,
+ &spr_read_ureg, SPR_NOACCESS,
+ 0x00000000);
+
+ spr_register(env, SPR_7XX_UPMC3, "UPMC3",
+ &spr_read_ureg, SPR_NOACCESS,
+ &spr_read_ureg, SPR_NOACCESS,
+ 0x00000000);
+
+ spr_register(env, SPR_7XX_UPMC4, "UPMC4",
+ &spr_read_ureg, SPR_NOACCESS,
+ &spr_read_ureg, SPR_NOACCESS,
+ 0x00000000);
+
+ spr_register(env, SPR_7XX_USIAR, "USIAR",
+ &spr_read_ureg, SPR_NOACCESS,
+ &spr_read_ureg, SPR_NOACCESS,
+ 0x00000000);
+ /* External access control */
+ spr_register(env, SPR_EAR, "EAR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+
/* Processor identification */
spr_register(env, SPR_PIR, "PIR",
SPR_NOACCESS, SPR_NOACCESS,
@@ -4640,8 +4731,6 @@ static void init_proc_7400(CPUPPCState *env)
{
register_ne_601_sprs(env);
register_sdr1_sprs(env);
- register_7xx_sprs(env);
- /* 74xx specific SPR */
register_74xx_sprs(env);
vscr_init(env, 0x00010000);
@@ -4714,8 +4803,6 @@ static void init_proc_7410(CPUPPCState *env)
{
register_ne_601_sprs(env);
register_sdr1_sprs(env);
- register_7xx_sprs(env);
- /* 74xx specific SPR */
register_74xx_sprs(env);
vscr_init(env, 0x00010000);
@@ -4795,8 +4882,6 @@ static void init_proc_7440(CPUPPCState *env)
{
register_ne_601_sprs(env);
register_sdr1_sprs(env);
- register_7xx_sprs(env);
- /* 74xx specific SPR */
register_74xx_sprs(env);
vscr_init(env, 0x00010000);
@@ -4897,8 +4982,6 @@ static void init_proc_7450(CPUPPCState *env)
{
register_ne_601_sprs(env);
register_sdr1_sprs(env);
- register_7xx_sprs(env);
- /* 74xx specific SPR */
register_74xx_sprs(env);
vscr_init(env, 0x00010000);
/* Level 3 cache control */
@@ -5021,8 +5104,6 @@ static void init_proc_7445(CPUPPCState *env)
{
register_ne_601_sprs(env);
register_sdr1_sprs(env);
- register_7xx_sprs(env);
- /* 74xx specific SPR */
register_74xx_sprs(env);
vscr_init(env, 0x00010000);
/* LDSTCR */
@@ -5152,8 +5233,6 @@ static void init_proc_7455(CPUPPCState *env)
{
register_ne_601_sprs(env);
register_sdr1_sprs(env);
- register_7xx_sprs(env);
- /* 74xx specific SPR */
register_74xx_sprs(env);
vscr_init(env, 0x00010000);
/* Level 3 cache control */
@@ -5285,8 +5364,6 @@ static void init_proc_7457(CPUPPCState *env)
{
register_ne_601_sprs(env);
register_sdr1_sprs(env);
- register_7xx_sprs(env);
- /* 74xx specific SPR */
register_74xx_sprs(env);
vscr_init(env, 0x00010000);
/* Level 3 cache control */
@@ -5438,8 +5515,6 @@ static void init_proc_e600(CPUPPCState *env)
{
register_ne_601_sprs(env);
register_sdr1_sprs(env);
- register_7xx_sprs(env);
- /* 74xx specific SPR */
register_74xx_sprs(env);
vscr_init(env, 0x00010000);
--
2.34.1
^ permalink raw reply related [flat|nested] 41+ messages in thread* [PULL 22/39] target/ppc: cpu_init: Deduplicate 440 SPR registration
2022-02-18 10:37 [PULL 00/39] ppc queue Cédric Le Goater
` (20 preceding siblings ...)
2022-02-18 10:38 ` [PULL 21/39] target/ppc: cpu_init: Decouple 74xx SPR registration from 7xx Cédric Le Goater
@ 2022-02-18 10:38 ` Cédric Le Goater
2022-02-18 10:38 ` [PULL 23/39] target/ppc: cpu_init: Deduplicate 603 " Cédric Le Goater
` (17 subsequent siblings)
39 siblings, 0 replies; 41+ messages in thread
From: Cédric Le Goater @ 2022-02-18 10:38 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, David Gibson, Cédric Le Goater, Fabiano Rosas
From: Fabiano Rosas <farosas@linux.ibm.com>
Move some of the 440 registers that are being repeated in the 440*
CPUs to register_440_sprs.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <20220216162426.1885923-11-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/cpu_init.c | 100 +++++++++++-------------------------------
1 file changed, 26 insertions(+), 74 deletions(-)
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 5ca0d78dd42f..43ba32423cf1 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -1396,6 +1396,32 @@ static void register_440_sprs(CPUPPCState *env)
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
+
+ /* Processor identification */
+ spr_register(env, SPR_BOOKE_PIR, "PIR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_pir,
+ 0x00000000);
+
+ spr_register(env, SPR_BOOKE_IAC3, "IAC3",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+
+ spr_register(env, SPR_BOOKE_IAC4, "IAC4",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+
+ spr_register(env, SPR_BOOKE_DVC1, "DVC1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+
+ spr_register(env, SPR_BOOKE_DVC2, "DVC2",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
}
/* SPR shared between PowerPC 40x implementations */
@@ -2513,31 +2539,6 @@ static void init_proc_440EP(CPUPPCState *env)
register_BookE_sprs(env, 0x000000000000FFFFULL);
register_440_sprs(env);
register_usprgh_sprs(env);
- /* Processor identification */
- spr_register(env, SPR_BOOKE_PIR, "PIR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_pir,
- 0x00000000);
-
- spr_register(env, SPR_BOOKE_IAC3, "IAC3",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-
- spr_register(env, SPR_BOOKE_IAC4, "IAC4",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-
- spr_register(env, SPR_BOOKE_DVC1, "DVC1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-
- spr_register(env, SPR_BOOKE_DVC2, "DVC2",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
spr_register(env, SPR_BOOKE_MCSR, "MCSR",
SPR_NOACCESS, SPR_NOACCESS,
@@ -2653,31 +2654,7 @@ static void init_proc_440GP(CPUPPCState *env)
register_BookE_sprs(env, 0x000000000000FFFFULL);
register_440_sprs(env);
register_usprgh_sprs(env);
- /* Processor identification */
- spr_register(env, SPR_BOOKE_PIR, "PIR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_pir,
- 0x00000000);
- spr_register(env, SPR_BOOKE_IAC3, "IAC3",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-
- spr_register(env, SPR_BOOKE_IAC4, "IAC4",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-
- spr_register(env, SPR_BOOKE_DVC1, "DVC1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-
- spr_register(env, SPR_BOOKE_DVC2, "DVC2",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
/* Memory management */
#if !defined(CONFIG_USER_ONLY)
env->nb_tlb = 64;
@@ -2734,31 +2711,6 @@ static void init_proc_440x5(CPUPPCState *env)
register_BookE_sprs(env, 0x000000000000FFFFULL);
register_440_sprs(env);
register_usprgh_sprs(env);
- /* Processor identification */
- spr_register(env, SPR_BOOKE_PIR, "PIR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_pir,
- 0x00000000);
-
- spr_register(env, SPR_BOOKE_IAC3, "IAC3",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-
- spr_register(env, SPR_BOOKE_IAC4, "IAC4",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-
- spr_register(env, SPR_BOOKE_DVC1, "DVC1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-
- spr_register(env, SPR_BOOKE_DVC2, "DVC2",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
spr_register(env, SPR_BOOKE_MCSR, "MCSR",
SPR_NOACCESS, SPR_NOACCESS,
--
2.34.1
^ permalink raw reply related [flat|nested] 41+ messages in thread* [PULL 23/39] target/ppc: cpu_init: Deduplicate 603 SPR registration
2022-02-18 10:37 [PULL 00/39] ppc queue Cédric Le Goater
` (21 preceding siblings ...)
2022-02-18 10:38 ` [PULL 22/39] target/ppc: cpu_init: Deduplicate 440 SPR registration Cédric Le Goater
@ 2022-02-18 10:38 ` Cédric Le Goater
2022-02-18 10:38 ` [PULL 24/39] target/ppc: cpu_init: Deduplicate 604 " Cédric Le Goater
` (16 subsequent siblings)
39 siblings, 0 replies; 41+ messages in thread
From: Cédric Le Goater @ 2022-02-18 10:38 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, David Gibson, Cédric Le Goater, Fabiano Rosas
From: Fabiano Rosas <farosas@linux.ibm.com>
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <20220216162426.1885923-12-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/cpu_init.c | 28 +++++++++-------------------
1 file changed, 9 insertions(+), 19 deletions(-)
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 43ba32423cf1..017a3b4b2979 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -710,6 +710,15 @@ static void register_603_sprs(CPUPPCState *env)
&spr_read_generic, &spr_write_generic,
0x00000000);
+ spr_register(env, SPR_HID0, "HID0",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+
+ spr_register(env, SPR_HID1, "HID1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
}
/* SPR specific to PowerPC G2 implementation */
@@ -3158,16 +3167,6 @@ static void init_proc_e300(CPUPPCState *env)
register_sdr1_sprs(env);
register_603_sprs(env);
/* hardware implementation registers */
- spr_register(env, SPR_HID0, "HID0",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-
- spr_register(env, SPR_HID1, "HID1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-
spr_register(env, SPR_HID2, "HID2",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
@@ -3714,16 +3713,7 @@ static void init_proc_603(CPUPPCState *env)
register_ne_601_sprs(env);
register_sdr1_sprs(env);
register_603_sprs(env);
- /* hardware implementation registers */
- spr_register(env, SPR_HID0, "HID0",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- spr_register(env, SPR_HID1, "HID1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
/* Memory management */
register_low_BATs(env);
register_6xx_7xx_soft_tlb(env, 64, 2);
--
2.34.1
^ permalink raw reply related [flat|nested] 41+ messages in thread* [PULL 24/39] target/ppc: cpu_init: Deduplicate 604 SPR registration
2022-02-18 10:37 [PULL 00/39] ppc queue Cédric Le Goater
` (22 preceding siblings ...)
2022-02-18 10:38 ` [PULL 23/39] target/ppc: cpu_init: Deduplicate 603 " Cédric Le Goater
@ 2022-02-18 10:38 ` Cédric Le Goater
2022-02-18 10:38 ` [PULL 25/39] target/ppc: cpu_init: Deduplicate 745/755 " Cédric Le Goater
` (15 subsequent siblings)
39 siblings, 0 replies; 41+ messages in thread
From: Cédric Le Goater @ 2022-02-18 10:38 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, David Gibson, Cédric Le Goater, Fabiano Rosas
From: Fabiano Rosas <farosas@linux.ibm.com>
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <20220216162426.1885923-13-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/cpu_init.c | 17 +++++++----------
1 file changed, 7 insertions(+), 10 deletions(-)
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 017a3b4b2979..970dc4ed0d73 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -694,6 +694,12 @@ static void register_604_sprs(CPUPPCState *env)
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
+
+ /* Hardware implementation registers */
+ spr_register(env, SPR_HID0, "HID0",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
}
/* SPR specific to PowerPC 603 implementation */
@@ -3807,11 +3813,7 @@ static void init_proc_604(CPUPPCState *env)
register_ne_601_sprs(env);
register_sdr1_sprs(env);
register_604_sprs(env);
- /* Hardware implementation registers */
- spr_register(env, SPR_HID0, "HID0",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
+
/* Memory management */
register_low_BATs(env);
init_excp_604(env);
@@ -3881,11 +3883,6 @@ static void init_proc_604E(CPUPPCState *env)
&spr_read_generic, &spr_write_generic,
0x00000000);
/* Hardware implementation registers */
- spr_register(env, SPR_HID0, "HID0",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-
spr_register(env, SPR_HID1, "HID1",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
--
2.34.1
^ permalink raw reply related [flat|nested] 41+ messages in thread* [PULL 25/39] target/ppc: cpu_init: Deduplicate 745/755 SPR registration
2022-02-18 10:37 [PULL 00/39] ppc queue Cédric Le Goater
` (23 preceding siblings ...)
2022-02-18 10:38 ` [PULL 24/39] target/ppc: cpu_init: Deduplicate 604 " Cédric Le Goater
@ 2022-02-18 10:38 ` Cédric Le Goater
2022-02-18 10:38 ` [PULL 26/39] target/ppc: cpu_init: Deduplicate 7xx " Cédric Le Goater
` (14 subsequent siblings)
39 siblings, 0 replies; 41+ messages in thread
From: Cédric Le Goater @ 2022-02-18 10:38 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, David Gibson, Cédric Le Goater, Fabiano Rosas
From: Fabiano Rosas <farosas@linux.ibm.com>
The 745 and 755 can share the HID registration, so move it all into
register_755_sprs, which applies for both CPUs.
Also rename that function to register_745_sprs, since the 745 is the
earliest of the two. This will help with separating 755-specific
registers in a subsequent patch.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <20220216162426.1885923-14-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/cpu_init.c | 50 ++++++++++++++++---------------------------
1 file changed, 19 insertions(+), 31 deletions(-)
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 970dc4ed0d73..43289a429fa8 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -466,7 +466,7 @@ static void register_6xx_7xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways
#endif
}
-static void register_755_sprs(CPUPPCState *env)
+static void register_745_sprs(CPUPPCState *env)
{
/* SGPRs */
spr_register(env, SPR_SPRG4, "SPRG4",
@@ -485,6 +485,22 @@ static void register_755_sprs(CPUPPCState *env)
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
+
+ /* Hardware implementation registers */
+ spr_register(env, SPR_HID0, "HID0",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+
+ spr_register(env, SPR_HID1, "HID1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+
+ spr_register(env, SPR_HID2, "HID2",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
}
/* SPR common to all 7xx PowerPC implementations */
@@ -4515,24 +4531,10 @@ static void init_proc_745(CPUPPCState *env)
register_ne_601_sprs(env);
register_sdr1_sprs(env);
register_7xx_sprs(env);
- register_755_sprs(env);
+ register_745_sprs(env);
/* Thermal management */
register_thrm_sprs(env);
- /* Hardware implementation registers */
- spr_register(env, SPR_HID0, "HID0",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-
- spr_register(env, SPR_HID1, "HID1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- spr_register(env, SPR_HID2, "HID2",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
/* Memory management */
register_low_BATs(env);
register_high_BATs(env);
@@ -4588,7 +4590,7 @@ static void init_proc_755(CPUPPCState *env)
register_ne_601_sprs(env);
register_sdr1_sprs(env);
register_7xx_sprs(env);
- register_755_sprs(env);
+ register_745_sprs(env);
/* L2 cache control */
spr_register(env, SPR_L2CR, "L2CR",
SPR_NOACCESS, SPR_NOACCESS,
@@ -4601,21 +4603,7 @@ static void init_proc_755(CPUPPCState *env)
0x00000000);
/* Thermal management */
register_thrm_sprs(env);
- /* Hardware implementation registers */
- spr_register(env, SPR_HID0, "HID0",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- spr_register(env, SPR_HID1, "HID1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-
- spr_register(env, SPR_HID2, "HID2",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
/* Memory management */
register_low_BATs(env);
register_high_BATs(env);
--
2.34.1
^ permalink raw reply related [flat|nested] 41+ messages in thread* [PULL 26/39] target/ppc: cpu_init: Deduplicate 7xx SPR registration
2022-02-18 10:37 [PULL 00/39] ppc queue Cédric Le Goater
` (24 preceding siblings ...)
2022-02-18 10:38 ` [PULL 25/39] target/ppc: cpu_init: Deduplicate 745/755 " Cédric Le Goater
@ 2022-02-18 10:38 ` Cédric Le Goater
2022-02-18 10:38 ` [PULL 27/39] target/ppc: cpu_init: Move 755 L2 cache SPRs into a function Cédric Le Goater
` (13 subsequent siblings)
39 siblings, 0 replies; 41+ messages in thread
From: Cédric Le Goater @ 2022-02-18 10:38 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, David Gibson, Cédric Le Goater, Fabiano Rosas
From: Fabiano Rosas <farosas@linux.ibm.com>
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <20220216162426.1885923-15-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/cpu_init.c | 68 +++++++------------------------------------
1 file changed, 11 insertions(+), 57 deletions(-)
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 43289a429fa8..d5c23785d727 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -596,6 +596,17 @@ static void register_7xx_sprs(CPUPPCState *env)
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
+
+ /* Hardware implementation registers */
+ spr_register(env, SPR_HID0, "HID0",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+
+ spr_register(env, SPR_HID1, "HID1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
}
#ifdef TARGET_PPC64
@@ -3958,16 +3969,7 @@ static void init_proc_740(CPUPPCState *env)
register_7xx_sprs(env);
/* Thermal management */
register_thrm_sprs(env);
- /* Hardware implementation registers */
- spr_register(env, SPR_HID0, "HID0",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- spr_register(env, SPR_HID1, "HID1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
/* Memory management */
register_low_BATs(env);
init_excp_7x0(env);
@@ -4028,16 +4030,7 @@ static void init_proc_750(CPUPPCState *env)
0x00000000);
/* Thermal management */
register_thrm_sprs(env);
- /* Hardware implementation registers */
- spr_register(env, SPR_HID0, "HID0",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- spr_register(env, SPR_HID1, "HID1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
/* Memory management */
register_low_BATs(env);
/*
@@ -4137,16 +4130,6 @@ static void init_proc_750cl(CPUPPCState *env)
&spr_read_generic, &spr_write_generic,
0x00000000);
/* Hardware implementation registers */
- spr_register(env, SPR_HID0, "HID0",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-
- spr_register(env, SPR_HID1, "HID1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-
spr_register(env, SPR_750CL_HID2, "HID2",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
@@ -4302,16 +4285,7 @@ static void init_proc_750cx(CPUPPCState *env)
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0x00000000);
- /* Hardware implementation registers */
- spr_register(env, SPR_HID0, "HID0",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- spr_register(env, SPR_HID1, "HID1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
/* Memory management */
register_low_BATs(env);
/* PowerPC 750cx has 8 DBATs and 8 IBATs */
@@ -4380,16 +4354,6 @@ static void init_proc_750fx(CPUPPCState *env)
&spr_read_generic, &spr_write_generic,
0x00000000);
/* Hardware implementation registers */
- spr_register(env, SPR_HID0, "HID0",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-
- spr_register(env, SPR_HID1, "HID1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-
spr_register(env, SPR_750FX_HID2, "HID2",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
@@ -4462,16 +4426,6 @@ static void init_proc_750gx(CPUPPCState *env)
&spr_read_generic, &spr_write_generic,
0x00000000);
/* Hardware implementation registers */
- spr_register(env, SPR_HID0, "HID0",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-
- spr_register(env, SPR_HID1, "HID1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-
spr_register(env, SPR_750FX_HID2, "HID2",
SPR_NOACCESS, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
--
2.34.1
^ permalink raw reply related [flat|nested] 41+ messages in thread* [PULL 27/39] target/ppc: cpu_init: Move 755 L2 cache SPRs into a function
2022-02-18 10:37 [PULL 00/39] ppc queue Cédric Le Goater
` (25 preceding siblings ...)
2022-02-18 10:38 ` [PULL 26/39] target/ppc: cpu_init: Deduplicate 7xx " Cédric Le Goater
@ 2022-02-18 10:38 ` Cédric Le Goater
2022-02-18 10:38 ` [PULL 28/39] target/ppc: cpu_init: Move e300 SPR registration " Cédric Le Goater
` (12 subsequent siblings)
39 siblings, 0 replies; 41+ messages in thread
From: Cédric Le Goater @ 2022-02-18 10:38 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, David Gibson, Cédric Le Goater, Fabiano Rosas
From: Fabiano Rosas <farosas@linux.ibm.com>
This is just to have 755-specific registers contained into a function,
intead of leaving them open-coded in init_proc_755. It makes init_proc
easier to read and keeps later patches that touch this code a bit
cleaner.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <20220216162426.1885923-16-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/cpu_init.c | 24 +++++++++++++++---------
1 file changed, 15 insertions(+), 9 deletions(-)
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index d5c23785d727..ef9353a7fe43 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -503,6 +503,20 @@ static void register_745_sprs(CPUPPCState *env)
0x00000000);
}
+static void register_755_sprs(CPUPPCState *env)
+{
+ /* L2 cache control */
+ spr_register(env, SPR_L2CR, "L2CR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, spr_access_nop,
+ 0x00000000);
+
+ spr_register(env, SPR_L2PMCR, "L2PMCR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+}
+
/* SPR common to all 7xx PowerPC implementations */
static void register_7xx_sprs(CPUPPCState *env)
{
@@ -4545,16 +4559,8 @@ static void init_proc_755(CPUPPCState *env)
register_sdr1_sprs(env);
register_7xx_sprs(env);
register_745_sprs(env);
- /* L2 cache control */
- spr_register(env, SPR_L2CR, "L2CR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, spr_access_nop,
- 0x00000000);
+ register_755_sprs(env);
- spr_register(env, SPR_L2PMCR, "L2PMCR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
/* Thermal management */
register_thrm_sprs(env);
--
2.34.1
^ permalink raw reply related [flat|nested] 41+ messages in thread* [PULL 28/39] target/ppc: cpu_init: Move e300 SPR registration into a function
2022-02-18 10:37 [PULL 00/39] ppc queue Cédric Le Goater
` (26 preceding siblings ...)
2022-02-18 10:38 ` [PULL 27/39] target/ppc: cpu_init: Move 755 L2 cache SPRs into a function Cédric Le Goater
@ 2022-02-18 10:38 ` Cédric Le Goater
2022-02-18 10:38 ` [PULL 29/39] target/ppc: cpu_init: Move 604e " Cédric Le Goater
` (11 subsequent siblings)
39 siblings, 0 replies; 41+ messages in thread
From: Cédric Le Goater @ 2022-02-18 10:38 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, David Gibson, Cédric Le Goater, Fabiano Rosas
From: Fabiano Rosas <farosas@linux.ibm.com>
This is done to improve init_proc readability and to make subsequent
patches that touch this code a bit cleaner.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <20220216162426.1885923-17-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/cpu_init.c | 64 +++++++++++++++++++++++--------------------
1 file changed, 35 insertions(+), 29 deletions(-)
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index ef9353a7fe43..62eec9e6f065 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -768,6 +768,40 @@ static void register_603_sprs(CPUPPCState *env)
0x00000000);
}
+static void register_e300_sprs(CPUPPCState *env)
+{
+ /* hardware implementation registers */
+ spr_register(env, SPR_HID2, "HID2",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* Breakpoints */
+ spr_register(env, SPR_DABR, "DABR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+
+ spr_register(env, SPR_DABR2, "DABR2",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+
+ spr_register(env, SPR_IABR2, "IABR2",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+
+ spr_register(env, SPR_IBCR, "IBCR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+
+ spr_register(env, SPR_DBCR, "DBCR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+}
+
/* SPR specific to PowerPC G2 implementation */
static void register_G2_sprs(CPUPPCState *env)
{
@@ -3213,36 +3247,8 @@ static void init_proc_e300(CPUPPCState *env)
register_ne_601_sprs(env);
register_sdr1_sprs(env);
register_603_sprs(env);
- /* hardware implementation registers */
- spr_register(env, SPR_HID2, "HID2",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* Breakpoints */
- spr_register(env, SPR_DABR, "DABR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
+ register_e300_sprs(env);
- spr_register(env, SPR_DABR2, "DABR2",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-
- spr_register(env, SPR_IABR2, "IABR2",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-
- spr_register(env, SPR_IBCR, "IBCR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-
- spr_register(env, SPR_DBCR, "DBCR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
/* Memory management */
register_low_BATs(env);
register_high_BATs(env);
--
2.34.1
^ permalink raw reply related [flat|nested] 41+ messages in thread* [PULL 29/39] target/ppc: cpu_init: Move 604e SPR registration into a function
2022-02-18 10:37 [PULL 00/39] ppc queue Cédric Le Goater
` (27 preceding siblings ...)
2022-02-18 10:38 ` [PULL 28/39] target/ppc: cpu_init: Move e300 SPR registration " Cédric Le Goater
@ 2022-02-18 10:38 ` Cédric Le Goater
2022-02-18 10:38 ` [PULL 30/39] target/ppc: cpu_init: Reuse init_proc_603 for the e300 Cédric Le Goater
` (10 subsequent siblings)
39 siblings, 0 replies; 41+ messages in thread
From: Cédric Le Goater @ 2022-02-18 10:38 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, David Gibson, Cédric Le Goater, Fabiano Rosas
From: Fabiano Rosas <farosas@linux.ibm.com>
This is done to improve init_proc readability and to make subsequent
patches that touch this code a bit cleaner.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <20220216162426.1885923-18-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/cpu_init.c | 43 ++++++++++++++++++++++++-------------------
1 file changed, 24 insertions(+), 19 deletions(-)
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 62eec9e6f065..f75aaf98c303 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -743,6 +743,29 @@ static void register_604_sprs(CPUPPCState *env)
0x00000000);
}
+static void register_604e_sprs(CPUPPCState *env)
+{
+ spr_register(env, SPR_7XX_MMCR1, "MMCR1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+
+ spr_register(env, SPR_7XX_PMC3, "PMC3",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+
+ spr_register(env, SPR_7XX_PMC4, "PMC4",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* Hardware implementation registers */
+ spr_register(env, SPR_HID1, "HID1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+}
+
/* SPR specific to PowerPC 603 implementation */
static void register_603_sprs(CPUPPCState *env)
{
@@ -3914,26 +3937,8 @@ static void init_proc_604E(CPUPPCState *env)
register_ne_601_sprs(env);
register_sdr1_sprs(env);
register_604_sprs(env);
+ register_604e_sprs(env);
- spr_register(env, SPR_7XX_MMCR1, "MMCR1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-
- spr_register(env, SPR_7XX_PMC3, "PMC3",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-
- spr_register(env, SPR_7XX_PMC4, "PMC4",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* Hardware implementation registers */
- spr_register(env, SPR_HID1, "HID1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
/* Memory management */
register_low_BATs(env);
init_excp_604(env);
--
2.34.1
^ permalink raw reply related [flat|nested] 41+ messages in thread* [PULL 30/39] target/ppc: cpu_init: Reuse init_proc_603 for the e300
2022-02-18 10:37 [PULL 00/39] ppc queue Cédric Le Goater
` (28 preceding siblings ...)
2022-02-18 10:38 ` [PULL 29/39] target/ppc: cpu_init: Move 604e " Cédric Le Goater
@ 2022-02-18 10:38 ` Cédric Le Goater
2022-02-18 10:38 ` [PULL 31/39] target/ppc: cpu_init: Reuse init_proc_604 for the 604e Cédric Le Goater
` (9 subsequent siblings)
39 siblings, 0 replies; 41+ messages in thread
From: Cédric Le Goater @ 2022-02-18 10:38 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, David Gibson, Cédric Le Goater, Fabiano Rosas
From: Fabiano Rosas <farosas@linux.ibm.com>
init_proc_603 is defined after init_proc_e300, so I had to move some
code around to make it work.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <20220216162426.1885923-19-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/cpu_init.c | 104 +++++++++++++++++++-----------------------
1 file changed, 46 insertions(+), 58 deletions(-)
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index f75aaf98c303..794486dd3a4d 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -3265,64 +3265,6 @@ POWERPC_FAMILY(e200)(ObjectClass *oc, void *data)
POWERPC_FLAG_BUS_CLK;
}
-static void init_proc_e300(CPUPPCState *env)
-{
- register_ne_601_sprs(env);
- register_sdr1_sprs(env);
- register_603_sprs(env);
- register_e300_sprs(env);
-
- /* Memory management */
- register_low_BATs(env);
- register_high_BATs(env);
- register_6xx_7xx_soft_tlb(env, 64, 2);
- init_excp_603(env);
- env->dcache_line_size = 32;
- env->icache_line_size = 32;
- /* Allocate hardware IRQ controller */
- ppc6xx_irq_init(env_archcpu(env));
-}
-
-POWERPC_FAMILY(e300)(ObjectClass *oc, void *data)
-{
- DeviceClass *dc = DEVICE_CLASS(oc);
- PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
-
- dc->desc = "e300 core";
- pcc->init_proc = init_proc_e300;
- pcc->check_pow = check_pow_hid0;
- pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
- PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
- PPC_FLOAT_STFIWX |
- PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
- PPC_MEM_SYNC | PPC_MEM_EIEIO |
- PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
- PPC_SEGMENT | PPC_EXTERN;
- pcc->msr_mask = (1ull << MSR_POW) |
- (1ull << MSR_TGPR) |
- (1ull << MSR_ILE) |
- (1ull << MSR_EE) |
- (1ull << MSR_PR) |
- (1ull << MSR_FP) |
- (1ull << MSR_ME) |
- (1ull << MSR_FE0) |
- (1ull << MSR_SE) |
- (1ull << MSR_DE) |
- (1ull << MSR_FE1) |
- (1ull << MSR_AL) |
- (1ull << MSR_EP) |
- (1ull << MSR_IR) |
- (1ull << MSR_DR) |
- (1ull << MSR_RI) |
- (1ull << MSR_LE);
- pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
- pcc->excp_model = POWERPC_EXCP_6xx;
- pcc->bus_model = PPC_FLAGS_INPUT_6xx;
- pcc->bfd_mach = bfd_mach_ppc_603;
- pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
- POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
-}
-
enum fsl_e500_version {
fsl_e500v1,
fsl_e500v2,
@@ -3878,6 +3820,52 @@ POWERPC_FAMILY(603E)(ObjectClass *oc, void *data)
POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
}
+static void init_proc_e300(CPUPPCState *env)
+{
+ init_proc_603(env);
+ register_e300_sprs(env);
+}
+
+POWERPC_FAMILY(e300)(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+ PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+
+ dc->desc = "e300 core";
+ pcc->init_proc = init_proc_e300;
+ pcc->check_pow = check_pow_hid0;
+ pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
+ PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
+ PPC_FLOAT_STFIWX |
+ PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
+ PPC_MEM_SYNC | PPC_MEM_EIEIO |
+ PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
+ PPC_SEGMENT | PPC_EXTERN;
+ pcc->msr_mask = (1ull << MSR_POW) |
+ (1ull << MSR_TGPR) |
+ (1ull << MSR_ILE) |
+ (1ull << MSR_EE) |
+ (1ull << MSR_PR) |
+ (1ull << MSR_FP) |
+ (1ull << MSR_ME) |
+ (1ull << MSR_FE0) |
+ (1ull << MSR_SE) |
+ (1ull << MSR_DE) |
+ (1ull << MSR_FE1) |
+ (1ull << MSR_AL) |
+ (1ull << MSR_EP) |
+ (1ull << MSR_IR) |
+ (1ull << MSR_DR) |
+ (1ull << MSR_RI) |
+ (1ull << MSR_LE);
+ pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
+ pcc->excp_model = POWERPC_EXCP_6xx;
+ pcc->bus_model = PPC_FLAGS_INPUT_6xx;
+ pcc->bfd_mach = bfd_mach_ppc_603;
+ pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
+ POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
+}
+
static void init_proc_604(CPUPPCState *env)
{
register_ne_601_sprs(env);
--
2.34.1
^ permalink raw reply related [flat|nested] 41+ messages in thread* [PULL 31/39] target/ppc: cpu_init: Reuse init_proc_604 for the 604e
2022-02-18 10:37 [PULL 00/39] ppc queue Cédric Le Goater
` (29 preceding siblings ...)
2022-02-18 10:38 ` [PULL 30/39] target/ppc: cpu_init: Reuse init_proc_603 for the e300 Cédric Le Goater
@ 2022-02-18 10:38 ` Cédric Le Goater
2022-02-18 10:38 ` [PULL 32/39] target/ppc: cpu_init: Reuse init_proc_745 for the 755 Cédric Le Goater
` (8 subsequent siblings)
39 siblings, 0 replies; 41+ messages in thread
From: Cédric Le Goater @ 2022-02-18 10:38 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, David Gibson, Cédric Le Goater, Fabiano Rosas
From: Fabiano Rosas <farosas@linux.ibm.com>
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <20220216162426.1885923-20-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/cpu_init.c | 12 +-----------
1 file changed, 1 insertion(+), 11 deletions(-)
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 794486dd3a4d..28e65ba20476 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -3922,18 +3922,8 @@ POWERPC_FAMILY(604)(ObjectClass *oc, void *data)
static void init_proc_604E(CPUPPCState *env)
{
- register_ne_601_sprs(env);
- register_sdr1_sprs(env);
- register_604_sprs(env);
+ init_proc_604(env);
register_604e_sprs(env);
-
- /* Memory management */
- register_low_BATs(env);
- init_excp_604(env);
- env->dcache_line_size = 32;
- env->icache_line_size = 32;
- /* Allocate hardware IRQ controller */
- ppc6xx_irq_init(env_archcpu(env));
}
POWERPC_FAMILY(604E)(ObjectClass *oc, void *data)
--
2.34.1
^ permalink raw reply related [flat|nested] 41+ messages in thread* [PULL 32/39] target/ppc: cpu_init: Reuse init_proc_745 for the 755
2022-02-18 10:37 [PULL 00/39] ppc queue Cédric Le Goater
` (30 preceding siblings ...)
2022-02-18 10:38 ` [PULL 31/39] target/ppc: cpu_init: Reuse init_proc_604 for the 604e Cédric Le Goater
@ 2022-02-18 10:38 ` Cédric Le Goater
2022-02-18 10:38 ` [PULL 33/39] target/ppc: cpu_init: Rename register_ne_601_sprs Cédric Le Goater
` (7 subsequent siblings)
39 siblings, 0 replies; 41+ messages in thread
From: Cédric Le Goater @ 2022-02-18 10:38 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, David Gibson, Cédric Le Goater, Fabiano Rosas
From: Fabiano Rosas <farosas@linux.ibm.com>
The init_proc_755 function is identical to the 745 one except for the
755-specific registers. I think it is worth it to make them share
code.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <20220216162426.1885923-21-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/cpu_init.c | 18 +-----------------
1 file changed, 1 insertion(+), 17 deletions(-)
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 28e65ba20476..243e05f7625d 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -4544,24 +4544,8 @@ POWERPC_FAMILY(745)(ObjectClass *oc, void *data)
static void init_proc_755(CPUPPCState *env)
{
- register_ne_601_sprs(env);
- register_sdr1_sprs(env);
- register_7xx_sprs(env);
- register_745_sprs(env);
+ init_proc_745(env);
register_755_sprs(env);
-
- /* Thermal management */
- register_thrm_sprs(env);
-
- /* Memory management */
- register_low_BATs(env);
- register_high_BATs(env);
- register_6xx_7xx_soft_tlb(env, 64, 2);
- init_excp_7x5(env);
- env->dcache_line_size = 32;
- env->icache_line_size = 32;
- /* Allocate hardware IRQ controller */
- ppc6xx_irq_init(env_archcpu(env));
}
POWERPC_FAMILY(755)(ObjectClass *oc, void *data)
--
2.34.1
^ permalink raw reply related [flat|nested] 41+ messages in thread* [PULL 33/39] target/ppc: cpu_init: Rename register_ne_601_sprs
2022-02-18 10:37 [PULL 00/39] ppc queue Cédric Le Goater
` (31 preceding siblings ...)
2022-02-18 10:38 ` [PULL 32/39] target/ppc: cpu_init: Reuse init_proc_745 for the 755 Cédric Le Goater
@ 2022-02-18 10:38 ` Cédric Le Goater
2022-02-18 10:38 ` [PULL 34/39] target/ppc: cpu_init: Remove register_usprg3_sprs Cédric Le Goater
` (6 subsequent siblings)
39 siblings, 0 replies; 41+ messages in thread
From: Cédric Le Goater @ 2022-02-18 10:38 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, David Gibson, Cédric Le Goater, Fabiano Rosas
From: Fabiano Rosas <farosas@linux.ibm.com>
The important part of this function is that it applies to non-embedded
CPUs, not that it also applies to the 601. We removed support for the
601 anyway, so rename this function.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <20220216162426.1885923-22-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/cpu_init.c | 41 ++++++++++++++++++++---------------------
1 file changed, 20 insertions(+), 21 deletions(-)
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 243e05f7625d..5980a6a4d312 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -241,8 +241,7 @@ static void register_generic_sprs(PowerPCCPU *cpu)
0x00000000);
}
-/* SPR common to all non-embedded PowerPC, including 601 */
-static void register_ne_601_sprs(CPUPPCState *env)
+static void register_non_embedded_sprs(CPUPPCState *env)
{
/* Exception processing */
spr_register_kvm(env, SPR_DSISR, "DSISR",
@@ -3018,7 +3017,7 @@ POWERPC_FAMILY(MPC8xx)(ObjectClass *oc, void *data)
static void init_proc_G2(CPUPPCState *env)
{
- register_ne_601_sprs(env);
+ register_non_embedded_sprs(env);
register_sdr1_sprs(env);
register_G2_sprs(env);
@@ -3728,7 +3727,7 @@ POWERPC_FAMILY(e6500)(ObjectClass *oc, void *data)
/* Non-embedded PowerPC */
static void init_proc_603(CPUPPCState *env)
{
- register_ne_601_sprs(env);
+ register_non_embedded_sprs(env);
register_sdr1_sprs(env);
register_603_sprs(env);
@@ -3868,7 +3867,7 @@ POWERPC_FAMILY(e300)(ObjectClass *oc, void *data)
static void init_proc_604(CPUPPCState *env)
{
- register_ne_601_sprs(env);
+ register_non_embedded_sprs(env);
register_sdr1_sprs(env);
register_604_sprs(env);
@@ -3967,7 +3966,7 @@ POWERPC_FAMILY(604E)(ObjectClass *oc, void *data)
static void init_proc_740(CPUPPCState *env)
{
- register_ne_601_sprs(env);
+ register_non_embedded_sprs(env);
register_sdr1_sprs(env);
register_7xx_sprs(env);
/* Thermal management */
@@ -4023,7 +4022,7 @@ POWERPC_FAMILY(740)(ObjectClass *oc, void *data)
static void init_proc_750(CPUPPCState *env)
{
- register_ne_601_sprs(env);
+ register_non_embedded_sprs(env);
register_sdr1_sprs(env);
register_7xx_sprs(env);
@@ -4088,7 +4087,7 @@ POWERPC_FAMILY(750)(ObjectClass *oc, void *data)
static void init_proc_750cl(CPUPPCState *env)
{
- register_ne_601_sprs(env);
+ register_non_embedded_sprs(env);
register_sdr1_sprs(env);
register_7xx_sprs(env);
@@ -4273,7 +4272,7 @@ POWERPC_FAMILY(750cl)(ObjectClass *oc, void *data)
static void init_proc_750cx(CPUPPCState *env)
{
- register_ne_601_sprs(env);
+ register_non_embedded_sprs(env);
register_sdr1_sprs(env);
register_7xx_sprs(env);
@@ -4341,7 +4340,7 @@ POWERPC_FAMILY(750cx)(ObjectClass *oc, void *data)
static void init_proc_750fx(CPUPPCState *env)
{
- register_ne_601_sprs(env);
+ register_non_embedded_sprs(env);
register_sdr1_sprs(env);
register_7xx_sprs(env);
@@ -4413,7 +4412,7 @@ POWERPC_FAMILY(750fx)(ObjectClass *oc, void *data)
static void init_proc_750gx(CPUPPCState *env)
{
- register_ne_601_sprs(env);
+ register_non_embedded_sprs(env);
register_sdr1_sprs(env);
register_7xx_sprs(env);
@@ -4485,7 +4484,7 @@ POWERPC_FAMILY(750gx)(ObjectClass *oc, void *data)
static void init_proc_745(CPUPPCState *env)
{
- register_ne_601_sprs(env);
+ register_non_embedded_sprs(env);
register_sdr1_sprs(env);
register_7xx_sprs(env);
register_745_sprs(env);
@@ -4589,7 +4588,7 @@ POWERPC_FAMILY(755)(ObjectClass *oc, void *data)
static void init_proc_7400(CPUPPCState *env)
{
- register_ne_601_sprs(env);
+ register_non_embedded_sprs(env);
register_sdr1_sprs(env);
register_74xx_sprs(env);
vscr_init(env, 0x00010000);
@@ -4661,7 +4660,7 @@ POWERPC_FAMILY(7400)(ObjectClass *oc, void *data)
static void init_proc_7410(CPUPPCState *env)
{
- register_ne_601_sprs(env);
+ register_non_embedded_sprs(env);
register_sdr1_sprs(env);
register_74xx_sprs(env);
vscr_init(env, 0x00010000);
@@ -4740,7 +4739,7 @@ POWERPC_FAMILY(7410)(ObjectClass *oc, void *data)
static void init_proc_7440(CPUPPCState *env)
{
- register_ne_601_sprs(env);
+ register_non_embedded_sprs(env);
register_sdr1_sprs(env);
register_74xx_sprs(env);
vscr_init(env, 0x00010000);
@@ -4840,7 +4839,7 @@ POWERPC_FAMILY(7440)(ObjectClass *oc, void *data)
static void init_proc_7450(CPUPPCState *env)
{
- register_ne_601_sprs(env);
+ register_non_embedded_sprs(env);
register_sdr1_sprs(env);
register_74xx_sprs(env);
vscr_init(env, 0x00010000);
@@ -4962,7 +4961,7 @@ POWERPC_FAMILY(7450)(ObjectClass *oc, void *data)
static void init_proc_7445(CPUPPCState *env)
{
- register_ne_601_sprs(env);
+ register_non_embedded_sprs(env);
register_sdr1_sprs(env);
register_74xx_sprs(env);
vscr_init(env, 0x00010000);
@@ -5091,7 +5090,7 @@ POWERPC_FAMILY(7445)(ObjectClass *oc, void *data)
static void init_proc_7455(CPUPPCState *env)
{
- register_ne_601_sprs(env);
+ register_non_embedded_sprs(env);
register_sdr1_sprs(env);
register_74xx_sprs(env);
vscr_init(env, 0x00010000);
@@ -5222,7 +5221,7 @@ POWERPC_FAMILY(7455)(ObjectClass *oc, void *data)
static void init_proc_7457(CPUPPCState *env)
{
- register_ne_601_sprs(env);
+ register_non_embedded_sprs(env);
register_sdr1_sprs(env);
register_74xx_sprs(env);
vscr_init(env, 0x00010000);
@@ -5373,7 +5372,7 @@ POWERPC_FAMILY(7457)(ObjectClass *oc, void *data)
static void init_proc_e600(CPUPPCState *env)
{
- register_ne_601_sprs(env);
+ register_non_embedded_sprs(env);
register_sdr1_sprs(env);
register_74xx_sprs(env);
vscr_init(env, 0x00010000);
@@ -6196,7 +6195,7 @@ static void init_tcg_pmu_power8(CPUPPCState *env)
static void init_proc_book3s_common(CPUPPCState *env)
{
- register_ne_601_sprs(env);
+ register_non_embedded_sprs(env);
register_usprg3_sprs(env);
register_book3s_altivec_sprs(env);
register_book3s_pmu_sup_sprs(env);
--
2.34.1
^ permalink raw reply related [flat|nested] 41+ messages in thread* [PULL 34/39] target/ppc: cpu_init: Remove register_usprg3_sprs
2022-02-18 10:37 [PULL 00/39] ppc queue Cédric Le Goater
` (32 preceding siblings ...)
2022-02-18 10:38 ` [PULL 33/39] target/ppc: cpu_init: Rename register_ne_601_sprs Cédric Le Goater
@ 2022-02-18 10:38 ` Cédric Le Goater
2022-02-18 10:38 ` [PULL 35/39] target/ppc: Rename spr_tcg.h to spr_common.h Cédric Le Goater
` (5 subsequent siblings)
39 siblings, 0 replies; 41+ messages in thread
From: Cédric Le Goater @ 2022-02-18 10:38 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, David Gibson, Cédric Le Goater, Fabiano Rosas
From: Fabiano Rosas <farosas@linux.ibm.com>
This function registers just one SPR and has only two callers, so open
code it.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <20220216162426.1885923-23-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/cpu_init.c | 21 +++++++++++----------
1 file changed, 11 insertions(+), 10 deletions(-)
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 5980a6a4d312..452dbdda4db6 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -1072,14 +1072,6 @@ static void register_l3_ctrl(CPUPPCState *env)
0x00000000);
}
-static void register_usprg3_sprs(CPUPPCState *env)
-{
- spr_register(env, SPR_USPRG3, "USPRG3",
- &spr_read_ureg, SPR_NOACCESS,
- &spr_read_ureg, SPR_NOACCESS,
- 0x00000000);
-}
-
static void register_usprgh_sprs(CPUPPCState *env)
{
spr_register(env, SPR_USPRG4, "USPRG4",
@@ -3306,7 +3298,12 @@ static void init_proc_e500(CPUPPCState *env, int version)
break;
}
register_BookE_sprs(env, ivor_mask);
- register_usprg3_sprs(env);
+
+ spr_register(env, SPR_USPRG3, "USPRG3",
+ &spr_read_ureg, SPR_NOACCESS,
+ &spr_read_ureg, SPR_NOACCESS,
+ 0x00000000);
+
/* Processor identification */
spr_register(env, SPR_BOOKE_PIR, "PIR",
SPR_NOACCESS, SPR_NOACCESS,
@@ -6196,7 +6193,6 @@ static void init_tcg_pmu_power8(CPUPPCState *env)
static void init_proc_book3s_common(CPUPPCState *env)
{
register_non_embedded_sprs(env);
- register_usprg3_sprs(env);
register_book3s_altivec_sprs(env);
register_book3s_pmu_sup_sprs(env);
register_book3s_pmu_user_sprs(env);
@@ -6206,6 +6202,11 @@ static void init_proc_book3s_common(CPUPPCState *env)
* value is the one used by 74xx processors.
*/
vscr_init(env, 0x00010000);
+
+ spr_register(env, SPR_USPRG3, "USPRG3",
+ &spr_read_ureg, SPR_NOACCESS,
+ &spr_read_ureg, SPR_NOACCESS,
+ 0x00000000);
}
static void init_proc_970(CPUPPCState *env)
--
2.34.1
^ permalink raw reply related [flat|nested] 41+ messages in thread* [PULL 35/39] target/ppc: Rename spr_tcg.h to spr_common.h
2022-02-18 10:37 [PULL 00/39] ppc queue Cédric Le Goater
` (33 preceding siblings ...)
2022-02-18 10:38 ` [PULL 34/39] target/ppc: cpu_init: Remove register_usprg3_sprs Cédric Le Goater
@ 2022-02-18 10:38 ` Cédric Le Goater
2022-02-18 10:38 ` [PULL 36/39] target/ppc: cpu_init: Expose some SPR registration helpers Cédric Le Goater
` (4 subsequent siblings)
39 siblings, 0 replies; 41+ messages in thread
From: Cédric Le Goater @ 2022-02-18 10:38 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, David Gibson, Cédric Le Goater, Fabiano Rosas
From: Fabiano Rosas <farosas@linux.ibm.com>
Initial intent for the spr_tcg header was to expose the spr_read|write
callbacks that are only used by TCG code. However, although these
routines are TCG-specific, the KVM code needs access to env->sprs
which creation is currently coupled to the callback registration.
We are probably not going to decouple SPR creation and TCG callback
registration any time soon, so let's rename the header to spr_common
to accomodate the register_*_sprs functions that will be moved out of
cpu_init.c in the following patches.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <20220216162426.1885923-24-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/{spr_tcg.h => spr_common.h} | 4 ++--
target/ppc/cpu_init.c | 2 +-
target/ppc/translate.c | 2 +-
3 files changed, 4 insertions(+), 4 deletions(-)
rename target/ppc/{spr_tcg.h => spr_common.h} (99%)
diff --git a/target/ppc/spr_tcg.h b/target/ppc/spr_common.h
similarity index 99%
rename from target/ppc/spr_tcg.h
rename to target/ppc/spr_common.h
index df2abacc644f..5aec76ade4dd 100644
--- a/target/ppc/spr_tcg.h
+++ b/target/ppc/spr_common.h
@@ -16,8 +16,8 @@
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
*/
-#ifndef SPR_TCG_H
-#define SPR_TCG_H
+#ifndef SPR_COMMON_H
+#define SPR_COMMON_H
#define SPR_NOACCESS (&spr_noaccess)
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 452dbdda4db6..f0bbe340e4fd 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -44,7 +44,7 @@
#include "helper_regs.h"
#include "internal.h"
-#include "spr_tcg.h"
+#include "spr_common.h"
#include "power8-pmu.h"
/* #define PPC_DEBUG_SPR */
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 2eaffd432a9d..ecc5a104e049 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -35,7 +35,7 @@
#include "exec/translator.h"
#include "exec/log.h"
#include "qemu/atomic128.h"
-#include "spr_tcg.h"
+#include "spr_common.h"
#include "qemu/qemu-print.h"
#include "qapi/error.h"
--
2.34.1
^ permalink raw reply related [flat|nested] 41+ messages in thread* [PULL 36/39] target/ppc: cpu_init: Expose some SPR registration helpers
2022-02-18 10:37 [PULL 00/39] ppc queue Cédric Le Goater
` (34 preceding siblings ...)
2022-02-18 10:38 ` [PULL 35/39] target/ppc: Rename spr_tcg.h to spr_common.h Cédric Le Goater
@ 2022-02-18 10:38 ` Cédric Le Goater
2022-02-18 10:38 ` [PULL 37/39] target/ppc: cpu_init: Move SPR registration macros to a header Cédric Le Goater
` (3 subsequent siblings)
39 siblings, 0 replies; 41+ messages in thread
From: Cédric Le Goater @ 2022-02-18 10:38 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, David Gibson, Cédric Le Goater, Fabiano Rosas
From: Fabiano Rosas <farosas@linux.ibm.com>
The following patches will move CPU-specific code into separate files,
so expose the most used SPR registration functions:
register_sdr1_sprs | 22 callers
register_low_BATs | 20 callers
register_non_embedded_sprs | 19 callers
register_high_BATs | 10 callers
register_thrm_sprs | 8 callers
register_usprgh_sprs | 6 callers
register_6xx_7xx_soft_tlb | only 3 callers, but it helps to
keep the soft TLB code consistent.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <20220216162426.1885923-25-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/spr_common.h | 8 ++++++++
target/ppc/cpu_init.c | 14 +++++++-------
2 files changed, 15 insertions(+), 7 deletions(-)
diff --git a/target/ppc/spr_common.h b/target/ppc/spr_common.h
index 5aec76ade4dd..329b7e91a23a 100644
--- a/target/ppc/spr_common.h
+++ b/target/ppc/spr_common.h
@@ -141,4 +141,12 @@ void spr_write_hmer(DisasContext *ctx, int sprn, int gprn);
void spr_write_lpcr(DisasContext *ctx, int sprn, int gprn);
#endif
+void register_low_BATs(CPUPPCState *env);
+void register_high_BATs(CPUPPCState *env);
+void register_sdr1_sprs(CPUPPCState *env);
+void register_thrm_sprs(CPUPPCState *env);
+void register_usprgh_sprs(CPUPPCState *env);
+void register_non_embedded_sprs(CPUPPCState *env);
+void register_6xx_7xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways);
+
#endif
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index f0bbe340e4fd..40dd2c0fd813 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -241,7 +241,7 @@ static void register_generic_sprs(PowerPCCPU *cpu)
0x00000000);
}
-static void register_non_embedded_sprs(CPUPPCState *env)
+void register_non_embedded_sprs(CPUPPCState *env)
{
/* Exception processing */
spr_register_kvm(env, SPR_DSISR, "DSISR",
@@ -260,7 +260,7 @@ static void register_non_embedded_sprs(CPUPPCState *env)
}
/* Storage Description Register 1 */
-static void register_sdr1_sprs(CPUPPCState *env)
+void register_sdr1_sprs(CPUPPCState *env)
{
#ifndef CONFIG_USER_ONLY
if (env->has_hv_mode) {
@@ -283,7 +283,7 @@ static void register_sdr1_sprs(CPUPPCState *env)
}
/* BATs 0-3 */
-static void register_low_BATs(CPUPPCState *env)
+void register_low_BATs(CPUPPCState *env)
{
#if !defined(CONFIG_USER_ONLY)
spr_register(env, SPR_IBAT0U, "IBAT0U",
@@ -355,7 +355,7 @@ static void register_low_BATs(CPUPPCState *env)
}
/* BATs 4-7 */
-static void register_high_BATs(CPUPPCState *env)
+void register_high_BATs(CPUPPCState *env)
{
#if !defined(CONFIG_USER_ONLY)
spr_register(env, SPR_IBAT4U, "IBAT4U",
@@ -427,7 +427,7 @@ static void register_high_BATs(CPUPPCState *env)
}
/* Softare table search registers */
-static void register_6xx_7xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways)
+void register_6xx_7xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways)
{
#if !defined(CONFIG_USER_ONLY)
env->nb_tlb = nb_tlbs;
@@ -667,7 +667,7 @@ static void register_iamr_sprs(CPUPPCState *env)
}
#endif /* TARGET_PPC64 */
-static void register_thrm_sprs(CPUPPCState *env)
+void register_thrm_sprs(CPUPPCState *env)
{
/* Thermal management */
spr_register(env, SPR_THRM1, "THRM1",
@@ -1072,7 +1072,7 @@ static void register_l3_ctrl(CPUPPCState *env)
0x00000000);
}
-static void register_usprgh_sprs(CPUPPCState *env)
+void register_usprgh_sprs(CPUPPCState *env)
{
spr_register(env, SPR_USPRG4, "USPRG4",
&spr_read_ureg, SPR_NOACCESS,
--
2.34.1
^ permalink raw reply related [flat|nested] 41+ messages in thread* [PULL 37/39] target/ppc: cpu_init: Move SPR registration macros to a header
2022-02-18 10:37 [PULL 00/39] ppc queue Cédric Le Goater
` (35 preceding siblings ...)
2022-02-18 10:38 ` [PULL 36/39] target/ppc: cpu_init: Expose some SPR registration helpers Cédric Le Goater
@ 2022-02-18 10:38 ` Cédric Le Goater
2022-02-18 10:38 ` [PULL 38/39] target/ppc: cpu_init: Move check_pow and QOM " Cédric Le Goater
` (2 subsequent siblings)
39 siblings, 0 replies; 41+ messages in thread
From: Cédric Le Goater @ 2022-02-18 10:38 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, David Gibson, Cédric Le Goater, Fabiano Rosas
From: Fabiano Rosas <farosas@linux.ibm.com>
Put the SPR registration macros in a header that is accessible outside
of cpu_init.c. The following patches will move CPU-specific code to
separate files and will need to access it.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <20220216162426.1885923-26-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/spr_common.h | 56 +++++++++++++++++++++++++++++++++++
target/ppc/cpu_init.c | 65 ++++++-----------------------------------
2 files changed, 65 insertions(+), 56 deletions(-)
diff --git a/target/ppc/spr_common.h b/target/ppc/spr_common.h
index 329b7e91a23a..a243c14a11d9 100644
--- a/target/ppc/spr_common.h
+++ b/target/ppc/spr_common.h
@@ -21,6 +21,62 @@
#define SPR_NOACCESS (&spr_noaccess)
+#ifdef CONFIG_TCG
+# define USR_ARG(X) X,
+# ifdef CONFIG_USER_ONLY
+# define SYS_ARG(X)
+# else
+# define SYS_ARG(X) X,
+# endif
+#else
+# define USR_ARG(X)
+# define SYS_ARG(X)
+#endif
+#ifdef CONFIG_KVM
+# define KVM_ARG(X) X,
+#else
+# define KVM_ARG(X)
+#endif
+
+typedef void spr_callback(DisasContext *, int, int);
+
+void _spr_register(CPUPPCState *env, int num, const char *name,
+ USR_ARG(spr_callback *uea_read)
+ USR_ARG(spr_callback *uea_write)
+ SYS_ARG(spr_callback *oea_read)
+ SYS_ARG(spr_callback *oea_write)
+ SYS_ARG(spr_callback *hea_read)
+ SYS_ARG(spr_callback *hea_write)
+ KVM_ARG(uint64_t one_reg_id)
+ target_ulong initial_value);
+
+/* spr_register_kvm_hv passes all required arguments. */
+#define spr_register_kvm_hv(env, num, name, uea_read, uea_write, \
+ oea_read, oea_write, hea_read, hea_write, \
+ one_reg_id, initial_value) \
+ _spr_register(env, num, name, \
+ USR_ARG(uea_read) USR_ARG(uea_write) \
+ SYS_ARG(oea_read) SYS_ARG(oea_write) \
+ SYS_ARG(hea_read) SYS_ARG(hea_write) \
+ KVM_ARG(one_reg_id) initial_value)
+
+/* spr_register_kvm duplicates the oea callbacks to the hea callbacks. */
+#define spr_register_kvm(env, num, name, uea_read, uea_write, \
+ oea_read, oea_write, one_reg_id, ival) \
+ spr_register_kvm_hv(env, num, name, uea_read, uea_write, oea_read, \
+ oea_write, oea_read, oea_write, one_reg_id, ival)
+
+/* spr_register_hv and spr_register are similar, except there is no kvm id. */
+#define spr_register_hv(env, num, name, uea_read, uea_write, \
+ oea_read, oea_write, hea_read, hea_write, ival) \
+ spr_register_kvm_hv(env, num, name, uea_read, uea_write, oea_read, \
+ oea_write, hea_read, hea_write, 0, ival)
+
+#define spr_register(env, num, name, uea_read, uea_write, \
+ oea_read, oea_write, ival) \
+ spr_register_kvm(env, num, name, uea_read, uea_write, \
+ oea_read, oea_write, 0, ival)
+
/* prototypes for readers and writers for SPRs */
void spr_noaccess(DisasContext *ctx, int gprn, int sprn);
void spr_read_generic(DisasContext *ctx, int gprn, int sprn);
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 40dd2c0fd813..c17994ec5876 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -67,35 +67,15 @@ static inline void vscr_init(CPUPPCState *env, uint32_t val)
* may be compiled out, and the system kvm header may not be available
* for supplying the ID numbers. This is ugly, but the best we can do.
*/
-
-#ifdef CONFIG_TCG
-# define USR_ARG(X) X,
-# ifdef CONFIG_USER_ONLY
-# define SYS_ARG(X)
-# else
-# define SYS_ARG(X) X,
-# endif
-#else
-# define USR_ARG(X)
-# define SYS_ARG(X)
-#endif
-#ifdef CONFIG_KVM
-# define KVM_ARG(X) X,
-#else
-# define KVM_ARG(X)
-#endif
-
-typedef void spr_callback(DisasContext *, int, int);
-
-static void _spr_register(CPUPPCState *env, int num, const char *name,
- USR_ARG(spr_callback *uea_read)
- USR_ARG(spr_callback *uea_write)
- SYS_ARG(spr_callback *oea_read)
- SYS_ARG(spr_callback *oea_write)
- SYS_ARG(spr_callback *hea_read)
- SYS_ARG(spr_callback *hea_write)
- KVM_ARG(uint64_t one_reg_id)
- target_ulong initial_value)
+void _spr_register(CPUPPCState *env, int num, const char *name,
+ USR_ARG(spr_callback *uea_read)
+ USR_ARG(spr_callback *uea_write)
+ SYS_ARG(spr_callback *oea_read)
+ SYS_ARG(spr_callback *oea_write)
+ SYS_ARG(spr_callback *hea_read)
+ SYS_ARG(spr_callback *hea_write)
+ KVM_ARG(uint64_t one_reg_id)
+ target_ulong initial_value)
{
ppc_spr_t *spr = &env->spr_cb[num];
@@ -122,33 +102,6 @@ static void _spr_register(CPUPPCState *env, int num, const char *name,
#endif
}
-/* spr_register_kvm_hv passes all required arguments. */
-#define spr_register_kvm_hv(env, num, name, uea_read, uea_write, \
- oea_read, oea_write, hea_read, hea_write, \
- one_reg_id, initial_value) \
- _spr_register(env, num, name, \
- USR_ARG(uea_read) USR_ARG(uea_write) \
- SYS_ARG(oea_read) SYS_ARG(oea_write) \
- SYS_ARG(hea_read) SYS_ARG(hea_write) \
- KVM_ARG(one_reg_id) initial_value)
-
-/* spr_register_kvm duplicates the oea callbacks to the hea callbacks. */
-#define spr_register_kvm(env, num, name, uea_read, uea_write, \
- oea_read, oea_write, one_reg_id, ival) \
- spr_register_kvm_hv(env, num, name, uea_read, uea_write, oea_read, \
- oea_write, oea_read, oea_write, one_reg_id, ival)
-
-/* spr_register_hv and spr_register are similar, except there is no kvm id. */
-#define spr_register_hv(env, num, name, uea_read, uea_write, \
- oea_read, oea_write, hea_read, hea_write, ival) \
- spr_register_kvm_hv(env, num, name, uea_read, uea_write, oea_read, \
- oea_write, hea_read, hea_write, 0, ival)
-
-#define spr_register(env, num, name, uea_read, uea_write, \
- oea_read, oea_write, ival) \
- spr_register_kvm(env, num, name, uea_read, uea_write, \
- oea_read, oea_write, 0, ival)
-
/* Generic PowerPC SPRs */
static void register_generic_sprs(PowerPCCPU *cpu)
{
--
2.34.1
^ permalink raw reply related [flat|nested] 41+ messages in thread* [PULL 38/39] target/ppc: cpu_init: Move check_pow and QOM macros to a header
2022-02-18 10:37 [PULL 00/39] ppc queue Cédric Le Goater
` (36 preceding siblings ...)
2022-02-18 10:38 ` [PULL 37/39] target/ppc: cpu_init: Move SPR registration macros to a header Cédric Le Goater
@ 2022-02-18 10:38 ` Cédric Le Goater
2022-02-18 10:38 ` [PULL 39/39] target/ppc: Move common SPR functions out of cpu_init Cédric Le Goater
2022-02-20 19:28 ` [PULL 00/39] ppc queue Peter Maydell
39 siblings, 0 replies; 41+ messages in thread
From: Cédric Le Goater @ 2022-02-18 10:38 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, David Gibson, Cédric Le Goater, Fabiano Rosas
From: Fabiano Rosas <farosas@linux.ibm.com>
These will need to be accessed from other files once we move the CPUs
code to separate files.
The check_pow_hid0 and check_pow_hid0_74xx are too specific to be
moved to a header so I'll deal with them later when splitting this
code between the multiple CPU families.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <20220216162426.1885923-27-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/cpu.h | 39 +++++++++++++++++++++++++++++++++++++++
target/ppc/cpu_init.c | 37 -------------------------------------
2 files changed, 39 insertions(+), 37 deletions(-)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 2baa750729fd..5b01d409b31a 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -2732,4 +2732,43 @@ void dump_mmu(CPUPPCState *env);
void ppc_maybe_bswap_register(CPUPPCState *env, uint8_t *mem_buf, int len);
void ppc_store_vscr(CPUPPCState *env, uint32_t vscr);
uint32_t ppc_get_vscr(CPUPPCState *env);
+
+/*****************************************************************************/
+/* Power management enable checks */
+static inline int check_pow_none(CPUPPCState *env)
+{
+ return 0;
+}
+
+static inline int check_pow_nocheck(CPUPPCState *env)
+{
+ return 1;
+}
+
+/*****************************************************************************/
+/* PowerPC implementations definitions */
+
+#define POWERPC_FAMILY(_name) \
+ static void \
+ glue(glue(ppc_, _name), _cpu_family_class_init)(ObjectClass *, void *); \
+ \
+ static const TypeInfo \
+ glue(glue(ppc_, _name), _cpu_family_type_info) = { \
+ .name = stringify(_name) "-family-" TYPE_POWERPC_CPU, \
+ .parent = TYPE_POWERPC_CPU, \
+ .abstract = true, \
+ .class_init = glue(glue(ppc_, _name), _cpu_family_class_init), \
+ }; \
+ \
+ static void glue(glue(ppc_, _name), _cpu_family_register_types)(void) \
+ { \
+ type_register_static( \
+ &glue(glue(ppc_, _name), _cpu_family_type_info)); \
+ } \
+ \
+ type_init(glue(glue(ppc_, _name), _cpu_family_register_types)) \
+ \
+ static void glue(glue(ppc_, _name), _cpu_family_class_init)
+
+
#endif /* PPC_CPU_H */
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index c17994ec5876..a435525ea32f 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -2480,18 +2480,6 @@ static void init_excp_POWER10(CPUPPCState *env)
#endif
-/*****************************************************************************/
-/* Power management enable checks */
-static int check_pow_none(CPUPPCState *env)
-{
- return 0;
-}
-
-static int check_pow_nocheck(CPUPPCState *env)
-{
- return 1;
-}
-
static int check_pow_hid0(CPUPPCState *env)
{
if (env->spr[SPR_HID0] & 0x00E00000) {
@@ -2510,31 +2498,6 @@ static int check_pow_hid0_74xx(CPUPPCState *env)
return 0;
}
-/*****************************************************************************/
-/* PowerPC implementations definitions */
-
-#define POWERPC_FAMILY(_name) \
- static void \
- glue(glue(ppc_, _name), _cpu_family_class_init)(ObjectClass *, void *); \
- \
- static const TypeInfo \
- glue(glue(ppc_, _name), _cpu_family_type_info) = { \
- .name = stringify(_name) "-family-" TYPE_POWERPC_CPU, \
- .parent = TYPE_POWERPC_CPU, \
- .abstract = true, \
- .class_init = glue(glue(ppc_, _name), _cpu_family_class_init), \
- }; \
- \
- static void glue(glue(ppc_, _name), _cpu_family_register_types)(void) \
- { \
- type_register_static( \
- &glue(glue(ppc_, _name), _cpu_family_type_info)); \
- } \
- \
- type_init(glue(glue(ppc_, _name), _cpu_family_register_types)) \
- \
- static void glue(glue(ppc_, _name), _cpu_family_class_init)
-
static void init_proc_405(CPUPPCState *env)
{
register_40x_sprs(env);
--
2.34.1
^ permalink raw reply related [flat|nested] 41+ messages in thread* [PULL 39/39] target/ppc: Move common SPR functions out of cpu_init
2022-02-18 10:37 [PULL 00/39] ppc queue Cédric Le Goater
` (37 preceding siblings ...)
2022-02-18 10:38 ` [PULL 38/39] target/ppc: cpu_init: Move check_pow and QOM " Cédric Le Goater
@ 2022-02-18 10:38 ` Cédric Le Goater
2022-02-20 19:28 ` [PULL 00/39] ppc queue Peter Maydell
39 siblings, 0 replies; 41+ messages in thread
From: Cédric Le Goater @ 2022-02-18 10:38 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, David Gibson, Cédric Le Goater, Fabiano Rosas
From: Fabiano Rosas <farosas@linux.ibm.com>
Let's leave cpu_init with just generic CPU initialization and
QOM-related functions.
The rest of the SPR registration functions will be moved in the
following patches along with the code that uses them. These are only
the commonly used ones.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Message-Id: <20220216162426.1885923-28-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/spr_common.h | 1 +
target/ppc/cpu_init.c | 400 --------------------------------------
target/ppc/helper_regs.c | 402 +++++++++++++++++++++++++++++++++++++++
3 files changed, 403 insertions(+), 400 deletions(-)
diff --git a/target/ppc/spr_common.h b/target/ppc/spr_common.h
index a243c14a11d9..b5a5bc68952e 100644
--- a/target/ppc/spr_common.h
+++ b/target/ppc/spr_common.h
@@ -204,5 +204,6 @@ void register_thrm_sprs(CPUPPCState *env);
void register_usprgh_sprs(CPUPPCState *env);
void register_non_embedded_sprs(CPUPPCState *env);
void register_6xx_7xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways);
+void register_generic_sprs(PowerPCCPU *cpu);
#endif
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index a435525ea32f..61d36b11a093 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -57,367 +57,6 @@ static inline void vscr_init(CPUPPCState *env, uint32_t val)
ppc_store_vscr(env, val);
}
-/**
- * _spr_register
- *
- * Register an SPR with all the callbacks required for tcg,
- * and the ID number for KVM.
- *
- * The reason for the conditional compilation is that the tcg functions
- * may be compiled out, and the system kvm header may not be available
- * for supplying the ID numbers. This is ugly, but the best we can do.
- */
-void _spr_register(CPUPPCState *env, int num, const char *name,
- USR_ARG(spr_callback *uea_read)
- USR_ARG(spr_callback *uea_write)
- SYS_ARG(spr_callback *oea_read)
- SYS_ARG(spr_callback *oea_write)
- SYS_ARG(spr_callback *hea_read)
- SYS_ARG(spr_callback *hea_write)
- KVM_ARG(uint64_t one_reg_id)
- target_ulong initial_value)
-{
- ppc_spr_t *spr = &env->spr_cb[num];
-
- /* No SPR should be registered twice. */
- assert(spr->name == NULL);
- assert(name != NULL);
-
- spr->name = name;
- spr->default_value = initial_value;
- env->spr[num] = initial_value;
-
-#ifdef CONFIG_TCG
- spr->uea_read = uea_read;
- spr->uea_write = uea_write;
-# ifndef CONFIG_USER_ONLY
- spr->oea_read = oea_read;
- spr->oea_write = oea_write;
- spr->hea_read = hea_read;
- spr->hea_write = hea_write;
-# endif
-#endif
-#ifdef CONFIG_KVM
- spr->one_reg_id = one_reg_id;
-#endif
-}
-
-/* Generic PowerPC SPRs */
-static void register_generic_sprs(PowerPCCPU *cpu)
-{
- PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
- CPUPPCState *env = &cpu->env;
-
- /* Integer processing */
- spr_register(env, SPR_XER, "XER",
- &spr_read_xer, &spr_write_xer,
- &spr_read_xer, &spr_write_xer,
- 0x00000000);
- /* Branch control */
- spr_register(env, SPR_LR, "LR",
- &spr_read_lr, &spr_write_lr,
- &spr_read_lr, &spr_write_lr,
- 0x00000000);
- spr_register(env, SPR_CTR, "CTR",
- &spr_read_ctr, &spr_write_ctr,
- &spr_read_ctr, &spr_write_ctr,
- 0x00000000);
- /* Interrupt processing */
- spr_register(env, SPR_SRR0, "SRR0",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- spr_register(env, SPR_SRR1, "SRR1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- /* Processor control */
- spr_register(env, SPR_SPRG0, "SPRG0",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- spr_register(env, SPR_SPRG1, "SPRG1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- spr_register(env, SPR_SPRG2, "SPRG2",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
- spr_register(env, SPR_SPRG3, "SPRG3",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-
- spr_register(env, SPR_PVR, "PVR",
- /* Linux permits userspace to read PVR */
-#if defined(CONFIG_LINUX_USER)
- &spr_read_generic,
-#else
- SPR_NOACCESS,
-#endif
- SPR_NOACCESS,
- &spr_read_generic, SPR_NOACCESS,
- pcc->pvr);
-
- /* Register SVR if it's defined to anything else than POWERPC_SVR_NONE */
- if (pcc->svr != POWERPC_SVR_NONE) {
- if (pcc->svr & POWERPC_SVR_E500) {
- spr_register(env, SPR_E500_SVR, "SVR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, SPR_NOACCESS,
- pcc->svr & ~POWERPC_SVR_E500);
- } else {
- spr_register(env, SPR_SVR, "SVR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, SPR_NOACCESS,
- pcc->svr);
- }
- }
-
- /* Time base */
- spr_register(env, SPR_VTBL, "TBL",
- &spr_read_tbl, SPR_NOACCESS,
- &spr_read_tbl, SPR_NOACCESS,
- 0x00000000);
- spr_register(env, SPR_TBL, "TBL",
- &spr_read_tbl, SPR_NOACCESS,
- &spr_read_tbl, &spr_write_tbl,
- 0x00000000);
- spr_register(env, SPR_VTBU, "TBU",
- &spr_read_tbu, SPR_NOACCESS,
- &spr_read_tbu, SPR_NOACCESS,
- 0x00000000);
- spr_register(env, SPR_TBU, "TBU",
- &spr_read_tbu, SPR_NOACCESS,
- &spr_read_tbu, &spr_write_tbu,
- 0x00000000);
-}
-
-void register_non_embedded_sprs(CPUPPCState *env)
-{
- /* Exception processing */
- spr_register_kvm(env, SPR_DSISR, "DSISR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- KVM_REG_PPC_DSISR, 0x00000000);
- spr_register_kvm(env, SPR_DAR, "DAR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- KVM_REG_PPC_DAR, 0x00000000);
- /* Timer */
- spr_register(env, SPR_DECR, "DECR",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_decr, &spr_write_decr,
- 0x00000000);
-}
-
-/* Storage Description Register 1 */
-void register_sdr1_sprs(CPUPPCState *env)
-{
-#ifndef CONFIG_USER_ONLY
- if (env->has_hv_mode) {
- /*
- * SDR1 is a hypervisor resource on CPUs which have a
- * hypervisor mode
- */
- spr_register_hv(env, SPR_SDR1, "SDR1",
- SPR_NOACCESS, SPR_NOACCESS,
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_sdr1,
- 0x00000000);
- } else {
- spr_register(env, SPR_SDR1, "SDR1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_sdr1,
- 0x00000000);
- }
-#endif
-}
-
-/* BATs 0-3 */
-void register_low_BATs(CPUPPCState *env)
-{
-#if !defined(CONFIG_USER_ONLY)
- spr_register(env, SPR_IBAT0U, "IBAT0U",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_ibat, &spr_write_ibatu,
- 0x00000000);
- spr_register(env, SPR_IBAT0L, "IBAT0L",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_ibat, &spr_write_ibatl,
- 0x00000000);
- spr_register(env, SPR_IBAT1U, "IBAT1U",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_ibat, &spr_write_ibatu,
- 0x00000000);
- spr_register(env, SPR_IBAT1L, "IBAT1L",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_ibat, &spr_write_ibatl,
- 0x00000000);
- spr_register(env, SPR_IBAT2U, "IBAT2U",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_ibat, &spr_write_ibatu,
- 0x00000000);
- spr_register(env, SPR_IBAT2L, "IBAT2L",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_ibat, &spr_write_ibatl,
- 0x00000000);
- spr_register(env, SPR_IBAT3U, "IBAT3U",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_ibat, &spr_write_ibatu,
- 0x00000000);
- spr_register(env, SPR_IBAT3L, "IBAT3L",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_ibat, &spr_write_ibatl,
- 0x00000000);
- spr_register(env, SPR_DBAT0U, "DBAT0U",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_dbat, &spr_write_dbatu,
- 0x00000000);
- spr_register(env, SPR_DBAT0L, "DBAT0L",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_dbat, &spr_write_dbatl,
- 0x00000000);
- spr_register(env, SPR_DBAT1U, "DBAT1U",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_dbat, &spr_write_dbatu,
- 0x00000000);
- spr_register(env, SPR_DBAT1L, "DBAT1L",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_dbat, &spr_write_dbatl,
- 0x00000000);
- spr_register(env, SPR_DBAT2U, "DBAT2U",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_dbat, &spr_write_dbatu,
- 0x00000000);
- spr_register(env, SPR_DBAT2L, "DBAT2L",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_dbat, &spr_write_dbatl,
- 0x00000000);
- spr_register(env, SPR_DBAT3U, "DBAT3U",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_dbat, &spr_write_dbatu,
- 0x00000000);
- spr_register(env, SPR_DBAT3L, "DBAT3L",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_dbat, &spr_write_dbatl,
- 0x00000000);
- env->nb_BATs += 4;
-#endif
-}
-
-/* BATs 4-7 */
-void register_high_BATs(CPUPPCState *env)
-{
-#if !defined(CONFIG_USER_ONLY)
- spr_register(env, SPR_IBAT4U, "IBAT4U",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_ibat_h, &spr_write_ibatu_h,
- 0x00000000);
- spr_register(env, SPR_IBAT4L, "IBAT4L",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_ibat_h, &spr_write_ibatl_h,
- 0x00000000);
- spr_register(env, SPR_IBAT5U, "IBAT5U",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_ibat_h, &spr_write_ibatu_h,
- 0x00000000);
- spr_register(env, SPR_IBAT5L, "IBAT5L",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_ibat_h, &spr_write_ibatl_h,
- 0x00000000);
- spr_register(env, SPR_IBAT6U, "IBAT6U",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_ibat_h, &spr_write_ibatu_h,
- 0x00000000);
- spr_register(env, SPR_IBAT6L, "IBAT6L",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_ibat_h, &spr_write_ibatl_h,
- 0x00000000);
- spr_register(env, SPR_IBAT7U, "IBAT7U",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_ibat_h, &spr_write_ibatu_h,
- 0x00000000);
- spr_register(env, SPR_IBAT7L, "IBAT7L",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_ibat_h, &spr_write_ibatl_h,
- 0x00000000);
- spr_register(env, SPR_DBAT4U, "DBAT4U",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_dbat_h, &spr_write_dbatu_h,
- 0x00000000);
- spr_register(env, SPR_DBAT4L, "DBAT4L",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_dbat_h, &spr_write_dbatl_h,
- 0x00000000);
- spr_register(env, SPR_DBAT5U, "DBAT5U",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_dbat_h, &spr_write_dbatu_h,
- 0x00000000);
- spr_register(env, SPR_DBAT5L, "DBAT5L",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_dbat_h, &spr_write_dbatl_h,
- 0x00000000);
- spr_register(env, SPR_DBAT6U, "DBAT6U",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_dbat_h, &spr_write_dbatu_h,
- 0x00000000);
- spr_register(env, SPR_DBAT6L, "DBAT6L",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_dbat_h, &spr_write_dbatl_h,
- 0x00000000);
- spr_register(env, SPR_DBAT7U, "DBAT7U",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_dbat_h, &spr_write_dbatu_h,
- 0x00000000);
- spr_register(env, SPR_DBAT7L, "DBAT7L",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_dbat_h, &spr_write_dbatl_h,
- 0x00000000);
- env->nb_BATs += 4;
-#endif
-}
-
-/* Softare table search registers */
-void register_6xx_7xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways)
-{
-#if !defined(CONFIG_USER_ONLY)
- env->nb_tlb = nb_tlbs;
- env->nb_ways = nb_ways;
- env->id_tlbs = 1;
- env->tlb_type = TLB_6XX;
- spr_register(env, SPR_DMISS, "DMISS",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, SPR_NOACCESS,
- 0x00000000);
- spr_register(env, SPR_DCMP, "DCMP",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, SPR_NOACCESS,
- 0x00000000);
- spr_register(env, SPR_HASH1, "HASH1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, SPR_NOACCESS,
- 0x00000000);
- spr_register(env, SPR_HASH2, "HASH2",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, SPR_NOACCESS,
- 0x00000000);
- spr_register(env, SPR_IMISS, "IMISS",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, SPR_NOACCESS,
- 0x00000000);
- spr_register(env, SPR_ICMP, "ICMP",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, SPR_NOACCESS,
- 0x00000000);
- spr_register(env, SPR_RPA, "RPA",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_generic, &spr_write_generic,
- 0x00000000);
-#endif
-}
-
static void register_745_sprs(CPUPPCState *env)
{
/* SGPRs */
@@ -620,25 +259,6 @@ static void register_iamr_sprs(CPUPPCState *env)
}
#endif /* TARGET_PPC64 */
-void register_thrm_sprs(CPUPPCState *env)
-{
- /* Thermal management */
- spr_register(env, SPR_THRM1, "THRM1",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_thrm, &spr_write_generic,
- 0x00000000);
-
- spr_register(env, SPR_THRM2, "THRM2",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_thrm, &spr_write_generic,
- 0x00000000);
-
- spr_register(env, SPR_THRM3, "THRM3",
- SPR_NOACCESS, SPR_NOACCESS,
- &spr_read_thrm, &spr_write_generic,
- 0x00000000);
-}
-
/* SPR specific to PowerPC 604 implementation */
static void register_604_sprs(CPUPPCState *env)
{
@@ -1025,26 +645,6 @@ static void register_l3_ctrl(CPUPPCState *env)
0x00000000);
}
-void register_usprgh_sprs(CPUPPCState *env)
-{
- spr_register(env, SPR_USPRG4, "USPRG4",
- &spr_read_ureg, SPR_NOACCESS,
- &spr_read_ureg, SPR_NOACCESS,
- 0x00000000);
- spr_register(env, SPR_USPRG5, "USPRG5",
- &spr_read_ureg, SPR_NOACCESS,
- &spr_read_ureg, SPR_NOACCESS,
- 0x00000000);
- spr_register(env, SPR_USPRG6, "USPRG6",
- &spr_read_ureg, SPR_NOACCESS,
- &spr_read_ureg, SPR_NOACCESS,
- 0x00000000);
- spr_register(env, SPR_USPRG7, "USPRG7",
- &spr_read_ureg, SPR_NOACCESS,
- &spr_read_ureg, SPR_NOACCESS,
- 0x00000000);
-}
-
/* PowerPC BookE SPR */
static void register_BookE_sprs(CPUPPCState *env, uint64_t ivor_mask)
{
diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c
index 38fcb5fe5048..9a691d6833fb 100644
--- a/target/ppc/helper_regs.c
+++ b/target/ppc/helper_regs.c
@@ -24,6 +24,8 @@
#include "sysemu/kvm.h"
#include "helper_regs.h"
#include "power8-pmu.h"
+#include "cpu-models.h"
+#include "spr_common.h"
/* Swap temporary saved registers with GPRs */
void hreg_swap_gpr_tgpr(CPUPPCState *env)
@@ -302,3 +304,403 @@ void check_tlb_flush(CPUPPCState *env, bool global)
}
}
#endif
+
+/**
+ * _spr_register
+ *
+ * Register an SPR with all the callbacks required for tcg,
+ * and the ID number for KVM.
+ *
+ * The reason for the conditional compilation is that the tcg functions
+ * may be compiled out, and the system kvm header may not be available
+ * for supplying the ID numbers. This is ugly, but the best we can do.
+ */
+void _spr_register(CPUPPCState *env, int num, const char *name,
+ USR_ARG(spr_callback *uea_read)
+ USR_ARG(spr_callback *uea_write)
+ SYS_ARG(spr_callback *oea_read)
+ SYS_ARG(spr_callback *oea_write)
+ SYS_ARG(spr_callback *hea_read)
+ SYS_ARG(spr_callback *hea_write)
+ KVM_ARG(uint64_t one_reg_id)
+ target_ulong initial_value)
+{
+ ppc_spr_t *spr = &env->spr_cb[num];
+
+ /* No SPR should be registered twice. */
+ assert(spr->name == NULL);
+ assert(name != NULL);
+
+ spr->name = name;
+ spr->default_value = initial_value;
+ env->spr[num] = initial_value;
+
+#ifdef CONFIG_TCG
+ spr->uea_read = uea_read;
+ spr->uea_write = uea_write;
+# ifndef CONFIG_USER_ONLY
+ spr->oea_read = oea_read;
+ spr->oea_write = oea_write;
+ spr->hea_read = hea_read;
+ spr->hea_write = hea_write;
+# endif
+#endif
+#ifdef CONFIG_KVM
+ spr->one_reg_id = one_reg_id;
+#endif
+}
+
+/* Generic PowerPC SPRs */
+void register_generic_sprs(PowerPCCPU *cpu)
+{
+ PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
+ CPUPPCState *env = &cpu->env;
+
+ /* Integer processing */
+ spr_register(env, SPR_XER, "XER",
+ &spr_read_xer, &spr_write_xer,
+ &spr_read_xer, &spr_write_xer,
+ 0x00000000);
+ /* Branch control */
+ spr_register(env, SPR_LR, "LR",
+ &spr_read_lr, &spr_write_lr,
+ &spr_read_lr, &spr_write_lr,
+ 0x00000000);
+ spr_register(env, SPR_CTR, "CTR",
+ &spr_read_ctr, &spr_write_ctr,
+ &spr_read_ctr, &spr_write_ctr,
+ 0x00000000);
+ /* Interrupt processing */
+ spr_register(env, SPR_SRR0, "SRR0",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register(env, SPR_SRR1, "SRR1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ /* Processor control */
+ spr_register(env, SPR_SPRG0, "SPRG0",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register(env, SPR_SPRG1, "SPRG1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register(env, SPR_SPRG2, "SPRG2",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+ spr_register(env, SPR_SPRG3, "SPRG3",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+
+ spr_register(env, SPR_PVR, "PVR",
+ /* Linux permits userspace to read PVR */
+#if defined(CONFIG_LINUX_USER)
+ &spr_read_generic,
+#else
+ SPR_NOACCESS,
+#endif
+ SPR_NOACCESS,
+ &spr_read_generic, SPR_NOACCESS,
+ pcc->pvr);
+
+ /* Register SVR if it's defined to anything else than POWERPC_SVR_NONE */
+ if (pcc->svr != POWERPC_SVR_NONE) {
+ if (pcc->svr & POWERPC_SVR_E500) {
+ spr_register(env, SPR_E500_SVR, "SVR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, SPR_NOACCESS,
+ pcc->svr & ~POWERPC_SVR_E500);
+ } else {
+ spr_register(env, SPR_SVR, "SVR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, SPR_NOACCESS,
+ pcc->svr);
+ }
+ }
+
+ /* Time base */
+ spr_register(env, SPR_VTBL, "TBL",
+ &spr_read_tbl, SPR_NOACCESS,
+ &spr_read_tbl, SPR_NOACCESS,
+ 0x00000000);
+ spr_register(env, SPR_TBL, "TBL",
+ &spr_read_tbl, SPR_NOACCESS,
+ &spr_read_tbl, &spr_write_tbl,
+ 0x00000000);
+ spr_register(env, SPR_VTBU, "TBU",
+ &spr_read_tbu, SPR_NOACCESS,
+ &spr_read_tbu, SPR_NOACCESS,
+ 0x00000000);
+ spr_register(env, SPR_TBU, "TBU",
+ &spr_read_tbu, SPR_NOACCESS,
+ &spr_read_tbu, &spr_write_tbu,
+ 0x00000000);
+}
+
+void register_non_embedded_sprs(CPUPPCState *env)
+{
+ /* Exception processing */
+ spr_register_kvm(env, SPR_DSISR, "DSISR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_DSISR, 0x00000000);
+ spr_register_kvm(env, SPR_DAR, "DAR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_DAR, 0x00000000);
+ /* Timer */
+ spr_register(env, SPR_DECR, "DECR",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_decr, &spr_write_decr,
+ 0x00000000);
+}
+
+/* Storage Description Register 1 */
+void register_sdr1_sprs(CPUPPCState *env)
+{
+#ifndef CONFIG_USER_ONLY
+ if (env->has_hv_mode) {
+ /*
+ * SDR1 is a hypervisor resource on CPUs which have a
+ * hypervisor mode
+ */
+ spr_register_hv(env, SPR_SDR1, "SDR1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_sdr1,
+ 0x00000000);
+ } else {
+ spr_register(env, SPR_SDR1, "SDR1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_sdr1,
+ 0x00000000);
+ }
+#endif
+}
+
+/* BATs 0-3 */
+void register_low_BATs(CPUPPCState *env)
+{
+#if !defined(CONFIG_USER_ONLY)
+ spr_register(env, SPR_IBAT0U, "IBAT0U",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_ibat, &spr_write_ibatu,
+ 0x00000000);
+ spr_register(env, SPR_IBAT0L, "IBAT0L",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_ibat, &spr_write_ibatl,
+ 0x00000000);
+ spr_register(env, SPR_IBAT1U, "IBAT1U",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_ibat, &spr_write_ibatu,
+ 0x00000000);
+ spr_register(env, SPR_IBAT1L, "IBAT1L",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_ibat, &spr_write_ibatl,
+ 0x00000000);
+ spr_register(env, SPR_IBAT2U, "IBAT2U",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_ibat, &spr_write_ibatu,
+ 0x00000000);
+ spr_register(env, SPR_IBAT2L, "IBAT2L",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_ibat, &spr_write_ibatl,
+ 0x00000000);
+ spr_register(env, SPR_IBAT3U, "IBAT3U",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_ibat, &spr_write_ibatu,
+ 0x00000000);
+ spr_register(env, SPR_IBAT3L, "IBAT3L",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_ibat, &spr_write_ibatl,
+ 0x00000000);
+ spr_register(env, SPR_DBAT0U, "DBAT0U",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_dbat, &spr_write_dbatu,
+ 0x00000000);
+ spr_register(env, SPR_DBAT0L, "DBAT0L",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_dbat, &spr_write_dbatl,
+ 0x00000000);
+ spr_register(env, SPR_DBAT1U, "DBAT1U",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_dbat, &spr_write_dbatu,
+ 0x00000000);
+ spr_register(env, SPR_DBAT1L, "DBAT1L",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_dbat, &spr_write_dbatl,
+ 0x00000000);
+ spr_register(env, SPR_DBAT2U, "DBAT2U",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_dbat, &spr_write_dbatu,
+ 0x00000000);
+ spr_register(env, SPR_DBAT2L, "DBAT2L",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_dbat, &spr_write_dbatl,
+ 0x00000000);
+ spr_register(env, SPR_DBAT3U, "DBAT3U",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_dbat, &spr_write_dbatu,
+ 0x00000000);
+ spr_register(env, SPR_DBAT3L, "DBAT3L",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_dbat, &spr_write_dbatl,
+ 0x00000000);
+ env->nb_BATs += 4;
+#endif
+}
+
+/* BATs 4-7 */
+void register_high_BATs(CPUPPCState *env)
+{
+#if !defined(CONFIG_USER_ONLY)
+ spr_register(env, SPR_IBAT4U, "IBAT4U",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_ibat_h, &spr_write_ibatu_h,
+ 0x00000000);
+ spr_register(env, SPR_IBAT4L, "IBAT4L",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_ibat_h, &spr_write_ibatl_h,
+ 0x00000000);
+ spr_register(env, SPR_IBAT5U, "IBAT5U",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_ibat_h, &spr_write_ibatu_h,
+ 0x00000000);
+ spr_register(env, SPR_IBAT5L, "IBAT5L",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_ibat_h, &spr_write_ibatl_h,
+ 0x00000000);
+ spr_register(env, SPR_IBAT6U, "IBAT6U",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_ibat_h, &spr_write_ibatu_h,
+ 0x00000000);
+ spr_register(env, SPR_IBAT6L, "IBAT6L",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_ibat_h, &spr_write_ibatl_h,
+ 0x00000000);
+ spr_register(env, SPR_IBAT7U, "IBAT7U",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_ibat_h, &spr_write_ibatu_h,
+ 0x00000000);
+ spr_register(env, SPR_IBAT7L, "IBAT7L",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_ibat_h, &spr_write_ibatl_h,
+ 0x00000000);
+ spr_register(env, SPR_DBAT4U, "DBAT4U",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_dbat_h, &spr_write_dbatu_h,
+ 0x00000000);
+ spr_register(env, SPR_DBAT4L, "DBAT4L",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_dbat_h, &spr_write_dbatl_h,
+ 0x00000000);
+ spr_register(env, SPR_DBAT5U, "DBAT5U",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_dbat_h, &spr_write_dbatu_h,
+ 0x00000000);
+ spr_register(env, SPR_DBAT5L, "DBAT5L",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_dbat_h, &spr_write_dbatl_h,
+ 0x00000000);
+ spr_register(env, SPR_DBAT6U, "DBAT6U",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_dbat_h, &spr_write_dbatu_h,
+ 0x00000000);
+ spr_register(env, SPR_DBAT6L, "DBAT6L",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_dbat_h, &spr_write_dbatl_h,
+ 0x00000000);
+ spr_register(env, SPR_DBAT7U, "DBAT7U",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_dbat_h, &spr_write_dbatu_h,
+ 0x00000000);
+ spr_register(env, SPR_DBAT7L, "DBAT7L",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_dbat_h, &spr_write_dbatl_h,
+ 0x00000000);
+ env->nb_BATs += 4;
+#endif
+}
+
+/* Softare table search registers */
+void register_6xx_7xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways)
+{
+#if !defined(CONFIG_USER_ONLY)
+ env->nb_tlb = nb_tlbs;
+ env->nb_ways = nb_ways;
+ env->id_tlbs = 1;
+ env->tlb_type = TLB_6XX;
+ spr_register(env, SPR_DMISS, "DMISS",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, SPR_NOACCESS,
+ 0x00000000);
+ spr_register(env, SPR_DCMP, "DCMP",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, SPR_NOACCESS,
+ 0x00000000);
+ spr_register(env, SPR_HASH1, "HASH1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, SPR_NOACCESS,
+ 0x00000000);
+ spr_register(env, SPR_HASH2, "HASH2",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, SPR_NOACCESS,
+ 0x00000000);
+ spr_register(env, SPR_IMISS, "IMISS",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, SPR_NOACCESS,
+ 0x00000000);
+ spr_register(env, SPR_ICMP, "ICMP",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, SPR_NOACCESS,
+ 0x00000000);
+ spr_register(env, SPR_RPA, "RPA",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ 0x00000000);
+#endif
+}
+
+void register_thrm_sprs(CPUPPCState *env)
+{
+ /* Thermal management */
+ spr_register(env, SPR_THRM1, "THRM1",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_thrm, &spr_write_generic,
+ 0x00000000);
+
+ spr_register(env, SPR_THRM2, "THRM2",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_thrm, &spr_write_generic,
+ 0x00000000);
+
+ spr_register(env, SPR_THRM3, "THRM3",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_thrm, &spr_write_generic,
+ 0x00000000);
+}
+
+void register_usprgh_sprs(CPUPPCState *env)
+{
+ spr_register(env, SPR_USPRG4, "USPRG4",
+ &spr_read_ureg, SPR_NOACCESS,
+ &spr_read_ureg, SPR_NOACCESS,
+ 0x00000000);
+ spr_register(env, SPR_USPRG5, "USPRG5",
+ &spr_read_ureg, SPR_NOACCESS,
+ &spr_read_ureg, SPR_NOACCESS,
+ 0x00000000);
+ spr_register(env, SPR_USPRG6, "USPRG6",
+ &spr_read_ureg, SPR_NOACCESS,
+ &spr_read_ureg, SPR_NOACCESS,
+ 0x00000000);
+ spr_register(env, SPR_USPRG7, "USPRG7",
+ &spr_read_ureg, SPR_NOACCESS,
+ &spr_read_ureg, SPR_NOACCESS,
+ 0x00000000);
+}
--
2.34.1
^ permalink raw reply related [flat|nested] 41+ messages in thread* Re: [PULL 00/39] ppc queue
2022-02-18 10:37 [PULL 00/39] ppc queue Cédric Le Goater
` (38 preceding siblings ...)
2022-02-18 10:38 ` [PULL 39/39] target/ppc: Move common SPR functions out of cpu_init Cédric Le Goater
@ 2022-02-20 19:28 ` Peter Maydell
39 siblings, 0 replies; 41+ messages in thread
From: Peter Maydell @ 2022-02-20 19:28 UTC (permalink / raw)
To: Cédric Le Goater; +Cc: qemu-ppc, qemu-devel
On Fri, 18 Feb 2022 at 10:38, Cédric Le Goater <clg@kaod.org> wrote:
>
> The following changes since commit c13b8e9973635f34f3ce4356af27a311c993729c:
>
> Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20220216' into staging (2022-02-16 09:57:11 +0000)
>
> are available in the Git repository at:
>
> https://github.com/legoater/qemu/ tags/pull-ppc-20220218
>
> for you to fetch changes up to 65e0446c86ee70d2125c1f1d1e36e6c2dfb08642:
>
> target/ppc: Move common SPR functions out of cpu_init (2022-02-18 08:34:15 +0100)
>
> ----------------------------------------------------------------
> ppc-7.0 queue
>
> * target/ppc: SPR registration cleanups (Fabiano)
> * ppc: nested KVM HV for spapr virtual hypervisor (Nicholas)
> * spapr: nvdimm: Introduce spapr-nvdimm device (Shivaprasad)
>
> ----------------------------------------------------------------
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/7.0
for any user-visible changes.
-- PMM
^ permalink raw reply [flat|nested] 41+ messages in thread