From: Stafford Horne <shorne@gmail.com>
To: QEMU Development <qemu-devel@nongnu.org>
Cc: "Peter Maydell" <peter.maydell@linaro.org>,
"Stafford Horne" <shorne@gmail.com>,
"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
"Jia Liu" <proljc@gmail.com>
Subject: [PATCH v3 2/6] hw/openrisc/openrisc_sim: Parameterize initialization
Date: Sat, 19 Feb 2022 15:42:06 +0900 [thread overview]
Message-ID: <20220219064210.3145381-3-shorne@gmail.com> (raw)
In-Reply-To: <20220219064210.3145381-1-shorne@gmail.com>
Move magic numbers to variables and enums. These will be reused for
upcoming fdt initialization.
Signed-off-by: Stafford Horne <shorne@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
hw/openrisc/openrisc_sim.c | 42 ++++++++++++++++++++++++++++++--------
1 file changed, 34 insertions(+), 8 deletions(-)
diff --git a/hw/openrisc/openrisc_sim.c b/hw/openrisc/openrisc_sim.c
index 26d2370e60..d12b3e0c5e 100644
--- a/hw/openrisc/openrisc_sim.c
+++ b/hw/openrisc/openrisc_sim.c
@@ -49,6 +49,29 @@ typedef struct Or1ksimState {
} Or1ksimState;
+enum {
+ OR1KSIM_DRAM,
+ OR1KSIM_UART,
+ OR1KSIM_ETHOC,
+ OR1KSIM_OMPIC,
+};
+
+enum {
+ OR1KSIM_OMPIC_IRQ = 1,
+ OR1KSIM_UART_IRQ = 2,
+ OR1KSIM_ETHOC_IRQ = 4,
+};
+
+static const struct MemmapEntry {
+ hwaddr base;
+ hwaddr size;
+} or1ksim_memmap[] = {
+ [OR1KSIM_DRAM] = { 0x00000000, 0 },
+ [OR1KSIM_UART] = { 0x90000000, 0x100 },
+ [OR1KSIM_ETHOC] = { 0x92000000, 0x800 },
+ [OR1KSIM_OMPIC] = { 0x98000000, 16 },
+};
+
static struct openrisc_boot_info {
uint32_t bootstrap_pc;
} boot_info;
@@ -176,21 +199,24 @@ static void openrisc_sim_init(MachineState *machine)
memory_region_add_subregion(get_system_memory(), 0, ram);
if (nd_table[0].used) {
- openrisc_sim_net_init(0x92000000, 0x92000400, smp_cpus,
- cpus, 4, nd_table);
+ openrisc_sim_net_init(or1ksim_memmap[OR1KSIM_ETHOC].base,
+ or1ksim_memmap[OR1KSIM_ETHOC].base + 0x400,
+ smp_cpus, cpus,
+ OR1KSIM_ETHOC_IRQ, nd_table);
}
if (smp_cpus > 1) {
- openrisc_sim_ompic_init(0x98000000, smp_cpus, cpus, 1);
+ openrisc_sim_ompic_init(or1ksim_memmap[OR1KSIM_OMPIC].base, smp_cpus,
+ cpus, OR1KSIM_OMPIC_IRQ);
- serial_irq = qemu_irq_split(get_cpu_irq(cpus, 0, 2),
- get_cpu_irq(cpus, 1, 2));
+ serial_irq = qemu_irq_split(get_cpu_irq(cpus, 0, OR1KSIM_UART_IRQ),
+ get_cpu_irq(cpus, 1, OR1KSIM_UART_IRQ));
} else {
- serial_irq = get_cpu_irq(cpus, 0, 2);
+ serial_irq = get_cpu_irq(cpus, 0, OR1KSIM_UART_IRQ);
}
- serial_mm_init(get_system_memory(), 0x90000000, 0, serial_irq,
- 115200, serial_hd(0), DEVICE_NATIVE_ENDIAN);
+ serial_mm_init(get_system_memory(), or1ksim_memmap[OR1KSIM_UART].base, 0,
+ serial_irq, 115200, serial_hd(0), DEVICE_NATIVE_ENDIAN);
openrisc_load_kernel(ram_size, kernel_filename);
}
--
2.31.1
next prev parent reply other threads:[~2022-02-19 7:18 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-02-19 6:42 [PATCH v3 0/6] OpenRISC Device Tree Generation Stafford Horne
2022-02-19 6:42 ` [PATCH v3 1/6] hw/openrisc/openrisc_sim: Create machine state for or1ksim Stafford Horne
2022-02-19 6:42 ` Stafford Horne [this message]
2022-02-19 6:42 ` [PATCH v3 3/6] hw/openrisc/openrisc_sim: Use IRQ splitter when connecting UART Stafford Horne
2022-02-19 13:01 ` Peter Maydell
2022-02-20 20:06 ` Philippe Mathieu-Daudé
2022-02-21 0:08 ` Stafford Horne
2022-02-19 6:42 ` [PATCH v3 4/6] hw/openrisc/openrisc_sim: Increase max_cpus to 4 Stafford Horne
2022-02-19 13:02 ` Peter Maydell
2022-02-20 20:07 ` Philippe Mathieu-Daudé
2022-02-20 23:59 ` Stafford Horne
2022-02-19 6:42 ` [PATCH v3 5/6] hw/openrisc/openrisc_sim: Add automatic device tree generation Stafford Horne
2022-02-19 13:06 ` Peter Maydell
2022-02-19 6:42 ` [PATCH v3 6/6] hw/openrisc/openrisc_sim: Add support for initrd loading Stafford Horne
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