From: Stafford Horne <shorne@gmail.com>
To: QEMU Development <qemu-devel@nongnu.org>
Cc: Peter Maydell <peter.maydell@linaro.org>,
Stafford Horne <shorne@gmail.com>, Jia Liu <proljc@gmail.com>
Subject: [PATCH v3 4/6] hw/openrisc/openrisc_sim: Increase max_cpus to 4
Date: Sat, 19 Feb 2022 15:42:08 +0900 [thread overview]
Message-ID: <20220219064210.3145381-5-shorne@gmail.com> (raw)
In-Reply-To: <20220219064210.3145381-1-shorne@gmail.com>
Now that we no longer have a limit of 2 CPUs due to fixing the
IRQ routing issues we can increase the max. Here we increase
the limit to 4, we could go higher, but currently OMPIC has a
limit of 4, so we align with that.
Signed-off-by: Stafford Horne <shorne@gmail.com>
---
hw/openrisc/openrisc_sim.c | 8 +++++---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/hw/openrisc/openrisc_sim.c b/hw/openrisc/openrisc_sim.c
index 5bfbac00f8..8cfb92bec6 100644
--- a/hw/openrisc/openrisc_sim.c
+++ b/hw/openrisc/openrisc_sim.c
@@ -37,6 +37,8 @@
#define KERNEL_LOAD_ADDR 0x100
+#define OR1KSIM_CPUS_MAX 4
+
#define TYPE_OR1KSIM_MACHINE MACHINE_TYPE_NAME("or1k-sim")
#define OR1KSIM_MACHINE(obj) \
OBJECT_CHECK(Or1ksimState, (obj), TYPE_OR1KSIM_MACHINE)
@@ -197,12 +199,12 @@ static void openrisc_sim_init(MachineState *machine)
{
ram_addr_t ram_size = machine->ram_size;
const char *kernel_filename = machine->kernel_filename;
- OpenRISCCPU *cpus[2] = {};
+ OpenRISCCPU *cpus[OR1KSIM_CPUS_MAX] = {};
MemoryRegion *ram;
int n;
unsigned int smp_cpus = machine->smp.cpus;
- assert(smp_cpus >= 1 && smp_cpus <= 2);
+ assert(smp_cpus >= 1 && smp_cpus <= OR1KSIM_CPUS_MAX);
for (n = 0; n < smp_cpus; n++) {
cpus[n] = OPENRISC_CPU(cpu_create(machine->cpu_type));
if (cpus[n] == NULL) {
@@ -243,7 +245,7 @@ static void openrisc_sim_machine_init(ObjectClass *oc, void *data)
mc->desc = "or1k simulation";
mc->init = openrisc_sim_init;
- mc->max_cpus = 2;
+ mc->max_cpus = OR1KSIM_CPUS_MAX;
mc->is_default = true;
mc->default_cpu_type = OPENRISC_CPU_TYPE_NAME("or1200");
}
--
2.31.1
next prev parent reply other threads:[~2022-02-19 6:53 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-02-19 6:42 [PATCH v3 0/6] OpenRISC Device Tree Generation Stafford Horne
2022-02-19 6:42 ` [PATCH v3 1/6] hw/openrisc/openrisc_sim: Create machine state for or1ksim Stafford Horne
2022-02-19 6:42 ` [PATCH v3 2/6] hw/openrisc/openrisc_sim: Parameterize initialization Stafford Horne
2022-02-19 6:42 ` [PATCH v3 3/6] hw/openrisc/openrisc_sim: Use IRQ splitter when connecting UART Stafford Horne
2022-02-19 13:01 ` Peter Maydell
2022-02-20 20:06 ` Philippe Mathieu-Daudé
2022-02-21 0:08 ` Stafford Horne
2022-02-19 6:42 ` Stafford Horne [this message]
2022-02-19 13:02 ` [PATCH v3 4/6] hw/openrisc/openrisc_sim: Increase max_cpus to 4 Peter Maydell
2022-02-20 20:07 ` Philippe Mathieu-Daudé
2022-02-20 23:59 ` Stafford Horne
2022-02-19 6:42 ` [PATCH v3 5/6] hw/openrisc/openrisc_sim: Add automatic device tree generation Stafford Horne
2022-02-19 13:06 ` Peter Maydell
2022-02-19 6:42 ` [PATCH v3 6/6] hw/openrisc/openrisc_sim: Add support for initrd loading Stafford Horne
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