From: Anup Patel <anup@brainfault.org>
To: Peter Maydell <peter.maydell@linaro.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Alistair Francis <Alistair.Francis@wdc.com>,
Sagar Karandikar <sagark@eecs.berkeley.edu>
Cc: qemu-riscv@nongnu.org, Frank Chang <frank.chang@sifive.com>,
Anup Patel <anup@brainfault.org>,
qemu-devel@nongnu.org,
Alistair Francis <alistair.francis@wdc.com>,
Atish Patra <atishp@atishpatra.org>,
Bin Meng <bmeng.cn@gmail.com>
Subject: [PATCH v10 5/5] hw/riscv: virt: Increase maximum number of allowed CPUs
Date: Sun, 20 Feb 2022 14:25:26 +0530 [thread overview]
Message-ID: <20220220085526.808674-6-anup@brainfault.org> (raw)
In-Reply-To: <20220220085526.808674-1-anup@brainfault.org>
From: Anup Patel <anup.patel@wdc.com>
To facilitate software development of RISC-V systems with large number
of HARTs, we increase the maximum number of allowed CPUs to 512 (2^9).
We also add a detailed source level comments about limit defines which
impact the physical address space utilization.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
---
hw/riscv/virt.c | 10 ++++++++++
include/hw/riscv/virt.h | 2 +-
2 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 94fbf63ec8..da50cbed43 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -45,6 +45,16 @@
#include "hw/pci-host/gpex.h"
#include "hw/display/ramfb.h"
+/*
+ * The virt machine physical address space used by some of the devices
+ * namely ACLINT, PLIC, APLIC, and IMSIC depend on number of Sockets,
+ * number of CPUs, and number of IMSIC guest files.
+ *
+ * Various limits defined by VIRT_SOCKETS_MAX_BITS, VIRT_CPUS_MAX_BITS,
+ * and VIRT_IRQCHIP_MAX_GUESTS_BITS are tuned for maximum utilization
+ * of virt machine physical address space.
+ */
+
#define VIRT_IMSIC_GROUP_MAX_SIZE (1U << IMSIC_MMIO_GROUP_MIN_SHIFT)
#if VIRT_IMSIC_GROUP_MAX_SIZE < \
IMSIC_GROUP_SIZE(VIRT_CPUS_MAX_BITS, VIRT_IRQCHIP_MAX_GUESTS_BITS)
diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
index d248d0dfa0..78b058ec86 100644
--- a/include/hw/riscv/virt.h
+++ b/include/hw/riscv/virt.h
@@ -24,7 +24,7 @@
#include "hw/block/flash.h"
#include "qom/object.h"
-#define VIRT_CPUS_MAX_BITS 3
+#define VIRT_CPUS_MAX_BITS 9
#define VIRT_CPUS_MAX (1 << VIRT_CPUS_MAX_BITS)
#define VIRT_SOCKETS_MAX_BITS 2
#define VIRT_SOCKETS_MAX (1 << VIRT_SOCKETS_MAX_BITS)
--
2.25.1
next prev parent reply other threads:[~2022-02-20 9:08 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-02-20 8:55 [PATCH v10 0/5] QEMU RISC-V AIA support Anup Patel
2022-02-20 8:55 ` [PATCH v10 1/5] hw/riscv: virt: Add optional AIA APLIC support to virt machine Anup Patel
2022-02-20 8:55 ` [PATCH v10 2/5] hw/intc: Add RISC-V AIA IMSIC device emulation Anup Patel
2022-02-20 8:55 ` [PATCH v10 3/5] hw/riscv: virt: Add optional AIA IMSIC support to virt machine Anup Patel
2022-02-20 8:55 ` [PATCH v10 4/5] docs/system: riscv: Document AIA options for " Anup Patel
2022-02-20 8:55 ` Anup Patel [this message]
2022-02-21 7:11 ` [PATCH v10 0/5] QEMU RISC-V AIA support Alistair Francis
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20220220085526.808674-6-anup@brainfault.org \
--to=anup@brainfault.org \
--cc=Alistair.Francis@wdc.com \
--cc=atishp@atishpatra.org \
--cc=bmeng.cn@gmail.com \
--cc=frank.chang@sifive.com \
--cc=palmer@dabbelt.com \
--cc=peter.maydell@linaro.org \
--cc=qemu-devel@nongnu.org \
--cc=qemu-riscv@nongnu.org \
--cc=sagark@eecs.berkeley.edu \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).