From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 10/26] target/arm: Unindent unnecessary else-clause
Date: Mon, 21 Feb 2022 09:27:44 +0000 [thread overview]
Message-ID: <20220221092800.404870-11-peter.maydell@linaro.org> (raw)
In-Reply-To: <20220221092800.404870-1-peter.maydell@linaro.org>
Now that the if() branch of the condition in aarch64_max_initfn()
returns early, we don't need to keep the rest of the code in
the function inside an else block. Remove the else, unindenting
that code.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Andrew Jones <drjones@redhat.com>
Reviewed-by: Alexander Graf <agraf@csgraf.de>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220204165506.2846058-5-peter.maydell@linaro.org
---
target/arm/cpu64.c | 289 +++++++++++++++++++++++----------------------
1 file changed, 146 insertions(+), 143 deletions(-)
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index ae2e431247f..2280e476fd7 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -707,176 +707,179 @@ static void aarch64_host_initfn(Object *obj)
static void aarch64_max_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
+ uint64_t t;
+ uint32_t u;
if (kvm_enabled()) {
/* With KVM, '-cpu max' is identical to '-cpu host' */
aarch64_host_initfn(obj);
return;
- } else {
- uint64_t t;
- uint32_t u;
- aarch64_a57_initfn(obj);
+ }
- /*
- * Reset MIDR so the guest doesn't mistake our 'max' CPU type for a real
- * one and try to apply errata workarounds or use impdef features we
- * don't provide.
- * An IMPLEMENTER field of 0 means "reserved for software use";
- * ARCHITECTURE must be 0xf indicating "v7 or later, check ID registers
- * to see which features are present";
- * the VARIANT, PARTNUM and REVISION fields are all implementation
- * defined and we choose to define PARTNUM just in case guest
- * code needs to distinguish this QEMU CPU from other software
- * implementations, though this shouldn't be needed.
- */
- t = FIELD_DP64(0, MIDR_EL1, IMPLEMENTER, 0);
- t = FIELD_DP64(t, MIDR_EL1, ARCHITECTURE, 0xf);
- t = FIELD_DP64(t, MIDR_EL1, PARTNUM, 'Q');
- t = FIELD_DP64(t, MIDR_EL1, VARIANT, 0);
- t = FIELD_DP64(t, MIDR_EL1, REVISION, 0);
- cpu->midr = t;
+ /* '-cpu max' for TCG: we currently do this as "A57 with extra things" */
- t = cpu->isar.id_aa64isar0;
- t = FIELD_DP64(t, ID_AA64ISAR0, AES, 2); /* AES + PMULL */
- t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1);
- t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 2); /* SHA512 */
- t = FIELD_DP64(t, ID_AA64ISAR0, CRC32, 1);
- t = FIELD_DP64(t, ID_AA64ISAR0, ATOMIC, 2);
- t = FIELD_DP64(t, ID_AA64ISAR0, RDM, 1);
- t = FIELD_DP64(t, ID_AA64ISAR0, SHA3, 1);
- t = FIELD_DP64(t, ID_AA64ISAR0, SM3, 1);
- t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 1);
- t = FIELD_DP64(t, ID_AA64ISAR0, DP, 1);
- t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 1);
- t = FIELD_DP64(t, ID_AA64ISAR0, TS, 2); /* v8.5-CondM */
- t = FIELD_DP64(t, ID_AA64ISAR0, TLB, 2); /* FEAT_TLBIRANGE */
- t = FIELD_DP64(t, ID_AA64ISAR0, RNDR, 1);
- cpu->isar.id_aa64isar0 = t;
+ aarch64_a57_initfn(obj);
- t = cpu->isar.id_aa64isar1;
- t = FIELD_DP64(t, ID_AA64ISAR1, DPB, 2);
- t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 1);
- t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1);
- t = FIELD_DP64(t, ID_AA64ISAR1, SB, 1);
- t = FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1);
- t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 1);
- t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 1);
- t = FIELD_DP64(t, ID_AA64ISAR1, LRCPC, 2); /* ARMv8.4-RCPC */
- t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1);
- cpu->isar.id_aa64isar1 = t;
+ /*
+ * Reset MIDR so the guest doesn't mistake our 'max' CPU type for a real
+ * one and try to apply errata workarounds or use impdef features we
+ * don't provide.
+ * An IMPLEMENTER field of 0 means "reserved for software use";
+ * ARCHITECTURE must be 0xf indicating "v7 or later, check ID registers
+ * to see which features are present";
+ * the VARIANT, PARTNUM and REVISION fields are all implementation
+ * defined and we choose to define PARTNUM just in case guest
+ * code needs to distinguish this QEMU CPU from other software
+ * implementations, though this shouldn't be needed.
+ */
+ t = FIELD_DP64(0, MIDR_EL1, IMPLEMENTER, 0);
+ t = FIELD_DP64(t, MIDR_EL1, ARCHITECTURE, 0xf);
+ t = FIELD_DP64(t, MIDR_EL1, PARTNUM, 'Q');
+ t = FIELD_DP64(t, MIDR_EL1, VARIANT, 0);
+ t = FIELD_DP64(t, MIDR_EL1, REVISION, 0);
+ cpu->midr = t;
- t = cpu->isar.id_aa64pfr0;
- t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1);
- t = FIELD_DP64(t, ID_AA64PFR0, FP, 1);
- t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1);
- t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1);
- t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1);
- cpu->isar.id_aa64pfr0 = t;
+ t = cpu->isar.id_aa64isar0;
+ t = FIELD_DP64(t, ID_AA64ISAR0, AES, 2); /* AES + PMULL */
+ t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1);
+ t = FIELD_DP64(t, ID_AA64ISAR0, SHA2, 2); /* SHA512 */
+ t = FIELD_DP64(t, ID_AA64ISAR0, CRC32, 1);
+ t = FIELD_DP64(t, ID_AA64ISAR0, ATOMIC, 2);
+ t = FIELD_DP64(t, ID_AA64ISAR0, RDM, 1);
+ t = FIELD_DP64(t, ID_AA64ISAR0, SHA3, 1);
+ t = FIELD_DP64(t, ID_AA64ISAR0, SM3, 1);
+ t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 1);
+ t = FIELD_DP64(t, ID_AA64ISAR0, DP, 1);
+ t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 1);
+ t = FIELD_DP64(t, ID_AA64ISAR0, TS, 2); /* v8.5-CondM */
+ t = FIELD_DP64(t, ID_AA64ISAR0, TLB, 2); /* FEAT_TLBIRANGE */
+ t = FIELD_DP64(t, ID_AA64ISAR0, RNDR, 1);
+ cpu->isar.id_aa64isar0 = t;
- t = cpu->isar.id_aa64pfr1;
- t = FIELD_DP64(t, ID_AA64PFR1, BT, 1);
- t = FIELD_DP64(t, ID_AA64PFR1, SSBS, 2);
- /*
- * Begin with full support for MTE. This will be downgraded to MTE=0
- * during realize if the board provides no tag memory, much like
- * we do for EL2 with the virtualization=on property.
- */
- t = FIELD_DP64(t, ID_AA64PFR1, MTE, 3);
- cpu->isar.id_aa64pfr1 = t;
+ t = cpu->isar.id_aa64isar1;
+ t = FIELD_DP64(t, ID_AA64ISAR1, DPB, 2);
+ t = FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 1);
+ t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1);
+ t = FIELD_DP64(t, ID_AA64ISAR1, SB, 1);
+ t = FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1);
+ t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 1);
+ t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 1);
+ t = FIELD_DP64(t, ID_AA64ISAR1, LRCPC, 2); /* ARMv8.4-RCPC */
+ t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1);
+ cpu->isar.id_aa64isar1 = t;
- t = cpu->isar.id_aa64mmfr0;
- t = FIELD_DP64(t, ID_AA64MMFR0, PARANGE, 5); /* PARange: 48 bits */
- cpu->isar.id_aa64mmfr0 = t;
+ t = cpu->isar.id_aa64pfr0;
+ t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1);
+ t = FIELD_DP64(t, ID_AA64PFR0, FP, 1);
+ t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1);
+ t = FIELD_DP64(t, ID_AA64PFR0, SEL2, 1);
+ t = FIELD_DP64(t, ID_AA64PFR0, DIT, 1);
+ cpu->isar.id_aa64pfr0 = t;
- t = cpu->isar.id_aa64mmfr1;
- t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* HPD */
- t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1);
- t = FIELD_DP64(t, ID_AA64MMFR1, VH, 1);
- t = FIELD_DP64(t, ID_AA64MMFR1, PAN, 2); /* ATS1E1 */
- t = FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* VMID16 */
- t = FIELD_DP64(t, ID_AA64MMFR1, XNX, 1); /* TTS2UXN */
- cpu->isar.id_aa64mmfr1 = t;
+ t = cpu->isar.id_aa64pfr1;
+ t = FIELD_DP64(t, ID_AA64PFR1, BT, 1);
+ t = FIELD_DP64(t, ID_AA64PFR1, SSBS, 2);
+ /*
+ * Begin with full support for MTE. This will be downgraded to MTE=0
+ * during realize if the board provides no tag memory, much like
+ * we do for EL2 with the virtualization=on property.
+ */
+ t = FIELD_DP64(t, ID_AA64PFR1, MTE, 3);
+ cpu->isar.id_aa64pfr1 = t;
- t = cpu->isar.id_aa64mmfr2;
- t = FIELD_DP64(t, ID_AA64MMFR2, UAO, 1);
- t = FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* TTCNP */
- t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* TTST */
- cpu->isar.id_aa64mmfr2 = t;
+ t = cpu->isar.id_aa64mmfr0;
+ t = FIELD_DP64(t, ID_AA64MMFR0, PARANGE, 5); /* PARange: 48 bits */
+ cpu->isar.id_aa64mmfr0 = t;
- t = cpu->isar.id_aa64zfr0;
- t = FIELD_DP64(t, ID_AA64ZFR0, SVEVER, 1);
- t = FIELD_DP64(t, ID_AA64ZFR0, AES, 2); /* PMULL */
- t = FIELD_DP64(t, ID_AA64ZFR0, BITPERM, 1);
- t = FIELD_DP64(t, ID_AA64ZFR0, BFLOAT16, 1);
- t = FIELD_DP64(t, ID_AA64ZFR0, SHA3, 1);
- t = FIELD_DP64(t, ID_AA64ZFR0, SM4, 1);
- t = FIELD_DP64(t, ID_AA64ZFR0, I8MM, 1);
- t = FIELD_DP64(t, ID_AA64ZFR0, F32MM, 1);
- t = FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1);
- cpu->isar.id_aa64zfr0 = t;
+ t = cpu->isar.id_aa64mmfr1;
+ t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* HPD */
+ t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1);
+ t = FIELD_DP64(t, ID_AA64MMFR1, VH, 1);
+ t = FIELD_DP64(t, ID_AA64MMFR1, PAN, 2); /* ATS1E1 */
+ t = FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* VMID16 */
+ t = FIELD_DP64(t, ID_AA64MMFR1, XNX, 1); /* TTS2UXN */
+ cpu->isar.id_aa64mmfr1 = t;
- /* Replicate the same data to the 32-bit id registers. */
- u = cpu->isar.id_isar5;
- u = FIELD_DP32(u, ID_ISAR5, AES, 2); /* AES + PMULL */
- u = FIELD_DP32(u, ID_ISAR5, SHA1, 1);
- u = FIELD_DP32(u, ID_ISAR5, SHA2, 1);
- u = FIELD_DP32(u, ID_ISAR5, CRC32, 1);
- u = FIELD_DP32(u, ID_ISAR5, RDM, 1);
- u = FIELD_DP32(u, ID_ISAR5, VCMA, 1);
- cpu->isar.id_isar5 = u;
+ t = cpu->isar.id_aa64mmfr2;
+ t = FIELD_DP64(t, ID_AA64MMFR2, UAO, 1);
+ t = FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* TTCNP */
+ t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* TTST */
+ cpu->isar.id_aa64mmfr2 = t;
- u = cpu->isar.id_isar6;
- u = FIELD_DP32(u, ID_ISAR6, JSCVT, 1);
- u = FIELD_DP32(u, ID_ISAR6, DP, 1);
- u = FIELD_DP32(u, ID_ISAR6, FHM, 1);
- u = FIELD_DP32(u, ID_ISAR6, SB, 1);
- u = FIELD_DP32(u, ID_ISAR6, SPECRES, 1);
- u = FIELD_DP32(u, ID_ISAR6, BF16, 1);
- u = FIELD_DP32(u, ID_ISAR6, I8MM, 1);
- cpu->isar.id_isar6 = u;
+ t = cpu->isar.id_aa64zfr0;
+ t = FIELD_DP64(t, ID_AA64ZFR0, SVEVER, 1);
+ t = FIELD_DP64(t, ID_AA64ZFR0, AES, 2); /* PMULL */
+ t = FIELD_DP64(t, ID_AA64ZFR0, BITPERM, 1);
+ t = FIELD_DP64(t, ID_AA64ZFR0, BFLOAT16, 1);
+ t = FIELD_DP64(t, ID_AA64ZFR0, SHA3, 1);
+ t = FIELD_DP64(t, ID_AA64ZFR0, SM4, 1);
+ t = FIELD_DP64(t, ID_AA64ZFR0, I8MM, 1);
+ t = FIELD_DP64(t, ID_AA64ZFR0, F32MM, 1);
+ t = FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1);
+ cpu->isar.id_aa64zfr0 = t;
- u = cpu->isar.id_pfr0;
- u = FIELD_DP32(u, ID_PFR0, DIT, 1);
- cpu->isar.id_pfr0 = u;
+ /* Replicate the same data to the 32-bit id registers. */
+ u = cpu->isar.id_isar5;
+ u = FIELD_DP32(u, ID_ISAR5, AES, 2); /* AES + PMULL */
+ u = FIELD_DP32(u, ID_ISAR5, SHA1, 1);
+ u = FIELD_DP32(u, ID_ISAR5, SHA2, 1);
+ u = FIELD_DP32(u, ID_ISAR5, CRC32, 1);
+ u = FIELD_DP32(u, ID_ISAR5, RDM, 1);
+ u = FIELD_DP32(u, ID_ISAR5, VCMA, 1);
+ cpu->isar.id_isar5 = u;
- u = cpu->isar.id_pfr2;
- u = FIELD_DP32(u, ID_PFR2, SSBS, 1);
- cpu->isar.id_pfr2 = u;
+ u = cpu->isar.id_isar6;
+ u = FIELD_DP32(u, ID_ISAR6, JSCVT, 1);
+ u = FIELD_DP32(u, ID_ISAR6, DP, 1);
+ u = FIELD_DP32(u, ID_ISAR6, FHM, 1);
+ u = FIELD_DP32(u, ID_ISAR6, SB, 1);
+ u = FIELD_DP32(u, ID_ISAR6, SPECRES, 1);
+ u = FIELD_DP32(u, ID_ISAR6, BF16, 1);
+ u = FIELD_DP32(u, ID_ISAR6, I8MM, 1);
+ cpu->isar.id_isar6 = u;
- u = cpu->isar.id_mmfr3;
- u = FIELD_DP32(u, ID_MMFR3, PAN, 2); /* ATS1E1 */
- cpu->isar.id_mmfr3 = u;
+ u = cpu->isar.id_pfr0;
+ u = FIELD_DP32(u, ID_PFR0, DIT, 1);
+ cpu->isar.id_pfr0 = u;
- u = cpu->isar.id_mmfr4;
- u = FIELD_DP32(u, ID_MMFR4, HPDS, 1); /* AA32HPD */
- u = FIELD_DP32(u, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
- u = FIELD_DP32(u, ID_MMFR4, CNP, 1); /* TTCNP */
- u = FIELD_DP32(u, ID_MMFR4, XNX, 1); /* TTS2UXN */
- cpu->isar.id_mmfr4 = u;
+ u = cpu->isar.id_pfr2;
+ u = FIELD_DP32(u, ID_PFR2, SSBS, 1);
+ cpu->isar.id_pfr2 = u;
- t = cpu->isar.id_aa64dfr0;
- t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* v8.4-PMU */
- cpu->isar.id_aa64dfr0 = t;
+ u = cpu->isar.id_mmfr3;
+ u = FIELD_DP32(u, ID_MMFR3, PAN, 2); /* ATS1E1 */
+ cpu->isar.id_mmfr3 = u;
- u = cpu->isar.id_dfr0;
- u = FIELD_DP32(u, ID_DFR0, PERFMON, 5); /* v8.4-PMU */
- cpu->isar.id_dfr0 = u;
+ u = cpu->isar.id_mmfr4;
+ u = FIELD_DP32(u, ID_MMFR4, HPDS, 1); /* AA32HPD */
+ u = FIELD_DP32(u, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
+ u = FIELD_DP32(u, ID_MMFR4, CNP, 1); /* TTCNP */
+ u = FIELD_DP32(u, ID_MMFR4, XNX, 1); /* TTS2UXN */
+ cpu->isar.id_mmfr4 = u;
- u = cpu->isar.mvfr1;
- u = FIELD_DP32(u, MVFR1, FPHP, 3); /* v8.2-FP16 */
- u = FIELD_DP32(u, MVFR1, SIMDHP, 2); /* v8.2-FP16 */
- cpu->isar.mvfr1 = u;
+ t = cpu->isar.id_aa64dfr0;
+ t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* v8.4-PMU */
+ cpu->isar.id_aa64dfr0 = t;
+
+ u = cpu->isar.id_dfr0;
+ u = FIELD_DP32(u, ID_DFR0, PERFMON, 5); /* v8.4-PMU */
+ cpu->isar.id_dfr0 = u;
+
+ u = cpu->isar.mvfr1;
+ u = FIELD_DP32(u, MVFR1, FPHP, 3); /* v8.2-FP16 */
+ u = FIELD_DP32(u, MVFR1, SIMDHP, 2); /* v8.2-FP16 */
+ cpu->isar.mvfr1 = u;
#ifdef CONFIG_USER_ONLY
- /* For usermode -cpu max we can use a larger and more efficient DCZ
- * blocksize since we don't have to follow what the hardware does.
- */
- cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */
- cpu->dcz_blocksize = 7; /* 512 bytes */
+ /*
+ * For usermode -cpu max we can use a larger and more efficient DCZ
+ * blocksize since we don't have to follow what the hardware does.
+ */
+ cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */
+ cpu->dcz_blocksize = 7; /* 512 bytes */
#endif
- bitmap_fill(cpu->sve_vq_supported, ARM_MAX_VQ);
- }
+ bitmap_fill(cpu->sve_vq_supported, ARM_MAX_VQ);
aarch64_add_pauth_properties(obj);
aarch64_add_sve_properties(obj);
--
2.25.1
next prev parent reply other threads:[~2022-02-21 9:52 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-02-21 9:27 [PULL 00/26] target-arm queue Peter Maydell
2022-02-21 9:27 ` [PULL 01/26] MAINTAINERS: Adding myself as a reviewer of some components Peter Maydell
2022-02-21 9:27 ` [PULL 02/26] tests/qtest: add qtests for npcm7xx sdhci Peter Maydell
2022-02-21 9:27 ` [PULL 03/26] hvf: arm: Use macros for sysreg shift/masking Peter Maydell
2022-02-21 9:27 ` [PULL 04/26] hvf: arm: Handle unknown ID registers as RES0 Peter Maydell
2022-02-21 9:27 ` [PULL 05/26] Mark remaining global TypeInfo instances as const Peter Maydell
2022-02-21 9:27 ` [PULL 06/26] checkpatch: Ensure that TypeInfos are const Peter Maydell
2022-02-21 9:27 ` [PULL 07/26] target/arm: Move '-cpu host' code to cpu64.c Peter Maydell
2022-02-21 9:27 ` [PULL 08/26] target/arm: Use aarch64_cpu_register() for 'host' CPU type Peter Maydell
2022-02-21 9:27 ` [PULL 09/26] target/arm: Make KVM -cpu max exactly like -cpu host Peter Maydell
2022-02-21 9:27 ` Peter Maydell [this message]
2022-02-21 9:27 ` [PULL 11/26] target/arm: Fix '-cpu max' for HVF Peter Maydell
2022-02-21 9:27 ` [PULL 12/26] target/arm: Support PAuth extension for hvf Peter Maydell
2022-02-21 9:27 ` [PULL 13/26] Kconfig: Add I2C_DEVICES device group Peter Maydell
2022-02-21 9:27 ` [PULL 14/26] Kconfig: Add 'imply I2C_DEVICES' on boards with available i2c bus Peter Maydell
2022-02-21 9:27 ` [PULL 15/26] hw/arm/armv7m: Handle disconnected clock inputs Peter Maydell
2022-02-21 9:27 ` [PULL 16/26] include: Move qemu_madvise() and related #defines to new qemu/madvise.h Peter Maydell
2022-02-21 9:27 ` [PULL 17/26] include: Move qemu_mprotect_*() to new qemu/mprotect.h Peter Maydell
2022-02-21 9:27 ` [PULL 18/26] include: Move QEMU_MAP_* constants to mmap-alloc.h Peter Maydell
2022-02-21 9:27 ` [PULL 19/26] include: Move qemu_[id]cache_* declarations to new qemu/cacheinfo.h Peter Maydell
2022-02-21 9:27 ` [PULL 20/26] include: Move hardware version declarations to new qemu/hw-version.h Peter Maydell
2022-02-21 9:27 ` [PULL 21/26] MAINTAINERS: Add Akihiko Odaki to macOS-relateds Peter Maydell
2022-02-21 9:27 ` [PULL 22/26] hw/timer: fix a9gtimer vmstate Peter Maydell
2022-02-21 9:27 ` [PULL 23/26] hw/arm: add initial mori-bmc board Peter Maydell
2022-02-21 9:27 ` [PULL 24/26] ui/cocoa: Remove allowedFileTypes restriction in SavePanel Peter Maydell
2022-02-21 9:27 ` [PULL 25/26] ui/cocoa: Do not alert even without block devices Peter Maydell
2022-02-21 9:28 ` [PULL 26/26] ui/cocoa: Fix the leak of qemu_console_get_label Peter Maydell
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