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[213.175.37.10]) by smtp.gmail.com with ESMTPSA id o9sm7213780ejn.16.2022.02.23.01.31.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Feb 2022 01:31:52 -0800 (PST) Date: Wed, 23 Feb 2022 10:31:51 +0100 From: Igor Mammedov To: "Dr. David Alan Gilbert" Subject: Re: [PATCH RFCv2 2/4] i386/pc: relocate 4g start to 1T where applicable Message-ID: <20220223103151.70f70410@redhat.com> In-Reply-To: References: <20220207202422.31582-3-joao.m.martins@oracle.com> <20220214155318.3ce80da0@redhat.com> <20220214163158.4c4b210b@redhat.com> <20220215095358.5qcrgwlasheu63uj@sirius.home.kraxel.org> <20220222094602.66d55613@redhat.com> <20220222094255.as2alzu65rhateml@sirius.home.kraxel.org> <20220223094343.2e600a22@redhat.com> X-Mailer: Claws Mail 4.0.0 (GTK+ 3.24.31; x86_64-redhat-linux-gnu) MIME-Version: 1.0 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=imammedo@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=170.10.129.124; envelope-from=imammedo@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -28 X-Spam_score: -2.9 X-Spam_bar: -- X-Spam_report: (-2.9 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.082, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Daniel P. =?UTF-8?B?QmVycmFuZ8Op?=" , Eduardo Habkost , "Michael S . Tsirkin" , Richard Henderson , qemu-devel@nongnu.org, Daniel Jordan , David Edmondson , Alex Williamson , Gerd Hoffmann , Suravee Suthikulpanit , Ani Sinha , Paolo Bonzini , Joao Martins Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Wed, 23 Feb 2022 09:16:51 +0000 "Dr. David Alan Gilbert" wrote: > * Igor Mammedov (imammedo@redhat.com) wrote: > > On Tue, 22 Feb 2022 10:42:55 +0100 > > Gerd Hoffmann wrote: > > > > > Hi, > > > > > > > > And the upstream code is now pretty much identical except for the > > > > > default; note that for TCG you do need to keep to 40 I think. > > > > > > > > will TCG work with 40bits on host that supports less than that? > > > > > > When I understand things correctly the problem is that the phys-bits > > > limit applies to the npt/ept tables too, effectively restricting guest > > > physical address space to host physical address space. > > > > > > TCG is not affected by that and should work just fine. > > > > > > Not sure what happens if you turn off npt/ept and run on softmmu. > > > Possibly that works fine too. > > > > > > > Also quick look at host-phys-bits shows that it affects only 'host' > > > > cpu model and is NOP for all other models. > > > > > > I don't think so. microvm forces host-phys-bits=on and that works with > > > all cpu models. > > > > I just don't see how host-phys-bits can work for other than 'host' cpu model. > > It's true that property is available for all cpu models, but the field it sets > > is only used in target/i386/host-cpu.c, the same applies to host-phys-bits-limit. > > Am I missing something? > > The hook in kvm/kvm-cpu.c kvm_cpu_realizefn: > > /* > * The realize order is important, since x86_cpu_realize() checks if > * nothing else has been set by the user (or by accelerators) in > * cpu->ucode_rev and cpu->phys_bits, and updates the CPUID results in > * mwait.ecx. > * This accel realization code also assumes cpu features are already expanded. > * > * realize order: > * > * x86_cpu_realize(): > * -> x86_cpu_expand_features() > * -> cpu_exec_realizefn(): > * -> accel_cpu_realizefn() > * kvm_cpu_realizefn() -> host_cpu_realizefn() > * -> check/update ucode_rev, phys_bits, mwait > */ Thanks, I didn't expect host_cpu_realizefn being called from elsewhere beside of cpu model it belongs to or models inherited from it. > > Dave > > > > > > > take care, > > > Gerd > > > > >