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Fri, 25 Feb 2022 00:32:29 -0800 (PST) Received: from localhost ([2409:10:24a0:4700:e8ad:216a:2a9d:6d0c]) by smtp.gmail.com with ESMTPSA id k12-20020a056a00168c00b004e15818cda3sm2379975pfc.114.2022.02.25.00.32.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Feb 2022 00:32:28 -0800 (PST) From: Stafford Horne To: QEMU Development Subject: [PULL 0/6] OpenRISC DTS Generation patches for 7.0 Date: Fri, 25 Feb 2022 17:32:16 +0900 Message-Id: <20220225083222.1174517-1-shorne@gmail.com> X-Mailer: git-send-email 2.31.1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::534 (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::534; envelope-from=shorne@gmail.com; helo=mail-pg1-x534.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Stafford Horne Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" The following changes since commit 4aa2e497a98bafe962e72997f67a369e4b52d9c1: Merge remote-tracking branch 'remotes/berrange-gitlab/tags/misc-next-pull-request' into staging (2022-02-23 09:25:05 +0000) are available in the Git repository at: git://github.com/stffrdhrn/qemu.git tags/or1k-pull-request for you to fetch changes up to 94c71f14e9ca15ede4172e0826d690b15069a7f8: hw/openrisc/openrisc_sim: Add support for initrd loading (2022-02-25 15:42:23 +0900) ---------------------------------------------------------------- OpenRISC patches - Add automatic DTS generation to openrisc_sim ---------------------------------------------------------------- Stafford Horne (6): hw/openrisc/openrisc_sim: Create machine state for or1ksim hw/openrisc/openrisc_sim: Parameterize initialization hw/openrisc/openrisc_sim: Use IRQ splitter when connecting UART hw/openrisc/openrisc_sim: Increase max_cpus to 4 hw/openrisc/openrisc_sim: Add automatic device tree generation hw/openrisc/openrisc_sim: Add support for initrd loading configs/targets/or1k-softmmu.mak | 1 + hw/openrisc/openrisc_sim.c | 308 ++++++++++++++++++++++++++++++++++++--- 2 files changed, 285 insertions(+), 24 deletions(-)