From: Stafford Horne <shorne@gmail.com>
To: QEMU Development <qemu-devel@nongnu.org>
Cc: "Peter Maydell" <peter.maydell@linaro.org>,
"Stafford Horne" <shorne@gmail.com>,
"Philippe Mathieu-Daudé" <f4bug@amsat.org>
Subject: [PULL 4/6] hw/openrisc/openrisc_sim: Increase max_cpus to 4
Date: Fri, 25 Feb 2022 17:32:20 +0900 [thread overview]
Message-ID: <20220225083222.1174517-5-shorne@gmail.com> (raw)
In-Reply-To: <20220225083222.1174517-1-shorne@gmail.com>
Now that we no longer have a limit of 2 CPUs due to fixing the
IRQ routing issues we can increase the max. Here we increase
the limit to 4, we could go higher, but currently OMPIC has a
limit of 4, so we align with that.
Signed-off-by: Stafford Horne <shorne@gmail.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
hw/openrisc/openrisc_sim.c | 8 +++++---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/hw/openrisc/openrisc_sim.c b/hw/openrisc/openrisc_sim.c
index 5bfbac00f8..8cfb92bec6 100644
--- a/hw/openrisc/openrisc_sim.c
+++ b/hw/openrisc/openrisc_sim.c
@@ -37,6 +37,8 @@
#define KERNEL_LOAD_ADDR 0x100
+#define OR1KSIM_CPUS_MAX 4
+
#define TYPE_OR1KSIM_MACHINE MACHINE_TYPE_NAME("or1k-sim")
#define OR1KSIM_MACHINE(obj) \
OBJECT_CHECK(Or1ksimState, (obj), TYPE_OR1KSIM_MACHINE)
@@ -197,12 +199,12 @@ static void openrisc_sim_init(MachineState *machine)
{
ram_addr_t ram_size = machine->ram_size;
const char *kernel_filename = machine->kernel_filename;
- OpenRISCCPU *cpus[2] = {};
+ OpenRISCCPU *cpus[OR1KSIM_CPUS_MAX] = {};
MemoryRegion *ram;
int n;
unsigned int smp_cpus = machine->smp.cpus;
- assert(smp_cpus >= 1 && smp_cpus <= 2);
+ assert(smp_cpus >= 1 && smp_cpus <= OR1KSIM_CPUS_MAX);
for (n = 0; n < smp_cpus; n++) {
cpus[n] = OPENRISC_CPU(cpu_create(machine->cpu_type));
if (cpus[n] == NULL) {
@@ -243,7 +245,7 @@ static void openrisc_sim_machine_init(ObjectClass *oc, void *data)
mc->desc = "or1k simulation";
mc->init = openrisc_sim_init;
- mc->max_cpus = 2;
+ mc->max_cpus = OR1KSIM_CPUS_MAX;
mc->is_default = true;
mc->default_cpu_type = OPENRISC_CPU_TYPE_NAME("or1200");
}
--
2.31.1
next prev parent reply other threads:[~2022-02-25 9:26 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-02-25 8:32 [PULL 0/6] OpenRISC DTS Generation patches for 7.0 Stafford Horne
2022-02-25 8:32 ` [PULL 1/6] hw/openrisc/openrisc_sim: Create machine state for or1ksim Stafford Horne
2022-02-25 8:32 ` [PULL 2/6] hw/openrisc/openrisc_sim: Parameterize initialization Stafford Horne
2022-02-25 8:32 ` [PULL 3/6] hw/openrisc/openrisc_sim: Use IRQ splitter when connecting UART Stafford Horne
2022-02-25 8:32 ` Stafford Horne [this message]
2022-02-25 8:32 ` [PULL 5/6] hw/openrisc/openrisc_sim: Add automatic device tree generation Stafford Horne
2022-02-25 8:32 ` [PULL 6/6] hw/openrisc/openrisc_sim: Add support for initrd loading Stafford Horne
2022-02-25 13:52 ` [PULL 0/6] OpenRISC DTS Generation patches for 7.0 Peter Maydell
2022-02-26 1:22 ` Stafford Horne
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