From: "Alex Bennée" <alex.bennee@linaro.org>
To: qemu-devel@nongnu.org
Cc: fam@euphon.net, "Peter Maydell" <peter.maydell@linaro.org>,
"Keith Packard" <keithp@keithp.com>,
berrange@redhat.com, sw@weilnetz.de,
"Andrew Strauss" <astrauss11@gmail.com>,
richard.henderson@linaro.org, f4bug@amsat.org,
qemu-arm@nongnu.org, stefanha@redhat.com, crosa@redhat.com,
pbonzini@redhat.com, "Alex Bennée" <alex.bennee@linaro.org>,
aurelien@aurel32.net
Subject: [PATCH v2 17/18] semihosting/arm-compat: replace heuristic for softmmu SYS_HEAPINFO
Date: Fri, 25 Feb 2022 17:20:20 +0000 [thread overview]
Message-ID: <20220225172021.3493923-18-alex.bennee@linaro.org> (raw)
In-Reply-To: <20220225172021.3493923-1-alex.bennee@linaro.org>
The previous numbers were a guess at best and rather arbitrary without
taking into account anything that might be loaded. Instead of using
guesses based on the state of registers implement a new function that:
a) scans the MemoryRegions for the largest RAM block
b) iterates through all "ROM" blobs looking for the biggest gap
The "ROM" blobs include all code loaded via -kernel and the various
-device loader techniques.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Cc: Andrew Strauss <astrauss11@gmail.com>
Cc: Keith Packard <keithp@keithp.com>
Message-Id: <20210601090715.22330-1-alex.bennee@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20220210113021.3799514-2-alex.bennee@linaro.org>
---
v7
- remove stray comment
---
include/hw/loader.h | 14 ++++
hw/core/loader.c | 86 +++++++++++++++++++++++
semihosting/arm-compat-semi.c | 124 +++++++++++++++++-----------------
3 files changed, 163 insertions(+), 61 deletions(-)
diff --git a/include/hw/loader.h b/include/hw/loader.h
index 4fa485bd61..5572108ba5 100644
--- a/include/hw/loader.h
+++ b/include/hw/loader.h
@@ -343,4 +343,18 @@ int rom_add_option(const char *file, int32_t bootindex);
* overflow on real hardware too. */
#define UBOOT_MAX_GUNZIP_BYTES (64 << 20)
+typedef struct RomGap {
+ hwaddr base;
+ size_t size;
+} RomGap;
+
+/**
+ * rom_find_largest_gap_between: return largest gap between ROMs in given range
+ *
+ * Given a range of addresses, this function finds the largest
+ * contiguous subrange which has no ROMs loaded to it. That is,
+ * it finds the biggest gap which is free for use for other things.
+ */
+RomGap rom_find_largest_gap_between(hwaddr base, size_t size);
+
#endif
diff --git a/hw/core/loader.c b/hw/core/loader.c
index 19edb928e9..ca2f2431fb 100644
--- a/hw/core/loader.c
+++ b/hw/core/loader.c
@@ -1333,6 +1333,92 @@ static Rom *find_rom(hwaddr addr, size_t size)
return NULL;
}
+typedef struct RomSec {
+ hwaddr base;
+ int se; /* start/end flag */
+} RomSec;
+
+
+/*
+ * Sort into address order. We break ties between rom-startpoints
+ * and rom-endpoints in favour of the startpoint, by sorting the 0->1
+ * transition before the 1->0 transition. Either way round would
+ * work, but this way saves a little work later by avoiding
+ * dealing with "gaps" of 0 length.
+ */
+static gint sort_secs(gconstpointer a, gconstpointer b)
+{
+ RomSec *ra = (RomSec *) a;
+ RomSec *rb = (RomSec *) b;
+
+ if (ra->base == rb->base) {
+ return ra->se - rb->se;
+ }
+ return ra->base > rb->base ? 1 : -1;
+}
+
+static GList *add_romsec_to_list(GList *secs, hwaddr base, int se)
+{
+ RomSec *cand = g_new(RomSec, 1);
+ cand->base = base;
+ cand->se = se;
+ return g_list_prepend(secs, cand);
+}
+
+RomGap rom_find_largest_gap_between(hwaddr base, size_t size)
+{
+ Rom *rom;
+ RomSec *cand;
+ RomGap res = {0, 0};
+ hwaddr gapstart = base;
+ GList *it, *secs = NULL;
+ int count = 0;
+
+ QTAILQ_FOREACH(rom, &roms, next) {
+ /* Ignore blobs being loaded to special places */
+ if (rom->mr || rom->fw_file) {
+ continue;
+ }
+ /* ignore anything finishing bellow base */
+ if (rom->addr + rom->romsize <= base) {
+ continue;
+ }
+ /* ignore anything starting above the region */
+ if (rom->addr >= base + size) {
+ continue;
+ }
+
+ /* Save the start and end of each relevant ROM */
+ secs = add_romsec_to_list(secs, rom->addr, 1);
+
+ if (rom->addr + rom->romsize < base + size) {
+ secs = add_romsec_to_list(secs, rom->addr + rom->romsize, -1);
+ }
+ }
+
+ /* sentinel */
+ secs = add_romsec_to_list(secs, base + size, 1);
+
+ secs = g_list_sort(secs, sort_secs);
+
+ for (it = g_list_first(secs); it; it = g_list_next(it)) {
+ cand = (RomSec *) it->data;
+ if (count == 0 && count + cand->se == 1) {
+ size_t gap = cand->base - gapstart;
+ if (gap > res.size) {
+ res.base = gapstart;
+ res.size = gap;
+ }
+ } else if (count == 1 && count + cand->se == 0) {
+ gapstart = cand->base;
+ }
+ count += cand->se;
+ }
+
+ g_list_free_full(secs, g_free);
+ return res;
+}
+
/*
* Copies memory from registered ROMs to dest. Any memory that is contained in
* a ROM between addr and addr + size is copied. Note that this can involve
diff --git a/semihosting/arm-compat-semi.c b/semihosting/arm-compat-semi.c
index 37963becae..7a51fd0737 100644
--- a/semihosting/arm-compat-semi.c
+++ b/semihosting/arm-compat-semi.c
@@ -44,6 +44,7 @@
#define COMMON_SEMI_HEAP_SIZE (128 * 1024 * 1024)
#else
#include "qemu/cutils.h"
+#include "hw/loader.h"
#ifdef TARGET_ARM
#include "hw/arm/boot.h"
#endif
@@ -144,33 +145,69 @@ typedef struct GuestFD {
static GArray *guestfd_array;
#ifndef CONFIG_USER_ONLY
-#include "exec/address-spaces.h"
-/*
- * Find the base of a RAM region containing the specified address
+
+/**
+ * common_semi_find_bases: find information about ram and heap base
+ *
+ * This function attempts to provide meaningful numbers for RAM and
+ * HEAP base addresses. The rambase is simply the lowest addressable
+ * RAM position. For the heapbase we ask the loader to scan the
+ * address space and the largest available gap by querying the "ROM"
+ * regions.
+ *
+ * Returns: a structure with the numbers we need.
*/
-static inline hwaddr
-common_semi_find_region_base(hwaddr addr)
+
+typedef struct LayoutInfo {
+ target_ulong rambase;
+ size_t ramsize;
+ hwaddr heapbase;
+ hwaddr heaplimit;
+} LayoutInfo;
+
+static bool find_ram_cb(Int128 start, Int128 len, const MemoryRegion *mr,
+ hwaddr offset_in_region, void *opaque)
{
- MemoryRegion *subregion;
+ LayoutInfo *info = (LayoutInfo *) opaque;
+ uint64_t size = int128_get64(len);
+
+ if (!mr->ram || mr->readonly) {
+ return false;
+ }
+
+ if (size > info->ramsize) {
+ info->rambase = int128_get64(start);
+ info->ramsize = size;
+ }
+
+ /* search exhaustively for largest RAM */
+ return false;
+}
+
+static LayoutInfo common_semi_find_bases(CPUState *cs)
+{
+ FlatView *fv;
+ LayoutInfo info = { 0, 0, 0, 0 };
+
+ RCU_READ_LOCK_GUARD();
+
+ fv = address_space_to_flatview(cs->as);
+ flatview_for_each_range(fv, find_ram_cb, &info);
/*
- * Find the chunk of R/W memory containing the address. This is
- * used for the SYS_HEAPINFO semihosting call, which should
- * probably be using information from the loaded application.
+ * If we have found the RAM lets iterate through the ROM blobs to
+ * work out the best place for the remainder of RAM and split it
+ * equally between stack and heap.
*/
- QTAILQ_FOREACH(subregion, &get_system_memory()->subregions,
- subregions_link) {
- if (subregion->ram && !subregion->readonly) {
- Int128 top128 = int128_add(int128_make64(subregion->addr),
- subregion->size);
- Int128 addr128 = int128_make64(addr);
- if (subregion->addr <= addr && int128_lt(addr128, top128)) {
- return subregion->addr;
- }
- }
+ if (info.rambase || info.ramsize > 0) {
+ RomGap gap = rom_find_largest_gap_between(info.rambase, info.ramsize);
+ info.heapbase = gap.base;
+ info.heaplimit = gap.base + gap.size;
}
- return 0;
+
+ return info;
}
+
#endif
#ifdef TARGET_ARM
@@ -204,28 +241,6 @@ common_semi_sys_exit_extended(CPUState *cs, int nr)
return (nr == TARGET_SYS_EXIT_EXTENDED || is_a64(cs->env_ptr));
}
-#ifndef CONFIG_USER_ONLY
-#include "hw/arm/boot.h"
-static inline target_ulong
-common_semi_rambase(CPUState *cs)
-{
- CPUArchState *env = cs->env_ptr;
- const struct arm_boot_info *info = env->boot_info;
- target_ulong sp;
-
- if (info) {
- return info->loader_start;
- }
-
- if (is_a64(env)) {
- sp = env->xregs[31];
- } else {
- sp = env->regs[13];
- }
- return common_semi_find_region_base(sp);
-}
-#endif
-
#endif /* TARGET_ARM */
#ifdef TARGET_RISCV
@@ -251,17 +266,6 @@ common_semi_sys_exit_extended(CPUState *cs, int nr)
return (nr == TARGET_SYS_EXIT_EXTENDED || sizeof(target_ulong) == 8);
}
-#ifndef CONFIG_USER_ONLY
-
-static inline target_ulong
-common_semi_rambase(CPUState *cs)
-{
- RISCVCPU *cpu = RISCV_CPU(cs);
- CPURISCVState *env = &cpu->env;
- return common_semi_find_region_base(env->gpr[xSP]);
-}
-#endif
-
#endif
/*
@@ -1165,12 +1169,12 @@ target_ulong do_common_semihosting(CPUState *cs)
case TARGET_SYS_HEAPINFO:
{
target_ulong retvals[4];
- target_ulong limit;
int i;
#ifdef CONFIG_USER_ONLY
TaskState *ts = cs->opaque;
+ target_ulong limit;
#else
- target_ulong rambase = common_semi_rambase(cs);
+ LayoutInfo info = common_semi_find_bases(cs);
#endif
GET_ARG(0);
@@ -1201,12 +1205,10 @@ target_ulong do_common_semihosting(CPUState *cs)
retvals[2] = ts->stack_base;
retvals[3] = 0; /* Stack limit. */
#else
- limit = current_machine->ram_size;
- /* TODO: Make this use the limit of the loaded application. */
- retvals[0] = rambase + limit / 2;
- retvals[1] = rambase + limit;
- retvals[2] = rambase + limit; /* Stack base */
- retvals[3] = rambase; /* Stack limit. */
+ retvals[0] = info.heapbase; /* Heap Base */
+ retvals[1] = info.heaplimit; /* Heap Limit */
+ retvals[2] = info.heaplimit; /* Stack base */
+ retvals[3] = info.heapbase; /* Stack limit. */
#endif
for (i = 0; i < ARRAY_SIZE(retvals); i++) {
--
2.30.2
next prev parent reply other threads:[~2022-02-25 18:18 UTC|newest]
Thread overview: 41+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-02-25 17:20 [PATCH v2 00/18] testing and semihosting pre-PR Alex Bennée
2022-02-25 17:20 ` [PATCH v2 01/18] tests/docker: restore TESTS/IMAGES filtering Alex Bennée
2022-02-25 20:11 ` Richard Henderson
2022-02-25 17:20 ` [PATCH v2 02/18] tests/docker: add NOUSER for alpine image Alex Bennée
2022-02-25 20:12 ` Richard Henderson
2022-02-25 17:20 ` [PATCH v2 03/18] tests/lcitool: update to latest version Alex Bennée
2022-02-25 17:57 ` Peter Maydell
2022-02-28 16:44 ` Alex Bennée
2022-02-28 16:49 ` Peter Maydell
2022-02-25 17:20 ` [PATCH v2 04/18] tests/docker: update debian-arm64-cross with lci-tool Alex Bennée
2022-02-28 8:39 ` Thomas Huth
2022-02-28 9:20 ` Daniel P. Berrangé
2022-02-28 9:28 ` Daniel P. Berrangé
2022-02-28 14:39 ` Alex Bennée
2022-03-01 10:03 ` Daniel P. Berrangé
2022-02-25 17:20 ` [PATCH v2 05/18] tests/docker: update debian-s390x-cross with lcitool Alex Bennée
2022-02-25 20:15 ` Richard Henderson
2022-02-25 17:20 ` [PATCH v2 06/18] tests/docker: introduce debian-riscv64-test-cross Alex Bennée
2022-02-25 17:20 ` [PATCH v2 07/18] scripts/ci: add build env rules for aarch32 on aarch64 Alex Bennée
2022-02-25 20:17 ` Richard Henderson
2022-02-25 17:20 ` [PATCH v2 08/18] scripts/ci: allow for a secondary runner Alex Bennée
2022-02-25 20:18 ` Richard Henderson
2022-02-25 17:20 ` [PATCH v2 09/18] gitlab: add a new aarch32 custom runner definition Alex Bennée
2022-02-25 20:25 ` Richard Henderson
2022-02-25 17:20 ` [PATCH v2 10/18] tests/tcg/ppc64: clean-up handling of byte-reverse Alex Bennée
2022-02-25 20:26 ` Richard Henderson
2022-02-25 17:20 ` [PATCH v2 11/18] tests/tcg: build sha1-vector with O3 and compare Alex Bennée
2022-02-25 17:20 ` [PATCH v2 12/18] tests/tcg: add sha512 test Alex Bennée
2022-02-25 17:20 ` [PATCH v2 13/18] tests/tcg: add vectorised sha512 versions Alex Bennée
2022-02-25 22:52 ` Richard Henderson
2022-02-28 13:58 ` Alex Bennée
2022-02-28 16:43 ` Alex Bennée
2022-02-28 20:56 ` Richard Henderson
2022-02-25 17:20 ` [PATCH v2 14/18] travis.yml: Update the s390x jobs to Ubuntu Focal Alex Bennée
2022-02-25 20:27 ` Richard Henderson
2022-02-25 17:20 ` [PATCH v2 15/18] gitlab: upgrade the job definition for s390x to 20.04 Alex Bennée
2022-02-25 20:28 ` Richard Henderson
2022-02-25 17:20 ` [PATCH v2 16/18] tests/tcg: completely disable threadcount for sh4 Alex Bennée
2022-02-25 20:29 ` Richard Henderson
2022-02-25 17:20 ` Alex Bennée [this message]
2022-02-25 17:20 ` [PATCH v2 18/18] tests/tcg: port SYS_HEAPINFO to a system test Alex Bennée
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20220225172021.3493923-18-alex.bennee@linaro.org \
--to=alex.bennee@linaro.org \
--cc=astrauss11@gmail.com \
--cc=aurelien@aurel32.net \
--cc=berrange@redhat.com \
--cc=crosa@redhat.com \
--cc=f4bug@amsat.org \
--cc=fam@euphon.net \
--cc=keithp@keithp.com \
--cc=pbonzini@redhat.com \
--cc=peter.maydell@linaro.org \
--cc=qemu-arm@nongnu.org \
--cc=qemu-devel@nongnu.org \
--cc=richard.henderson@linaro.org \
--cc=stefanha@redhat.com \
--cc=sw@weilnetz.de \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).