From: Stafford Horne <shorne@gmail.com>
To: QEMU Development <qemu-devel@nongnu.org>
Cc: "Stafford Horne" <shorne@gmail.com>,
"Philippe Mathieu-Daudé" <f4bug@amsat.org>
Subject: [PULL v2 1/6] hw/openrisc/openrisc_sim: Create machine state for or1ksim
Date: Sat, 26 Feb 2022 10:59:19 +0900 [thread overview]
Message-ID: <20220226015924.1293022-2-shorne@gmail.com> (raw)
In-Reply-To: <20220226015924.1293022-1-shorne@gmail.com>
This will allow us to attach machine state attributes like
the device tree fdt.
Signed-off-by: Stafford Horne <shorne@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
hw/openrisc/openrisc_sim.c | 30 ++++++++++++++++++++++++++++--
1 file changed, 28 insertions(+), 2 deletions(-)
diff --git a/hw/openrisc/openrisc_sim.c b/hw/openrisc/openrisc_sim.c
index 73fe383c2d..26d2370e60 100644
--- a/hw/openrisc/openrisc_sim.c
+++ b/hw/openrisc/openrisc_sim.c
@@ -37,6 +37,18 @@
#define KERNEL_LOAD_ADDR 0x100
+#define TYPE_OR1KSIM_MACHINE MACHINE_TYPE_NAME("or1k-sim")
+#define OR1KSIM_MACHINE(obj) \
+ OBJECT_CHECK(Or1ksimState, (obj), TYPE_OR1KSIM_MACHINE)
+
+typedef struct Or1ksimState {
+ /*< private >*/
+ MachineState parent_obj;
+
+ /*< public >*/
+
+} Or1ksimState;
+
static struct openrisc_boot_info {
uint32_t bootstrap_pc;
} boot_info;
@@ -183,8 +195,10 @@ static void openrisc_sim_init(MachineState *machine)
openrisc_load_kernel(ram_size, kernel_filename);
}
-static void openrisc_sim_machine_init(MachineClass *mc)
+static void openrisc_sim_machine_init(ObjectClass *oc, void *data)
{
+ MachineClass *mc = MACHINE_CLASS(oc);
+
mc->desc = "or1k simulation";
mc->init = openrisc_sim_init;
mc->max_cpus = 2;
@@ -192,4 +206,16 @@ static void openrisc_sim_machine_init(MachineClass *mc)
mc->default_cpu_type = OPENRISC_CPU_TYPE_NAME("or1200");
}
-DEFINE_MACHINE("or1k-sim", openrisc_sim_machine_init)
+static const TypeInfo or1ksim_machine_typeinfo = {
+ .name = TYPE_OR1KSIM_MACHINE,
+ .parent = TYPE_MACHINE,
+ .class_init = openrisc_sim_machine_init,
+ .instance_size = sizeof(Or1ksimState),
+};
+
+static void or1ksim_machine_init_register_types(void)
+{
+ type_register_static(&or1ksim_machine_typeinfo);
+}
+
+type_init(or1ksim_machine_init_register_types)
--
2.31.1
next prev parent reply other threads:[~2022-02-26 2:03 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-02-26 1:59 [PULL v2 0/6] OpenRISC DTS Generation patches for 7.0 Stafford Horne
2022-02-26 1:59 ` Stafford Horne [this message]
2022-02-26 1:59 ` [PULL v2 2/6] hw/openrisc/openrisc_sim: Parameterize initialization Stafford Horne
2022-02-26 1:59 ` [PULL v2 3/6] hw/openrisc/openrisc_sim: Use IRQ splitter when connecting UART Stafford Horne
2022-02-26 1:59 ` [PULL v2 4/6] hw/openrisc/openrisc_sim: Increase max_cpus to 4 Stafford Horne
2022-02-26 1:59 ` [PULL v2 5/6] hw/openrisc/openrisc_sim: Add automatic device tree generation Stafford Horne
2022-02-26 1:59 ` [PULL v2 6/6] hw/openrisc/openrisc_sim: Add support for initrd loading Stafford Horne
2022-02-28 16:46 ` [PULL v2 0/6] OpenRISC DTS Generation patches for 7.0 Peter Maydell
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20220226015924.1293022-2-shorne@gmail.com \
--to=shorne@gmail.com \
--cc=f4bug@amsat.org \
--cc=qemu-devel@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).