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[50.253.99.174]) by smtp.gmail.com with ESMTPSA id e23-20020a6b5017000000b00635b8032d45sm3138764iob.22.2022.02.26.09.07.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 26 Feb 2022 09:07:26 -0800 (PST) From: Warner Losh To: qemu-devel@nongnu.org Subject: [PATCH v2 14/16] bsd-user: introduce target.h Date: Sat, 26 Feb 2022 10:07:42 -0700 Message-Id: <20220226170744.76615-15-imp@bsdimp.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20220226170744.76615-1-imp@bsdimp.com> References: <20220226170744.76615-1-imp@bsdimp.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::d2d (failed) Received-SPF: none client-ip=2607:f8b0:4864:20::d2d; envelope-from=imp@bsdimp.com; helo=mail-io1-xd2d.google.com X-Spam_score_int: -4 X-Spam_score: -0.5 X-Spam_bar: / X-Spam_report: (-0.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , arrowd@FreeBSD.org, Kyle Evans , Richard Henderson , def@FreeBSD.org, jrtc27@FreeBSD.org, Warner Losh , Brad Smith Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Create target.h. This file is intended to be simple and describe basic things about the architecture. If something is a basic feature of the architecture, it belongs here. Should we need something that's per-BSD there will be a target-os.h that will live in the per-bsd directories. Define regpairs_aligned to reflect whether or not registers are 'paired' for 64-bit arguments or not. This will be false for all 64-bit targets, and will be true on those architectures that pair (currently just armv7 and powerpc on FreeBSD 14.x). Signed-off-by: Warner Losh Reviewed-by: Kyle Evans Reviewed-by: Richard Henderson --- bsd-user/arm/target.h | 21 +++++++++++++++++++++ bsd-user/i386/target.h | 21 +++++++++++++++++++++ bsd-user/qemu.h | 1 + bsd-user/x86_64/target.h | 21 +++++++++++++++++++++ 4 files changed, 64 insertions(+) create mode 100644 bsd-user/arm/target.h create mode 100644 bsd-user/i386/target.h create mode 100644 bsd-user/x86_64/target.h diff --git a/bsd-user/arm/target.h b/bsd-user/arm/target.h new file mode 100644 index 00000000000..419c039b68e --- /dev/null +++ b/bsd-user/arm/target.h @@ -0,0 +1,21 @@ +/* + * Intel general target stuff that's common to all i386 details + * + * Copyright (c) 2022 M. Warner Losh + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef TARGET_H +#define TARGET_H + +/* + * arm EABI 'lumps' the registers for 64-bit args. + */ +static inline bool regpairs_aligned(void *cpu_env) +{ + return true; +} + +#endif /* ! TARGET_H */ + diff --git a/bsd-user/i386/target.h b/bsd-user/i386/target.h new file mode 100644 index 00000000000..9b9df047a3b --- /dev/null +++ b/bsd-user/i386/target.h @@ -0,0 +1,21 @@ +/* + * Intel general target stuff that's common to all i386 details + * + * Copyright (c) 2022 M. Warner Losh + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef TARGET_ARCH_H +#define TARGET_ARCH_H + +/* + * i386 doesn't 'lump' the registers for 64-bit args. + */ +static inline bool regpairs_aligned(void *cpu_env) +{ + return false; +} + +#endif /* ! TARGET_ARCH_H */ + diff --git a/bsd-user/qemu.h b/bsd-user/qemu.h index 56042ddbc5d..a9efa807b78 100644 --- a/bsd-user/qemu.h +++ b/bsd-user/qemu.h @@ -35,6 +35,7 @@ extern char **environ; #include "target_syscall.h" #include "target_os_vmparam.h" #include "target_os_signal.h" +#include "target.h" #include "exec/gdbstub.h" /* diff --git a/bsd-user/x86_64/target.h b/bsd-user/x86_64/target.h new file mode 100644 index 00000000000..8956631db1d --- /dev/null +++ b/bsd-user/x86_64/target.h @@ -0,0 +1,21 @@ +/* + * Intel general target stuff that's common to all x86_64 details + * + * Copyright (c) 2022 M. Warner Losh + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef TARGET_H +#define TARGET_H + +/* + * x86 doesn't 'lump' the registers for 64-bit args, all args are 64 bits. + */ +static inline bool regpairs_aligned(void *cpu_env) +{ + return false; +} + +#endif /* ! TARGET_H */ + -- 2.33.1