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Mon, 28 Feb 2022 15:52:34 +0000 Received: from d06av21.portsmouth.uk.ibm.com (d06av21.portsmouth.uk.ibm.com [9.149.105.232]) by b06cxnps3075.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 21SFqWnJ47186184 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Mon, 28 Feb 2022 15:52:32 GMT Received: from d06av21.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 53FFC52050; Mon, 28 Feb 2022 15:52:32 +0000 (GMT) Received: from smtp.tlslab.ibm.com (unknown [9.101.4.1]) by d06av21.portsmouth.uk.ibm.com (Postfix) with SMTP id 12C185204F; Mon, 28 Feb 2022 15:52:32 +0000 (GMT) Received: from yukon.ibmuc.com (unknown [9.171.85.32]) by smtp.tlslab.ibm.com (Postfix) with ESMTP id 5EF292203EC; Mon, 28 Feb 2022 16:52:31 +0100 (CET) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-ppc@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v4 11/18] ppc/pnv: Add support for PQ offload on PHB5 Date: Mon, 28 Feb 2022 16:52:15 +0100 Message-Id: <20220228155222.643974-12-clg@kaod.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220228155222.643974-1-clg@kaod.org> References: <20220228155222.643974-1-clg@kaod.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: W5OZKe5nSLesl6lqo8XXFqbiMAV3xpuM X-Proofpoint-GUID: Wl1Egn1ISv_aWKMkepAEJswkji8pRtGs X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.816,Hydra:6.0.425,FMLib:17.11.64.514 definitions=2022-02-28_07,2022-02-26_01,2022-02-23_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1034 mlxscore=0 phishscore=0 adultscore=0 malwarescore=0 bulkscore=0 priorityscore=1501 mlxlogscore=913 suspectscore=0 spamscore=0 impostorscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2201110000 definitions=main-2202280083 Received-SPF: softfail client-ip=148.163.156.1; envelope-from=clg@kaod.org; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -11 X-Spam_score: -1.2 X-Spam_bar: - X-Spam_report: (-1.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_SOFTFAIL=0.665, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alexey Kardashevskiy , Frederic Barrat , Daniel Henrique Barboza , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" The PQ_disable configuration bit disables the check done on the PQ state bits when processing new MSI interrupts. When bit 9 is enabled, the PHB forwards any MSI trigger to the XIVE interrupt controller without checking the PQ state bits. The XIVE IC knows from the trigger message that the PQ bits have not been checked and performs the check locally. This configuration bit only applies to MSIs and LSIs are still checked on the PHB to handle the assertion level. PQ_disable enablement is a requirement for StoreEOI. Reviewed-by: Daniel Henrique Barboza Signed-off-by: C=C3=A9dric Le Goater --- include/hw/pci-host/pnv_phb4_regs.h | 1 + include/hw/ppc/xive.h | 1 + hw/intc/xive.c | 22 +++++++++++++++++++++- hw/pci-host/pnv_phb4.c | 9 +++++++++ 4 files changed, 32 insertions(+), 1 deletion(-) diff --git a/include/hw/pci-host/pnv_phb4_regs.h b/include/hw/pci-host/pn= v_phb4_regs.h index 55df2c3e5ece..64f326b7158e 100644 --- a/include/hw/pci-host/pnv_phb4_regs.h +++ b/include/hw/pci-host/pnv_phb4_regs.h @@ -225,6 +225,7 @@ /* Fundamental register set B */ #define PHB_VERSION 0x800 #define PHB_CTRLR 0x810 +#define PHB_CTRLR_IRQ_PQ_DISABLE PPC_BIT(9) /* P10 */ #define PHB_CTRLR_IRQ_PGSZ_64K PPC_BIT(11) #define PHB_CTRLR_IRQ_STORE_EOI PPC_BIT(12) #define PHB_CTRLR_MMIO_RD_STRICT PPC_BIT(13) diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h index 649b58a08f0c..126e4e2c3a17 100644 --- a/include/hw/ppc/xive.h +++ b/include/hw/ppc/xive.h @@ -176,6 +176,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(XiveSource, XIVE_SOURCE) */ #define XIVE_SRC_H_INT_ESB 0x1 /* ESB managed with hcall H_INT_ESB *= / #define XIVE_SRC_STORE_EOI 0x2 /* Store EOI supported */ +#define XIVE_SRC_PQ_DISABLE 0x4 /* Disable check on the PQ state bits= */ =20 struct XiveSource { DeviceState parent; diff --git a/hw/intc/xive.c b/hw/intc/xive.c index deb0db21e093..b8e4c7294d59 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -886,6 +886,16 @@ static bool xive_source_lsi_trigger(XiveSource *xsrc= , uint32_t srcno) } } =20 +/* + * Sources can be configured with PQ offloading in which case the check + * on the PQ state bits of MSIs is disabled + */ +static bool xive_source_esb_disabled(XiveSource *xsrc, uint32_t srcno) +{ + return (xsrc->esb_flags & XIVE_SRC_PQ_DISABLE) && + !xive_source_irq_is_lsi(xsrc, srcno); +} + /* * Returns whether the event notification should be forwarded. */ @@ -895,6 +905,10 @@ static bool xive_source_esb_trigger(XiveSource *xsrc= , uint32_t srcno) =20 assert(srcno < xsrc->nr_irqs); =20 + if (xive_source_esb_disabled(xsrc, srcno)) { + return true; + } + ret =3D xive_esb_trigger(&xsrc->status[srcno]); =20 if (xive_source_irq_is_lsi(xsrc, srcno) && @@ -915,6 +929,11 @@ static bool xive_source_esb_eoi(XiveSource *xsrc, ui= nt32_t srcno) =20 assert(srcno < xsrc->nr_irqs); =20 + if (xive_source_esb_disabled(xsrc, srcno)) { + qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid EOI for IRQ %d\n",= srcno); + return false; + } + ret =3D xive_esb_eoi(&xsrc->status[srcno]); =20 /* @@ -936,9 +955,10 @@ static bool xive_source_esb_eoi(XiveSource *xsrc, ui= nt32_t srcno) static void xive_source_notify(XiveSource *xsrc, int srcno) { XiveNotifierClass *xnc =3D XIVE_NOTIFIER_GET_CLASS(xsrc->xive); + bool pq_checked =3D !xive_source_esb_disabled(xsrc, srcno); =20 if (xnc->notify) { - xnc->notify(xsrc->xive, srcno, true); + xnc->notify(xsrc->xive, srcno, pq_checked); } } =20 diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c index 58498feace48..0b407ac69ba6 100644 --- a/hw/pci-host/pnv_phb4.c +++ b/hw/pci-host/pnv_phb4.c @@ -485,6 +485,15 @@ static void pnv_phb4_update_xsrc(PnvPHB4 *phb) flags =3D 0; } =20 + /* + * When the PQ disable configuration bit is set, the check on the + * PQ state bits is disabled on the PHB side (for MSI only) and it + * is performed on the IC side instead. + */ + if (phb->regs[PHB_CTRLR >> 3] & PHB_CTRLR_IRQ_PQ_DISABLE) { + flags |=3D XIVE_SRC_PQ_DISABLE; + } + phb->xsrc.esb_shift =3D shift; phb->xsrc.esb_flags =3D flags; =20 --=20 2.34.1