From: "Cédric Le Goater" <clg@kaod.org>
To: qemu-ppc@nongnu.org, qemu-devel@nongnu.org
Cc: "Alexey Kardashevskiy" <aik@ozlabs.ru>,
"Frederic Barrat" <fbarrat@linux.ibm.com>,
"Daniel Henrique Barboza" <danielhb413@gmail.com>,
"Cédric Le Goater" <clg@kaod.org>
Subject: [PATCH v4 05/18] ppc/pnv: Add POWER10 quads
Date: Mon, 28 Feb 2022 16:52:09 +0100 [thread overview]
Message-ID: <20220228155222.643974-6-clg@kaod.org> (raw)
In-Reply-To: <20220228155222.643974-1-clg@kaod.org>
and use a pnv_chip_power10_quad_realize() helper to avoid code
duplication with P9. This still needs some refinements on the XSCOM
registers handling in PnvQuad.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
include/hw/ppc/pnv.h | 3 +++
hw/ppc/pnv.c | 50 +++++++++++++++++++++++++++++++++++---------
2 files changed, 43 insertions(+), 10 deletions(-)
diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h
index 21e69b0fc187..6449fba39bfb 100644
--- a/include/hw/ppc/pnv.h
+++ b/include/hw/ppc/pnv.h
@@ -129,6 +129,9 @@ struct Pnv10Chip {
Pnv9Psi psi;
PnvLpcController lpc;
PnvOCC occ;
+
+ uint32_t nr_quads;
+ PnvQuad *quads;
};
#define PNV10_PIR2FUSEDCORE(pir) (((pir) >> 3) & 0xf)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 8394b786d89d..514019366c86 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -1388,6 +1388,21 @@ static void pnv_chip_power9_instance_init(Object *obj)
}
}
+static void pnv_chip_quad_realize_one(PnvChip *chip, PnvQuad *eq,
+ PnvCore *pnv_core)
+{
+ char eq_name[32];
+ int core_id = CPU_CORE(pnv_core)->core_id;
+
+ snprintf(eq_name, sizeof(eq_name), "eq[%d]", core_id);
+ object_initialize_child_with_props(OBJECT(chip), eq_name, eq,
+ sizeof(*eq), TYPE_PNV_QUAD,
+ &error_fatal, NULL);
+
+ object_property_set_int(OBJECT(eq), "quad-id", core_id, &error_fatal);
+ qdev_realize(DEVICE(eq), NULL, &error_fatal);
+}
+
static void pnv_chip_quad_realize(Pnv9Chip *chip9, Error **errp)
{
PnvChip *chip = PNV_CHIP(chip9);
@@ -1397,18 +1412,9 @@ static void pnv_chip_quad_realize(Pnv9Chip *chip9, Error **errp)
chip9->quads = g_new0(PnvQuad, chip9->nr_quads);
for (i = 0; i < chip9->nr_quads; i++) {
- char eq_name[32];
PnvQuad *eq = &chip9->quads[i];
- PnvCore *pnv_core = chip->cores[i * 4];
- int core_id = CPU_CORE(pnv_core)->core_id;
-
- snprintf(eq_name, sizeof(eq_name), "eq[%d]", core_id);
- object_initialize_child_with_props(OBJECT(chip), eq_name, eq,
- sizeof(*eq), TYPE_PNV_QUAD,
- &error_fatal, NULL);
- object_property_set_int(OBJECT(eq), "quad-id", core_id, &error_fatal);
- qdev_realize(DEVICE(eq), NULL, &error_fatal);
+ pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4]);
pnv_xscom_add_subregion(chip, PNV9_XSCOM_EQ_BASE(eq->quad_id),
&eq->xscom_regs);
@@ -1585,6 +1591,24 @@ static void pnv_chip_power10_instance_init(Object *obj)
object_initialize_child(obj, "occ", &chip10->occ, TYPE_PNV10_OCC);
}
+static void pnv_chip_power10_quad_realize(Pnv10Chip *chip10, Error **errp)
+{
+ PnvChip *chip = PNV_CHIP(chip10);
+ int i;
+
+ chip10->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4);
+ chip10->quads = g_new0(PnvQuad, chip10->nr_quads);
+
+ for (i = 0; i < chip10->nr_quads; i++) {
+ PnvQuad *eq = &chip10->quads[i];
+
+ pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4]);
+
+ pnv_xscom_add_subregion(chip, PNV10_XSCOM_EQ_BASE(eq->quad_id),
+ &eq->xscom_regs);
+ }
+}
+
static void pnv_chip_power10_realize(DeviceState *dev, Error **errp)
{
PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev);
@@ -1606,6 +1630,12 @@ static void pnv_chip_power10_realize(DeviceState *dev, Error **errp)
return;
}
+ pnv_chip_power10_quad_realize(chip10, &local_err);
+ if (local_err) {
+ error_propagate(errp, local_err);
+ return;
+ }
+
/* XIVE2 interrupt controller (POWER10) */
object_property_set_int(OBJECT(&chip10->xive), "ic-bar",
PNV10_XIVE2_IC_BASE(chip), &error_fatal);
--
2.34.1
next prev parent reply other threads:[~2022-02-28 15:54 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-02-28 15:52 [PATCH v4 00/18] ppc/pnv: Extend the powernv10 machin Cédric Le Goater
2022-02-28 15:52 ` [PATCH v4 01/18] ppc/xive2: Introduce a XIVE2 core framework Cédric Le Goater
2022-03-10 17:55 ` Thomas Huth
2022-03-11 7:38 ` Cédric Le Goater
2022-02-28 15:52 ` [PATCH v4 02/18] ppc/xive2: Introduce a presenter matching routine Cédric Le Goater
2022-02-28 15:52 ` [PATCH v4 03/18] ppc/pnv: Add a XIVE2 controller to the POWER10 chip Cédric Le Goater
2022-02-28 15:52 ` [PATCH v4 04/18] ppc/pnv: Add a OCC model for POWER10 Cédric Le Goater
2022-02-28 15:52 ` Cédric Le Goater [this message]
2022-02-28 15:52 ` [PATCH v4 06/18] ppc/pnv: Add model for POWER10 PHB5 PCIe Host bridge Cédric Le Goater
2022-02-28 17:26 ` Daniel Henrique Barboza
2022-02-28 15:52 ` [PATCH v4 07/18] ppc/pnv: Add a HOMER model to POWER10 Cédric Le Goater
2022-03-11 6:05 ` Alexey Kardashevskiy
2022-03-11 7:13 ` Cédric Le Goater
2022-02-28 15:52 ` [PATCH v4 08/18] ppc/psi: Add support for StoreEOI and 64k ESB pages (POWER10) Cédric Le Goater
2022-02-28 15:52 ` [PATCH v4 09/18] ppc/xive2: Add support for notification injection on ESB pages Cédric Le Goater
2022-02-28 15:52 ` [PATCH v4 10/18] ppc/xive: Add support for PQ state bits offload Cédric Le Goater
2022-02-28 15:52 ` [PATCH v4 11/18] ppc/pnv: Add support for PQ offload on PHB5 Cédric Le Goater
2022-02-28 15:52 ` [PATCH v4 12/18] ppc/pnv: Add support for PHB5 "Address-based trigger" mode Cédric Le Goater
2022-02-28 15:52 ` [PATCH v4 13/18] pnv/xive2: Introduce new capability bits Cédric Le Goater
2022-02-28 15:52 ` [PATCH v4 14/18] ppc/pnv: add XIVE Gen2 TIMA support Cédric Le Goater
2022-02-28 15:52 ` [PATCH v4 15/18] pnv/xive2: Add support XIVE2 P9-compat mode (or Gen1) Cédric Le Goater
2022-02-28 15:52 ` [PATCH v4 16/18] xive2: Add a get_config() handler for the router configuration Cédric Le Goater
2022-02-28 15:52 ` [PATCH v4 17/18] pnv/xive2: Add support for automatic save&restore Cédric Le Goater
2022-02-28 15:52 ` [PATCH v4 18/18] pnv/xive2: Add support for 8bits thread id Cédric Le Goater
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