* [PULL 01/87] hw/ppc/pnv: Determine ns16550's IRQ number from QOM property
2022-03-02 11:06 [PULL 00/87] ppc queue Cédric Le Goater
@ 2022-03-02 11:06 ` Cédric Le Goater
2022-03-02 11:06 ` [PULL 02/87] ppc/pnv: fix default PHB4 QOM hierarchy Cédric Le Goater
` (86 subsequent siblings)
87 siblings, 0 replies; 89+ messages in thread
From: Cédric Le Goater @ 2022-03-02 11:06 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Bernhard Beschow, Cédric Le Goater,
Philippe Mathieu-Daudé
From: Bernhard Beschow <shentey@gmail.com>
Determine the IRQ number in the same way as for pnv_dt_ipmi_bt(). This
resolves one usage of ISADevice::isairq[] which allows it to be removed
eventually.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20220301220037.76555-6-shentey@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/ppc/pnv.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 837146a2fbbe..441bf958cadb 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -380,9 +380,12 @@ static void pnv_dt_serial(ISADevice *d, void *fdt, int lpc_off)
cpu_to_be32(io_base),
cpu_to_be32(8)
};
+ uint32_t irq;
char *name;
int node;
+ irq = object_property_get_uint(OBJECT(d), "irq", &error_fatal);
+
name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base);
node = fdt_add_subnode(fdt, lpc_off, name);
_FDT(node);
@@ -394,7 +397,7 @@ static void pnv_dt_serial(ISADevice *d, void *fdt, int lpc_off)
_FDT((fdt_setprop_cell(fdt, node, "clock-frequency", 1843200)));
_FDT((fdt_setprop_cell(fdt, node, "current-speed", 115200)));
- _FDT((fdt_setprop_cell(fdt, node, "interrupts", d->isairq[0])));
+ _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq)));
_FDT((fdt_setprop_cell(fdt, node, "interrupt-parent",
fdt_get_phandle(fdt, lpc_off))));
--
2.34.1
^ permalink raw reply related [flat|nested] 89+ messages in thread* [PULL 02/87] ppc/pnv: fix default PHB4 QOM hierarchy
2022-03-02 11:06 [PULL 00/87] ppc queue Cédric Le Goater
2022-03-02 11:06 ` [PULL 01/87] hw/ppc/pnv: Determine ns16550's IRQ number from QOM property Cédric Le Goater
@ 2022-03-02 11:06 ` Cédric Le Goater
2022-03-02 11:06 ` [PULL 03/87] target/ppc: make power8-pmu.c CONFIG_TCG only Cédric Le Goater
` (85 subsequent siblings)
87 siblings, 0 replies; 89+ messages in thread
From: Cédric Le Goater @ 2022-03-02 11:06 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Daniel Henrique Barboza, Cédric Le Goater
From: Daniel Henrique Barboza <danielhb413@gmail.com>
Commit 3f4c369ea63e ("ppc/pnv: make PECs create and realize PHB4s")
changed phb4_pec code to create the default PHB4 objects in
pnv_pec_default_phb_realize(). In this process the stacks[] PEC array was
removed and each PHB4 object is tied together with its PEC via the
phb->pec pointer.
This change also broke the previous QOM hierarchy - the PHB4 objects are
being created and not being parented to their respective chips. This can
be verified by 'info pic' in a powernv9 domain with default settings.
pnv_chip_power9_pic_print_info() will fail to find the PHBs because
object_child_foreach_recursive() won't find any.
The solution is to set the parent chip and the parent bus, in the same
way done for user created PHB4 devices, for all PHB4 devices.
Fixes: 3f4c369ea63e ("ppc/pnv: make PECs create and realize PHB4s")
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20220218202804.413157-1-danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/pci-host/pnv_phb4.c | 36 ++++++++++++++++--------------------
1 file changed, 16 insertions(+), 20 deletions(-)
diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c
index e91249ef641d..846e7d0c3e24 100644
--- a/hw/pci-host/pnv_phb4.c
+++ b/hw/pci-host/pnv_phb4.c
@@ -1568,40 +1568,36 @@ static PnvPhb4PecState *pnv_phb4_get_pec(PnvChip *chip, PnvPHB4 *phb,
static void pnv_phb4_realize(DeviceState *dev, Error **errp)
{
PnvPHB4 *phb = PNV_PHB4(dev);
+ PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine());
+ PnvChip *chip = pnv_get_chip(pnv, phb->chip_id);
PCIHostState *pci = PCI_HOST_BRIDGE(dev);
XiveSource *xsrc = &phb->xsrc;
+ BusState *s;
Error *local_err = NULL;
int nr_irqs;
char name[32];
- /* User created PHB */
- if (!phb->pec) {
- PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine());
- PnvChip *chip = pnv_get_chip(pnv, phb->chip_id);
- BusState *s;
-
- if (!chip) {
- error_setg(errp, "invalid chip id: %d", phb->chip_id);
- return;
- }
+ if (!chip) {
+ error_setg(errp, "invalid chip id: %d", phb->chip_id);
+ return;
+ }
+ /* User created PHBs need to be assigned to a PEC */
+ if (!phb->pec) {
phb->pec = pnv_phb4_get_pec(chip, phb, &local_err);
if (local_err) {
error_propagate(errp, local_err);
return;
}
+ }
- /*
- * Reparent user created devices to the chip to build
- * correctly the device tree.
- */
- pnv_chip_parent_fixup(chip, OBJECT(phb), phb->phb_id);
+ /* Reparent the PHB to the chip to build the device tree */
+ pnv_chip_parent_fixup(chip, OBJECT(phb), phb->phb_id);
- s = qdev_get_parent_bus(DEVICE(chip));
- if (!qdev_set_parent_bus(DEVICE(phb), s, &local_err)) {
- error_propagate(errp, local_err);
- return;
- }
+ s = qdev_get_parent_bus(DEVICE(chip));
+ if (!qdev_set_parent_bus(DEVICE(phb), s, &local_err)) {
+ error_propagate(errp, local_err);
+ return;
}
/* Set the "big_phb" flag */
--
2.34.1
^ permalink raw reply related [flat|nested] 89+ messages in thread* [PULL 03/87] target/ppc: make power8-pmu.c CONFIG_TCG only
2022-03-02 11:06 [PULL 00/87] ppc queue Cédric Le Goater
2022-03-02 11:06 ` [PULL 01/87] hw/ppc/pnv: Determine ns16550's IRQ number from QOM property Cédric Le Goater
2022-03-02 11:06 ` [PULL 02/87] ppc/pnv: fix default PHB4 QOM hierarchy Cédric Le Goater
@ 2022-03-02 11:06 ` Cédric Le Goater
2022-03-02 11:06 ` [PULL 04/87] target/ppc: finalize pre-EBB PMU logic Cédric Le Goater
` (84 subsequent siblings)
87 siblings, 0 replies; 89+ messages in thread
From: Cédric Le Goater @ 2022-03-02 11:06 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Daniel Henrique Barboza, Richard Henderson,
Cédric Le Goater
From: Daniel Henrique Barboza <danielhb413@gmail.com>
This is an exclusive TCG helper. Gating it with CONFIG_TCG and changing
meson.build accordingly will prevent problems --disable-tcg and
--disable-linux-user later on.
We're also changing the uses of !kvm_enabled() to tcg_enabled() to avoid
adding "defined(CONFIG_TCG)" ifdefs, since tcg_enabled() will be
defaulted to false with --disable-tcg and the block will always be
skipped.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20220225101140.1054160-2-danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/power8-pmu.h | 4 ++--
target/ppc/cpu_init.c | 16 +++++++---------
target/ppc/machine.c | 6 +++++-
target/ppc/meson.build | 2 +-
4 files changed, 15 insertions(+), 13 deletions(-)
diff --git a/target/ppc/power8-pmu.h b/target/ppc/power8-pmu.h
index a8391995618a..256d90f523c9 100644
--- a/target/ppc/power8-pmu.h
+++ b/target/ppc/power8-pmu.h
@@ -13,11 +13,11 @@
#ifndef POWER8_PMU
#define POWER8_PMU
-void cpu_ppc_pmu_init(CPUPPCState *env);
-
#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
+void cpu_ppc_pmu_init(CPUPPCState *env);
void pmu_update_summaries(CPUPPCState *env);
#else
+static inline void cpu_ppc_pmu_init(CPUPPCState *env) { }
static inline void pmu_update_summaries(CPUPPCState *env) { }
#endif
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 61d36b11a093..544e0522902d 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -5698,12 +5698,10 @@ static void register_power9_mmu_sprs(CPUPPCState *env)
*/
static void init_tcg_pmu_power8(CPUPPCState *env)
{
-#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
/* Init PMU overflow timers */
- if (!kvm_enabled()) {
+ if (tcg_enabled()) {
cpu_ppc_pmu_init(env);
}
-#endif
}
static void init_proc_book3s_common(CPUPPCState *env)
@@ -7167,14 +7165,14 @@ static void ppc_cpu_reset(DeviceState *dev)
#if !defined(CONFIG_USER_ONLY)
env->nip = env->hreset_vector | env->excp_prefix;
-#if defined(CONFIG_TCG)
- if (env->mmu_model != POWERPC_MMU_REAL) {
- ppc_tlb_invalidate_all(env);
+
+ if (tcg_enabled()) {
+ if (env->mmu_model != POWERPC_MMU_REAL) {
+ ppc_tlb_invalidate_all(env);
+ }
+ pmu_update_summaries(env);
}
-#endif /* CONFIG_TCG */
#endif
-
- pmu_update_summaries(env);
hreg_compute_hflags(env);
env->reserve_addr = (target_ulong)-1ULL;
/* Be sure no exception or interrupt is pending */
diff --git a/target/ppc/machine.c b/target/ppc/machine.c
index 1b63146ed128..e67394459792 100644
--- a/target/ppc/machine.c
+++ b/target/ppc/machine.c
@@ -2,6 +2,7 @@
#include "cpu.h"
#include "exec/exec-all.h"
#include "sysemu/kvm.h"
+#include "sysemu/tcg.h"
#include "helper_regs.h"
#include "mmu-hash64.h"
#include "migration/cpu.h"
@@ -20,7 +21,10 @@ static void post_load_update_msr(CPUPPCState *env)
*/
env->msr ^= env->msr_mask & ~((1ULL << MSR_TGPR) | MSR_HVB);
ppc_store_msr(env, msr);
- pmu_update_summaries(env);
+
+ if (tcg_enabled()) {
+ pmu_update_summaries(env);
+ }
}
static int get_avr(QEMUFile *f, void *pv, size_t size,
diff --git a/target/ppc/meson.build b/target/ppc/meson.build
index a49a8911e069..79beaff14716 100644
--- a/target/ppc/meson.build
+++ b/target/ppc/meson.build
@@ -16,6 +16,7 @@ ppc_ss.add(when: 'CONFIG_TCG', if_true: files(
'misc_helper.c',
'timebase_helper.c',
'translate.c',
+ 'power8-pmu.c',
))
ppc_ss.add(libdecnumber)
@@ -51,7 +52,6 @@ ppc_softmmu_ss.add(when: 'TARGET_PPC64', if_true: files(
'mmu-book3s-v3.c',
'mmu-hash64.c',
'mmu-radix64.c',
- 'power8-pmu.c',
))
target_arch += {'ppc': ppc_ss}
--
2.34.1
^ permalink raw reply related [flat|nested] 89+ messages in thread* [PULL 04/87] target/ppc: finalize pre-EBB PMU logic
2022-03-02 11:06 [PULL 00/87] ppc queue Cédric Le Goater
` (2 preceding siblings ...)
2022-03-02 11:06 ` [PULL 03/87] target/ppc: make power8-pmu.c CONFIG_TCG only Cédric Le Goater
@ 2022-03-02 11:06 ` Cédric Le Goater
2022-03-02 11:06 ` [PULL 05/87] target/ppc: add PPC_INTERRUPT_EBB and EBB exceptions Cédric Le Goater
` (83 subsequent siblings)
87 siblings, 0 replies; 89+ messages in thread
From: Cédric Le Goater @ 2022-03-02 11:06 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Daniel Henrique Barboza, Cédric Le Goater
From: Daniel Henrique Barboza <danielhb413@gmail.com>
There are still PMU exclusive bits to handle in fire_PMC_interrupt()
before implementing the EBB support. Let's finalize it now to avoid
dealing with PMU and EBB logic at the same time in the next patches.
fire_PMC_interrupt() will fire an Performance Monitor alert depending on
MMCR0_PMAE. If we are required to freeze the timers (MMCR0_FCECE) we'll
also need to update summaries and delete the existing overflow timers.
In all cases we're going to update the cycle counters.
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20220225101140.1054160-3-danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/power8-pmu.c | 36 ++++++++++++++++++++++++++++++++++--
1 file changed, 34 insertions(+), 2 deletions(-)
diff --git a/target/ppc/power8-pmu.c b/target/ppc/power8-pmu.c
index 236e8e66e966..d24566315872 100644
--- a/target/ppc/power8-pmu.c
+++ b/target/ppc/power8-pmu.c
@@ -222,6 +222,20 @@ static void pmu_update_overflow_timers(CPUPPCState *env)
}
}
+static void pmu_delete_timers(CPUPPCState *env)
+{
+ QEMUTimer *pmc_overflow_timer;
+ int sprn;
+
+ for (sprn = SPR_POWER_PMC1; sprn <= SPR_POWER_PMC6; sprn++) {
+ pmc_overflow_timer = get_cyc_overflow_timer(env, sprn);
+
+ if (pmc_overflow_timer) {
+ timer_del(pmc_overflow_timer);
+ }
+ }
+}
+
void helper_store_mmcr0(CPUPPCState *env, target_ulong value)
{
bool hflags_pmcc0 = (value & MMCR0_PMCC0) != 0;
@@ -271,8 +285,26 @@ static void fire_PMC_interrupt(PowerPCCPU *cpu)
{
CPUPPCState *env = &cpu->env;
- if (!(env->spr[SPR_POWER_MMCR0] & MMCR0_EBE)) {
- return;
+ pmu_update_cycles(env);
+
+ if (env->spr[SPR_POWER_MMCR0] & MMCR0_FCECE) {
+ env->spr[SPR_POWER_MMCR0] &= ~MMCR0_FCECE;
+ env->spr[SPR_POWER_MMCR0] |= MMCR0_FC;
+
+ /* Changing MMCR0_FC requires a new HFLAGS_INSN_CNT calc */
+ pmu_update_summaries(env);
+
+ /*
+ * Delete all pending timers if we need to freeze
+ * the PMC. We'll restart them when the PMC starts
+ * running again.
+ */
+ pmu_delete_timers(env);
+ }
+
+ if (env->spr[SPR_POWER_MMCR0] & MMCR0_PMAE) {
+ env->spr[SPR_POWER_MMCR0] &= ~MMCR0_PMAE;
+ env->spr[SPR_POWER_MMCR0] |= MMCR0_PMAO;
}
/* PMC interrupt not implemented yet */
--
2.34.1
^ permalink raw reply related [flat|nested] 89+ messages in thread* [PULL 05/87] target/ppc: add PPC_INTERRUPT_EBB and EBB exceptions
2022-03-02 11:06 [PULL 00/87] ppc queue Cédric Le Goater
` (3 preceding siblings ...)
2022-03-02 11:06 ` [PULL 04/87] target/ppc: finalize pre-EBB PMU logic Cédric Le Goater
@ 2022-03-02 11:06 ` Cédric Le Goater
2022-03-02 11:06 ` [PULL 06/87] target/ppc: trigger PERFM EBBs from power8-pmu.c Cédric Le Goater
` (82 subsequent siblings)
87 siblings, 0 replies; 89+ messages in thread
From: Cédric Le Goater @ 2022-03-02 11:06 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Daniel Henrique Barboza, Cédric Le Goater
From: Daniel Henrique Barboza <danielhb413@gmail.com>
PPC_INTERRUPT_EBB is a new interrupt that will be used to deliver EBB
exceptions that had to be postponed because the thread wasn't in problem
state at the time the event-based branch was supposed to occur.
ISA 3.1 also defines two EBB exceptions: Performance Monitor EBB
exception and External EBB exception. They are being added as
POWERPC_EXCP_PERFM_EBB and POWERPC_EXCP_EXTERNAL_EBB.
PPC_INTERRUPT_EBB will check BESCR bits to see the EBB type that
occurred and trigger the appropriate exception. Both exceptions are
doing the same thing in this first implementation: clear BESCR_GE and
enter the branch with env->nip retrieved from SPR_EBBHR.
The checks being done by the interrupt code are msr_pr and BESCR_GE
states. All other checks (EBB facility check, BESCR_PME bit, specific
bits related to the event type) must be done beforehand.
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20220225101140.1054160-4-danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/cpu.h | 5 ++++-
target/ppc/cpu_init.c | 4 ++++
target/ppc/excp_helper.c | 33 +++++++++++++++++++++++++++++++++
3 files changed, 41 insertions(+), 1 deletion(-)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 5b01d409b31a..79375e8df489 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -127,8 +127,10 @@ enum {
/* ISA 3.00 additions */
POWERPC_EXCP_HVIRT = 101,
POWERPC_EXCP_SYSCALL_VECTORED = 102, /* scv exception */
+ POWERPC_EXCP_PERFM_EBB = 103, /* Performance Monitor EBB Exception */
+ POWERPC_EXCP_EXTERNAL_EBB = 104, /* External EBB Exception */
/* EOL */
- POWERPC_EXCP_NB = 103,
+ POWERPC_EXCP_NB = 105,
/* QEMU exceptions: special cases we want to stop translation */
POWERPC_EXCP_SYSCALL_USER = 0x203, /* System call in user mode only */
};
@@ -2434,6 +2436,7 @@ enum {
PPC_INTERRUPT_HMI, /* Hypervisor Maintenance interrupt */
PPC_INTERRUPT_HDOORBELL, /* Hypervisor Doorbell interrupt */
PPC_INTERRUPT_HVIRT, /* Hypervisor virtualization interrupt */
+ PPC_INTERRUPT_EBB, /* Event-based Branch exception */
};
/* Processor Compatibility mask (PCR) */
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 544e0522902d..073fd101687c 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -2060,6 +2060,10 @@ static void init_excp_POWER8(CPUPPCState *env)
env->excp_vectors[POWERPC_EXCP_FU] = 0x00000F60;
env->excp_vectors[POWERPC_EXCP_HV_FU] = 0x00000F80;
env->excp_vectors[POWERPC_EXCP_SDOOR_HV] = 0x00000E80;
+
+ /* Userland exceptions without vector value in PowerISA v3.1 */
+ env->excp_vectors[POWERPC_EXCP_PERFM_EBB] = 0x0;
+ env->excp_vectors[POWERPC_EXCP_EXTERNAL_EBB] = 0x0;
#endif
}
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 6538c56ab02b..5e7d29ae0081 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -1554,6 +1554,21 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int excp)
new_msr |= (target_ulong)MSR_HVB;
new_msr |= env->msr & ((target_ulong)1 << MSR_RI);
break;
+ case POWERPC_EXCP_PERFM_EBB: /* Performance Monitor EBB Exception */
+ case POWERPC_EXCP_EXTERNAL_EBB: /* External EBB Exception */
+ env->spr[SPR_BESCR] &= ~BESCR_GE;
+
+ /*
+ * Save NIP for rfebb insn in SPR_EBBRR. Next nip is
+ * stored in the EBB Handler SPR_EBBHR.
+ */
+ env->spr[SPR_EBBRR] = env->nip;
+ powerpc_set_excp_state(cpu, env->spr[SPR_EBBHR], env->msr);
+
+ /*
+ * This exception is handled in userspace. No need to proceed.
+ */
+ return;
case POWERPC_EXCP_THERM: /* Thermal interrupt */
case POWERPC_EXCP_PERFM: /* Embedded performance monitor interrupt */
case POWERPC_EXCP_VPUA: /* Vector assist exception */
@@ -1797,6 +1812,24 @@ static void ppc_hw_interrupt(CPUPPCState *env)
powerpc_excp(cpu, POWERPC_EXCP_THERM);
return;
}
+ /* EBB exception */
+ if (env->pending_interrupts & (1 << PPC_INTERRUPT_EBB)) {
+ /*
+ * EBB exception must be taken in problem state and
+ * with BESCR_GE set.
+ */
+ if (msr_pr == 1 && env->spr[SPR_BESCR] & BESCR_GE) {
+ env->pending_interrupts &= ~(1 << PPC_INTERRUPT_EBB);
+
+ if (env->spr[SPR_BESCR] & BESCR_PMEO) {
+ powerpc_excp(cpu, POWERPC_EXCP_PERFM_EBB);
+ } else if (env->spr[SPR_BESCR] & BESCR_EEO) {
+ powerpc_excp(cpu, POWERPC_EXCP_EXTERNAL_EBB);
+ }
+
+ return;
+ }
+ }
}
if (env->resume_as_sreset) {
--
2.34.1
^ permalink raw reply related [flat|nested] 89+ messages in thread* [PULL 06/87] target/ppc: trigger PERFM EBBs from power8-pmu.c
2022-03-02 11:06 [PULL 00/87] ppc queue Cédric Le Goater
` (4 preceding siblings ...)
2022-03-02 11:06 ` [PULL 05/87] target/ppc: add PPC_INTERRUPT_EBB and EBB exceptions Cédric Le Goater
@ 2022-03-02 11:06 ` Cédric Le Goater
2022-03-02 11:06 ` [PULL 07/87] target/ppc: Introduce TRANS*FLAGS macros Cédric Le Goater
` (81 subsequent siblings)
87 siblings, 0 replies; 89+ messages in thread
From: Cédric Le Goater @ 2022-03-02 11:06 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Daniel Henrique Barboza, Richard Henderson,
Cédric Le Goater
From: Daniel Henrique Barboza <danielhb413@gmail.com>
This patch adds the EBB exception support that are triggered by
Performance Monitor alerts. This happens when a Performance Monitor
alert occurs and MMCR0_EBE, BESCR_PME and BESCR_GE are set.
fire_PMC_interrupt() will execute the raise_ebb_perfm_exception() helper
which will check for MMCR0_EBE, BESCR_PME and BESCR_GE bits. If all bits
are set, do_ebb() will attempt to trigger a PERFM EBB event.
If the EBB facility is enabled in both FSCR and HFSCR we consider that
the EBB is valid and set BESCR_PMEO. After that, if we're running in
problem state, fire a POWERPC_EXCP_PERM_EBB immediately. Otherwise we'll
queue a PPC_INTERRUPT_EBB.
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220225101140.1054160-5-danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/cpu.h | 5 +++++
target/ppc/excp_helper.c | 48 ++++++++++++++++++++++++++++++++++++++++
target/ppc/power8-pmu.c | 3 +--
3 files changed, 54 insertions(+), 2 deletions(-)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 79375e8df489..1b687521c76c 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -2502,6 +2502,11 @@ void QEMU_NORETURN raise_exception_err(CPUPPCState *env, uint32_t exception,
void QEMU_NORETURN raise_exception_err_ra(CPUPPCState *env, uint32_t exception,
uint32_t error_code, uintptr_t raddr);
+/* PERFM EBB helper*/
+#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
+void raise_ebb_perfm_exception(CPUPPCState *env);
+#endif
+
#if !defined(CONFIG_USER_ONLY)
static inline int booke206_tlbm_id(CPUPPCState *env, ppcmas_tlb_t *tlbm)
{
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 5e7d29ae0081..d3e2cfcd7120 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -2066,6 +2066,54 @@ void helper_rfebb(CPUPPCState *env, target_ulong s)
env->spr[SPR_BESCR] &= ~BESCR_GE;
}
}
+
+/*
+ * Triggers or queues an 'ebb_excp' EBB exception. All checks
+ * but FSCR, HFSCR and msr_pr must be done beforehand.
+ *
+ * PowerISA v3.1 isn't clear about whether an EBB should be
+ * postponed or cancelled if the EBB facility is unavailable.
+ * Our assumption here is that the EBB is cancelled if both
+ * FSCR and HFSCR EBB facilities aren't available.
+ */
+static void do_ebb(CPUPPCState *env, int ebb_excp)
+{
+ PowerPCCPU *cpu = env_archcpu(env);
+ CPUState *cs = CPU(cpu);
+
+ /*
+ * FSCR_EBB and FSCR_IC_EBB are the same bits used with
+ * HFSCR.
+ */
+ helper_fscr_facility_check(env, FSCR_EBB, 0, FSCR_IC_EBB);
+ helper_hfscr_facility_check(env, FSCR_EBB, "EBB", FSCR_IC_EBB);
+
+ if (ebb_excp == POWERPC_EXCP_PERFM_EBB) {
+ env->spr[SPR_BESCR] |= BESCR_PMEO;
+ } else if (ebb_excp == POWERPC_EXCP_EXTERNAL_EBB) {
+ env->spr[SPR_BESCR] |= BESCR_EEO;
+ }
+
+ if (msr_pr == 1) {
+ powerpc_excp(cpu, ebb_excp);
+ } else {
+ env->pending_interrupts |= 1 << PPC_INTERRUPT_EBB;
+ cpu_interrupt(cs, CPU_INTERRUPT_HARD);
+ }
+}
+
+void raise_ebb_perfm_exception(CPUPPCState *env)
+{
+ bool perfm_ebb_enabled = env->spr[SPR_POWER_MMCR0] & MMCR0_EBE &&
+ env->spr[SPR_BESCR] & BESCR_PME &&
+ env->spr[SPR_BESCR] & BESCR_GE;
+
+ if (!perfm_ebb_enabled) {
+ return;
+ }
+
+ do_ebb(env, POWERPC_EXCP_PERFM_EBB);
+}
#endif
/*****************************************************************************/
diff --git a/target/ppc/power8-pmu.c b/target/ppc/power8-pmu.c
index d24566315872..beeab5c494e1 100644
--- a/target/ppc/power8-pmu.c
+++ b/target/ppc/power8-pmu.c
@@ -307,8 +307,7 @@ static void fire_PMC_interrupt(PowerPCCPU *cpu)
env->spr[SPR_POWER_MMCR0] |= MMCR0_PMAO;
}
- /* PMC interrupt not implemented yet */
- return;
+ raise_ebb_perfm_exception(env);
}
/* This helper assumes that the PMC is running. */
--
2.34.1
^ permalink raw reply related [flat|nested] 89+ messages in thread* [PULL 07/87] target/ppc: Introduce TRANS*FLAGS macros
2022-03-02 11:06 [PULL 00/87] ppc queue Cédric Le Goater
` (5 preceding siblings ...)
2022-03-02 11:06 ` [PULL 06/87] target/ppc: trigger PERFM EBBs from power8-pmu.c Cédric Le Goater
@ 2022-03-02 11:06 ` Cédric Le Goater
2022-03-02 11:06 ` [PULL 08/87] target/ppc: moved vector even and odd multiplication to decodetree Cédric Le Goater
` (80 subsequent siblings)
87 siblings, 0 replies; 89+ messages in thread
From: Cédric Le Goater @ 2022-03-02 11:06 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Luis Pires, Richard Henderson, Matheus Ferst,
Cédric Le Goater
From: Luis Pires <luis.pires@eldorado.org.br>
New macros that add FLAGS and FLAGS2 checking were added for
both TRANS and TRANS64.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Luis Pires <luis.pires@eldorado.org.br>
[ferst: - TRANS_FLAGS2 instead of TRANS_FLAGS_E
- Use the new macros in load/store vector insns ]
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20220225210936.1749575-2-matheus.ferst@eldorado.org.br>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/translate.c | 19 +++++++++++++++
target/ppc/translate/vsx-impl.c.inc | 37 ++++++++++-------------------
2 files changed, 31 insertions(+), 25 deletions(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index ecc5a104e049..b46a11386eee 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -6604,10 +6604,29 @@ static int times_16(DisasContext *ctx, int x)
#define TRANS(NAME, FUNC, ...) \
static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \
{ return FUNC(ctx, a, __VA_ARGS__); }
+#define TRANS_FLAGS(FLAGS, NAME, FUNC, ...) \
+ static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \
+ { \
+ REQUIRE_INSNS_FLAGS(ctx, FLAGS); \
+ return FUNC(ctx, a, __VA_ARGS__); \
+ }
+#define TRANS_FLAGS2(FLAGS2, NAME, FUNC, ...) \
+ static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \
+ { \
+ REQUIRE_INSNS_FLAGS2(ctx, FLAGS2); \
+ return FUNC(ctx, a, __VA_ARGS__); \
+ }
#define TRANS64(NAME, FUNC, ...) \
static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \
{ REQUIRE_64BIT(ctx); return FUNC(ctx, a, __VA_ARGS__); }
+#define TRANS64_FLAGS2(FLAGS2, NAME, FUNC, ...) \
+ static bool trans_##NAME(DisasContext *ctx, arg_##NAME *a) \
+ { \
+ REQUIRE_64BIT(ctx); \
+ REQUIRE_INSNS_FLAGS2(ctx, FLAGS2); \
+ return FUNC(ctx, a, __VA_ARGS__); \
+ }
/* TODO: More TRANS* helpers for extra insn_flags checks. */
diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx-impl.c.inc
index 128968b5e7a8..e8a4ba0cfa60 100644
--- a/target/ppc/translate/vsx-impl.c.inc
+++ b/target/ppc/translate/vsx-impl.c.inc
@@ -2072,12 +2072,6 @@ static bool do_lstxv(DisasContext *ctx, int ra, TCGv displ,
static bool do_lstxv_D(DisasContext *ctx, arg_D *a, bool store, bool paired)
{
- if (paired) {
- REQUIRE_INSNS_FLAGS2(ctx, ISA310);
- } else {
- REQUIRE_INSNS_FLAGS2(ctx, ISA300);
- }
-
if (paired || a->rt >= 32) {
REQUIRE_VSX(ctx);
} else {
@@ -2091,7 +2085,6 @@ static bool do_lstxv_PLS_D(DisasContext *ctx, arg_PLS_D *a,
bool store, bool paired)
{
arg_D d;
- REQUIRE_INSNS_FLAGS2(ctx, ISA310);
REQUIRE_VSX(ctx);
if (!resolve_PLS_D(ctx, &d, a)) {
@@ -2103,12 +2096,6 @@ static bool do_lstxv_PLS_D(DisasContext *ctx, arg_PLS_D *a,
static bool do_lstxv_X(DisasContext *ctx, arg_X *a, bool store, bool paired)
{
- if (paired) {
- REQUIRE_INSNS_FLAGS2(ctx, ISA310);
- } else {
- REQUIRE_INSNS_FLAGS2(ctx, ISA300);
- }
-
if (paired || a->rt >= 32) {
REQUIRE_VSX(ctx);
} else {
@@ -2118,18 +2105,18 @@ static bool do_lstxv_X(DisasContext *ctx, arg_X *a, bool store, bool paired)
return do_lstxv(ctx, a->ra, cpu_gpr[a->rb], a->rt, store, paired);
}
-TRANS(STXV, do_lstxv_D, true, false)
-TRANS(LXV, do_lstxv_D, false, false)
-TRANS(STXVP, do_lstxv_D, true, true)
-TRANS(LXVP, do_lstxv_D, false, true)
-TRANS(STXVX, do_lstxv_X, true, false)
-TRANS(LXVX, do_lstxv_X, false, false)
-TRANS(STXVPX, do_lstxv_X, true, true)
-TRANS(LXVPX, do_lstxv_X, false, true)
-TRANS64(PSTXV, do_lstxv_PLS_D, true, false)
-TRANS64(PLXV, do_lstxv_PLS_D, false, false)
-TRANS64(PSTXVP, do_lstxv_PLS_D, true, true)
-TRANS64(PLXVP, do_lstxv_PLS_D, false, true)
+TRANS_FLAGS2(ISA300, STXV, do_lstxv_D, true, false)
+TRANS_FLAGS2(ISA300, LXV, do_lstxv_D, false, false)
+TRANS_FLAGS2(ISA310, STXVP, do_lstxv_D, true, true)
+TRANS_FLAGS2(ISA310, LXVP, do_lstxv_D, false, true)
+TRANS_FLAGS2(ISA300, STXVX, do_lstxv_X, true, false)
+TRANS_FLAGS2(ISA300, LXVX, do_lstxv_X, false, false)
+TRANS_FLAGS2(ISA310, STXVPX, do_lstxv_X, true, true)
+TRANS_FLAGS2(ISA310, LXVPX, do_lstxv_X, false, true)
+TRANS64_FLAGS2(ISA310, PSTXV, do_lstxv_PLS_D, true, false)
+TRANS64_FLAGS2(ISA310, PLXV, do_lstxv_PLS_D, false, false)
+TRANS64_FLAGS2(ISA310, PSTXVP, do_lstxv_PLS_D, true, true)
+TRANS64_FLAGS2(ISA310, PLXVP, do_lstxv_PLS_D, false, true)
static void gen_xxblendv_vec(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b,
TCGv_vec c)
--
2.34.1
^ permalink raw reply related [flat|nested] 89+ messages in thread* [PULL 08/87] target/ppc: moved vector even and odd multiplication to decodetree
2022-03-02 11:06 [PULL 00/87] ppc queue Cédric Le Goater
` (6 preceding siblings ...)
2022-03-02 11:06 ` [PULL 07/87] target/ppc: Introduce TRANS*FLAGS macros Cédric Le Goater
@ 2022-03-02 11:06 ` Cédric Le Goater
2022-03-02 11:06 ` [PULL 09/87] target/ppc: Moved vector multiply high and low " Cédric Le Goater
` (79 subsequent siblings)
87 siblings, 0 replies; 89+ messages in thread
From: Cédric Le Goater @ 2022-03-02 11:06 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Lucas Mateus Castro (alqotel), Richard Henderson,
Lucas Mateus Castro, Cédric Le Goater, Matheus Ferst
From: "Lucas Mateus Castro (alqotel)" <lucas.castro@eldorado.org.br>
Moved the instructions vmulesb, vmulosb, vmuleub, vmuloub,
vmulesh, vmulosh, vmuleuh, vmulouh, vmulesw, vmulosw,
muleuw and vmulouw from legacy to decodetree. Implemented
the instructions vmulesd, vmulosd, vmuleud, vmuloud.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20220225210936.1749575-3-matheus.ferst@eldorado.org.br>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/helper.h | 24 ++++-----
target/ppc/insn32.decode | 22 +++++++++
target/ppc/int_helper.c | 20 ++++----
target/ppc/translate/vmx-impl.c.inc | 77 ++++++++++++++++++++++-------
target/ppc/translate/vmx-ops.c.inc | 15 ++----
tcg/ppc/tcg-target.c.inc | 6 +++
6 files changed, 112 insertions(+), 52 deletions(-)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index ae7d503fcf2f..c399fab1a830 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -192,18 +192,18 @@ DEF_HELPER_3(vmrglw, void, avr, avr, avr)
DEF_HELPER_3(vmrghb, void, avr, avr, avr)
DEF_HELPER_3(vmrghh, void, avr, avr, avr)
DEF_HELPER_3(vmrghw, void, avr, avr, avr)
-DEF_HELPER_3(vmulesb, void, avr, avr, avr)
-DEF_HELPER_3(vmulesh, void, avr, avr, avr)
-DEF_HELPER_3(vmulesw, void, avr, avr, avr)
-DEF_HELPER_3(vmuleub, void, avr, avr, avr)
-DEF_HELPER_3(vmuleuh, void, avr, avr, avr)
-DEF_HELPER_3(vmuleuw, void, avr, avr, avr)
-DEF_HELPER_3(vmulosb, void, avr, avr, avr)
-DEF_HELPER_3(vmulosh, void, avr, avr, avr)
-DEF_HELPER_3(vmulosw, void, avr, avr, avr)
-DEF_HELPER_3(vmuloub, void, avr, avr, avr)
-DEF_HELPER_3(vmulouh, void, avr, avr, avr)
-DEF_HELPER_3(vmulouw, void, avr, avr, avr)
+DEF_HELPER_FLAGS_3(VMULESB, TCG_CALL_NO_RWG, void, avr, avr, avr)
+DEF_HELPER_FLAGS_3(VMULESH, TCG_CALL_NO_RWG, void, avr, avr, avr)
+DEF_HELPER_FLAGS_3(VMULESW, TCG_CALL_NO_RWG, void, avr, avr, avr)
+DEF_HELPER_FLAGS_3(VMULEUB, TCG_CALL_NO_RWG, void, avr, avr, avr)
+DEF_HELPER_FLAGS_3(VMULEUH, TCG_CALL_NO_RWG, void, avr, avr, avr)
+DEF_HELPER_FLAGS_3(VMULEUW, TCG_CALL_NO_RWG, void, avr, avr, avr)
+DEF_HELPER_FLAGS_3(VMULOSB, TCG_CALL_NO_RWG, void, avr, avr, avr)
+DEF_HELPER_FLAGS_3(VMULOSH, TCG_CALL_NO_RWG, void, avr, avr, avr)
+DEF_HELPER_FLAGS_3(VMULOSW, TCG_CALL_NO_RWG, void, avr, avr, avr)
+DEF_HELPER_FLAGS_3(VMULOUB, TCG_CALL_NO_RWG, void, avr, avr, avr)
+DEF_HELPER_FLAGS_3(VMULOUH, TCG_CALL_NO_RWG, void, avr, avr, avr)
+DEF_HELPER_FLAGS_3(VMULOUW, TCG_CALL_NO_RWG, void, avr, avr, avr)
DEF_HELPER_3(vmulhsw, void, avr, avr, avr)
DEF_HELPER_3(vmulhuw, void, avr, avr, avr)
DEF_HELPER_3(vmulhsd, void, avr, avr, avr)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 2a9c91a4235e..092ea796184c 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -440,6 +440,28 @@ VEXTRACTWM 000100 ..... 01010 ..... 11001000010 @VX_tb
VEXTRACTDM 000100 ..... 01011 ..... 11001000010 @VX_tb
VEXTRACTQM 000100 ..... 01100 ..... 11001000010 @VX_tb
+## Vector Multiply Instruction
+
+VMULESB 000100 ..... ..... ..... 01100001000 @VX
+VMULOSB 000100 ..... ..... ..... 00100001000 @VX
+VMULEUB 000100 ..... ..... ..... 01000001000 @VX
+VMULOUB 000100 ..... ..... ..... 00000001000 @VX
+
+VMULESH 000100 ..... ..... ..... 01101001000 @VX
+VMULOSH 000100 ..... ..... ..... 00101001000 @VX
+VMULEUH 000100 ..... ..... ..... 01001001000 @VX
+VMULOUH 000100 ..... ..... ..... 00001001000 @VX
+
+VMULESW 000100 ..... ..... ..... 01110001000 @VX
+VMULOSW 000100 ..... ..... ..... 00110001000 @VX
+VMULEUW 000100 ..... ..... ..... 01010001000 @VX
+VMULOUW 000100 ..... ..... ..... 00010001000 @VX
+
+VMULESD 000100 ..... ..... ..... 01111001000 @VX
+VMULOSD 000100 ..... ..... ..... 00111001000 @VX
+VMULEUD 000100 ..... ..... ..... 01011001000 @VX
+VMULOUD 000100 ..... ..... ..... 00011001000 @VX
+
# VSX Load/Store Instructions
LXV 111101 ..... ..... ............ . 001 @DQ_TSX
diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
index d1b12788b215..c9f34ce3ca4e 100644
--- a/target/ppc/int_helper.c
+++ b/target/ppc/int_helper.c
@@ -1063,7 +1063,7 @@ void helper_vmsumuhs(CPUPPCState *env, ppc_avr_t *r, ppc_avr_t *a,
}
#define VMUL_DO_EVN(name, mul_element, mul_access, prod_access, cast) \
- void helper_v##name(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
+ void helper_V##name(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
{ \
int i; \
\
@@ -1074,7 +1074,7 @@ void helper_vmsumuhs(CPUPPCState *env, ppc_avr_t *r, ppc_avr_t *a,
}
#define VMUL_DO_ODD(name, mul_element, mul_access, prod_access, cast) \
- void helper_v##name(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
+ void helper_V##name(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
{ \
int i; \
\
@@ -1085,14 +1085,14 @@ void helper_vmsumuhs(CPUPPCState *env, ppc_avr_t *r, ppc_avr_t *a,
}
#define VMUL(suffix, mul_element, mul_access, prod_access, cast) \
- VMUL_DO_EVN(mule##suffix, mul_element, mul_access, prod_access, cast) \
- VMUL_DO_ODD(mulo##suffix, mul_element, mul_access, prod_access, cast)
-VMUL(sb, s8, VsrSB, VsrSH, int16_t)
-VMUL(sh, s16, VsrSH, VsrSW, int32_t)
-VMUL(sw, s32, VsrSW, VsrSD, int64_t)
-VMUL(ub, u8, VsrB, VsrH, uint16_t)
-VMUL(uh, u16, VsrH, VsrW, uint32_t)
-VMUL(uw, u32, VsrW, VsrD, uint64_t)
+ VMUL_DO_EVN(MULE##suffix, mul_element, mul_access, prod_access, cast) \
+ VMUL_DO_ODD(MULO##suffix, mul_element, mul_access, prod_access, cast)
+VMUL(SB, s8, VsrSB, VsrSH, int16_t)
+VMUL(SH, s16, VsrSH, VsrSW, int32_t)
+VMUL(SW, s32, VsrSW, VsrSD, int64_t)
+VMUL(UB, u8, VsrB, VsrH, uint16_t)
+VMUL(UH, u16, VsrH, VsrW, uint32_t)
+VMUL(UW, u32, VsrW, VsrD, uint64_t)
#undef VMUL_DO_EVN
#undef VMUL_DO_ODD
#undef VMUL
diff --git a/target/ppc/translate/vmx-impl.c.inc b/target/ppc/translate/vmx-impl.c.inc
index d5e02fd7f22e..a34a080e8324 100644
--- a/target/ppc/translate/vmx-impl.c.inc
+++ b/target/ppc/translate/vmx-impl.c.inc
@@ -798,29 +798,11 @@ static void trans_vclzd(DisasContext *ctx)
tcg_temp_free_i64(avr);
}
-GEN_VXFORM(vmuloub, 4, 0);
-GEN_VXFORM(vmulouh, 4, 1);
-GEN_VXFORM(vmulouw, 4, 2);
GEN_VXFORM_V(vmuluwm, MO_32, tcg_gen_gvec_mul, 4, 2);
-GEN_VXFORM_DUAL(vmulouw, PPC_ALTIVEC, PPC_NONE,
- vmuluwm, PPC_NONE, PPC2_ALTIVEC_207)
-GEN_VXFORM(vmulosb, 4, 4);
-GEN_VXFORM(vmulosh, 4, 5);
-GEN_VXFORM(vmulosw, 4, 6);
GEN_VXFORM_V(vmulld, MO_64, tcg_gen_gvec_mul, 4, 7);
-GEN_VXFORM(vmuleub, 4, 8);
-GEN_VXFORM(vmuleuh, 4, 9);
-GEN_VXFORM(vmuleuw, 4, 10);
GEN_VXFORM(vmulhuw, 4, 10);
GEN_VXFORM(vmulhud, 4, 11);
-GEN_VXFORM_DUAL(vmuleuw, PPC_ALTIVEC, PPC_NONE,
- vmulhuw, PPC_NONE, PPC2_ISA310);
-GEN_VXFORM(vmulesb, 4, 12);
-GEN_VXFORM(vmulesh, 4, 13);
-GEN_VXFORM(vmulesw, 4, 14);
GEN_VXFORM(vmulhsw, 4, 14);
-GEN_VXFORM_DUAL(vmulesw, PPC_ALTIVEC, PPC_NONE,
- vmulhsw, PPC_NONE, PPC2_ISA310);
GEN_VXFORM(vmulhsd, 4, 15);
GEN_VXFORM_V(vslb, MO_8, tcg_gen_gvec_shlv, 2, 4);
GEN_VXFORM_V(vslh, MO_16, tcg_gen_gvec_shlv, 2, 5);
@@ -2104,6 +2086,65 @@ static bool trans_VPEXTD(DisasContext *ctx, arg_VX *a)
return true;
}
+static bool do_vx_helper(DisasContext *ctx, arg_VX *a,
+ void (*gen_helper)(TCGv_ptr, TCGv_ptr, TCGv_ptr))
+{
+ TCGv_ptr ra, rb, rd;
+ REQUIRE_VECTOR(ctx);
+
+ ra = gen_avr_ptr(a->vra);
+ rb = gen_avr_ptr(a->vrb);
+ rd = gen_avr_ptr(a->vrt);
+ gen_helper(rd, ra, rb);
+ tcg_temp_free_ptr(ra);
+ tcg_temp_free_ptr(rb);
+ tcg_temp_free_ptr(rd);
+
+ return true;
+}
+
+static bool do_vx_vmuleo(DisasContext *ctx, arg_VX *a, bool even,
+ void (*gen_mul)(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_i64))
+{
+ TCGv_i64 vra, vrb, vrt0, vrt1;
+ REQUIRE_VECTOR(ctx);
+
+ vra = tcg_temp_new_i64();
+ vrb = tcg_temp_new_i64();
+ vrt0 = tcg_temp_new_i64();
+ vrt1 = tcg_temp_new_i64();
+
+ get_avr64(vra, a->vra, even);
+ get_avr64(vrb, a->vrb, even);
+ gen_mul(vrt0, vrt1, vra, vrb);
+ set_avr64(a->vrt, vrt0, false);
+ set_avr64(a->vrt, vrt1, true);
+
+ tcg_temp_free_i64(vra);
+ tcg_temp_free_i64(vrb);
+ tcg_temp_free_i64(vrt0);
+ tcg_temp_free_i64(vrt1);
+
+ return true;
+}
+
+TRANS_FLAGS2(ALTIVEC_207, VMULESB, do_vx_helper, gen_helper_VMULESB)
+TRANS_FLAGS2(ALTIVEC_207, VMULOSB, do_vx_helper, gen_helper_VMULOSB)
+TRANS_FLAGS2(ALTIVEC_207, VMULEUB, do_vx_helper, gen_helper_VMULEUB)
+TRANS_FLAGS2(ALTIVEC_207, VMULOUB, do_vx_helper, gen_helper_VMULOUB)
+TRANS_FLAGS2(ALTIVEC_207, VMULESH, do_vx_helper, gen_helper_VMULESH)
+TRANS_FLAGS2(ALTIVEC_207, VMULOSH, do_vx_helper, gen_helper_VMULOSH)
+TRANS_FLAGS2(ALTIVEC_207, VMULEUH, do_vx_helper, gen_helper_VMULEUH)
+TRANS_FLAGS2(ALTIVEC_207, VMULOUH, do_vx_helper, gen_helper_VMULOUH)
+TRANS_FLAGS2(ALTIVEC_207, VMULESW, do_vx_helper, gen_helper_VMULESW)
+TRANS_FLAGS2(ALTIVEC_207, VMULOSW, do_vx_helper, gen_helper_VMULOSW)
+TRANS_FLAGS2(ALTIVEC_207, VMULEUW, do_vx_helper, gen_helper_VMULEUW)
+TRANS_FLAGS2(ALTIVEC_207, VMULOUW, do_vx_helper, gen_helper_VMULOUW)
+TRANS_FLAGS2(ISA310, VMULESD, do_vx_vmuleo, true , tcg_gen_muls2_i64)
+TRANS_FLAGS2(ISA310, VMULOSD, do_vx_vmuleo, false, tcg_gen_muls2_i64)
+TRANS_FLAGS2(ISA310, VMULEUD, do_vx_vmuleo, true , tcg_gen_mulu2_i64)
+TRANS_FLAGS2(ISA310, VMULOUD, do_vx_vmuleo, false, tcg_gen_mulu2_i64)
+
#undef GEN_VR_LDX
#undef GEN_VR_STX
#undef GEN_VR_LVE
diff --git a/target/ppc/translate/vmx-ops.c.inc b/target/ppc/translate/vmx-ops.c.inc
index 25ee715b4326..f310b2fbde95 100644
--- a/target/ppc/translate/vmx-ops.c.inc
+++ b/target/ppc/translate/vmx-ops.c.inc
@@ -101,20 +101,11 @@ GEN_VXFORM_DUAL(vmrgow, vextuwlx, 6, 26, PPC_NONE, PPC2_ALTIVEC_207),
GEN_VXFORM_300(vextubrx, 6, 28),
GEN_VXFORM_300(vextuhrx, 6, 29),
GEN_VXFORM_DUAL(vmrgew, vextuwrx, 6, 30, PPC_NONE, PPC2_ALTIVEC_207),
-GEN_VXFORM(vmuloub, 4, 0),
-GEN_VXFORM(vmulouh, 4, 1),
-GEN_VXFORM_DUAL(vmulouw, vmuluwm, 4, 2, PPC_ALTIVEC, PPC_NONE),
-GEN_VXFORM(vmulosb, 4, 4),
-GEN_VXFORM(vmulosh, 4, 5),
-GEN_VXFORM_207(vmulosw, 4, 6),
+GEN_VXFORM_207(vmuluwm, 4, 2),
GEN_VXFORM_310(vmulld, 4, 7),
-GEN_VXFORM(vmuleub, 4, 8),
-GEN_VXFORM(vmuleuh, 4, 9),
-GEN_VXFORM_DUAL(vmuleuw, vmulhuw, 4, 10, PPC_ALTIVEC, PPC_NONE),
+GEN_VXFORM_310(vmulhuw, 4, 10),
GEN_VXFORM_310(vmulhud, 4, 11),
-GEN_VXFORM(vmulesb, 4, 12),
-GEN_VXFORM(vmulesh, 4, 13),
-GEN_VXFORM_DUAL(vmulesw, vmulhsw, 4, 14, PPC_ALTIVEC, PPC_NONE),
+GEN_VXFORM_310(vmulhsw, 4, 14),
GEN_VXFORM_310(vmulhsd, 4, 15),
GEN_VXFORM(vslb, 2, 4),
GEN_VXFORM(vslh, 2, 5),
diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
index dea24f23c4db..69d22e08cbf2 100644
--- a/tcg/ppc/tcg-target.c.inc
+++ b/tcg/ppc/tcg-target.c.inc
@@ -3987,3 +3987,9 @@ void tcg_register_jit(const void *buf, size_t buf_size)
tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame));
}
#endif /* __ELF__ */
+#undef VMULEUB
+#undef VMULEUH
+#undef VMULEUW
+#undef VMULOUB
+#undef VMULOUH
+#undef VMULOUW
--
2.34.1
^ permalink raw reply related [flat|nested] 89+ messages in thread* [PULL 09/87] target/ppc: Moved vector multiply high and low to decodetree
2022-03-02 11:06 [PULL 00/87] ppc queue Cédric Le Goater
` (7 preceding siblings ...)
2022-03-02 11:06 ` [PULL 08/87] target/ppc: moved vector even and odd multiplication to decodetree Cédric Le Goater
@ 2022-03-02 11:06 ` Cédric Le Goater
2022-03-02 11:06 ` [PULL 10/87] target/ppc: vmulh* instructions without helpers Cédric Le Goater
` (78 subsequent siblings)
87 siblings, 0 replies; 89+ messages in thread
From: Cédric Le Goater @ 2022-03-02 11:06 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Lucas Mateus Castro (alqotel), Richard Henderson,
Lucas Mateus Castro, Cédric Le Goater, Matheus Ferst
From: "Lucas Mateus Castro (alqotel)" <lucas.castro@eldorado.org.br>
Moved instructions vmulld, vmulhuw, vmulhsw, vmulhud and vmulhsd to
decodetree
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20220225210936.1749575-4-matheus.ferst@eldorado.org.br>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/helper.h | 8 ++++----
target/ppc/insn32.decode | 6 ++++++
target/ppc/int_helper.c | 8 ++++----
target/ppc/translate/vmx-impl.c.inc | 21 ++++++++++++++++-----
target/ppc/translate/vmx-ops.c.inc | 5 -----
5 files changed, 30 insertions(+), 18 deletions(-)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index c399fab1a830..43c7a0263c6c 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -204,10 +204,10 @@ DEF_HELPER_FLAGS_3(VMULOSW, TCG_CALL_NO_RWG, void, avr, avr, avr)
DEF_HELPER_FLAGS_3(VMULOUB, TCG_CALL_NO_RWG, void, avr, avr, avr)
DEF_HELPER_FLAGS_3(VMULOUH, TCG_CALL_NO_RWG, void, avr, avr, avr)
DEF_HELPER_FLAGS_3(VMULOUW, TCG_CALL_NO_RWG, void, avr, avr, avr)
-DEF_HELPER_3(vmulhsw, void, avr, avr, avr)
-DEF_HELPER_3(vmulhuw, void, avr, avr, avr)
-DEF_HELPER_3(vmulhsd, void, avr, avr, avr)
-DEF_HELPER_3(vmulhud, void, avr, avr, avr)
+DEF_HELPER_FLAGS_3(VMULHSW, TCG_CALL_NO_RWG, void, avr, avr, avr)
+DEF_HELPER_FLAGS_3(VMULHUW, TCG_CALL_NO_RWG, void, avr, avr, avr)
+DEF_HELPER_FLAGS_3(VMULHSD, TCG_CALL_NO_RWG, void, avr, avr, avr)
+DEF_HELPER_FLAGS_3(VMULHUD, TCG_CALL_NO_RWG, void, avr, avr, avr)
DEF_HELPER_3(vslo, void, avr, avr, avr)
DEF_HELPER_3(vsro, void, avr, avr, avr)
DEF_HELPER_3(vsrv, void, avr, avr, avr)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 092ea796184c..d817e44c7104 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -462,6 +462,12 @@ VMULOSD 000100 ..... ..... ..... 00111001000 @VX
VMULEUD 000100 ..... ..... ..... 01011001000 @VX
VMULOUD 000100 ..... ..... ..... 00011001000 @VX
+VMULHSW 000100 ..... ..... ..... 01110001001 @VX
+VMULHUW 000100 ..... ..... ..... 01010001001 @VX
+VMULHSD 000100 ..... ..... ..... 01111001001 @VX
+VMULHUD 000100 ..... ..... ..... 01011001001 @VX
+VMULLD 000100 ..... ..... ..... 00111001001 @VX
+
# VSX Load/Store Instructions
LXV 111101 ..... ..... ............ . 001 @DQ_TSX
diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
index c9f34ce3ca4e..873f957bf4ea 100644
--- a/target/ppc/int_helper.c
+++ b/target/ppc/int_helper.c
@@ -1097,7 +1097,7 @@ VMUL(UW, u32, VsrW, VsrD, uint64_t)
#undef VMUL_DO_ODD
#undef VMUL
-void helper_vmulhsw(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
+void helper_VMULHSW(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
{
int i;
@@ -1106,7 +1106,7 @@ void helper_vmulhsw(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
}
}
-void helper_vmulhuw(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
+void helper_VMULHUW(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
{
int i;
@@ -1116,7 +1116,7 @@ void helper_vmulhuw(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
}
}
-void helper_vmulhsd(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
+void helper_VMULHSD(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
{
uint64_t discard;
@@ -1124,7 +1124,7 @@ void helper_vmulhsd(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
muls64(&discard, &r->u64[1], a->s64[1], b->s64[1]);
}
-void helper_vmulhud(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
+void helper_VMULHUD(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
{
uint64_t discard;
diff --git a/target/ppc/translate/vmx-impl.c.inc b/target/ppc/translate/vmx-impl.c.inc
index a34a080e8324..d493de3629e5 100644
--- a/target/ppc/translate/vmx-impl.c.inc
+++ b/target/ppc/translate/vmx-impl.c.inc
@@ -799,11 +799,6 @@ static void trans_vclzd(DisasContext *ctx)
}
GEN_VXFORM_V(vmuluwm, MO_32, tcg_gen_gvec_mul, 4, 2);
-GEN_VXFORM_V(vmulld, MO_64, tcg_gen_gvec_mul, 4, 7);
-GEN_VXFORM(vmulhuw, 4, 10);
-GEN_VXFORM(vmulhud, 4, 11);
-GEN_VXFORM(vmulhsw, 4, 14);
-GEN_VXFORM(vmulhsd, 4, 15);
GEN_VXFORM_V(vslb, MO_8, tcg_gen_gvec_shlv, 2, 4);
GEN_VXFORM_V(vslh, MO_16, tcg_gen_gvec_shlv, 2, 5);
GEN_VXFORM_V(vslw, MO_32, tcg_gen_gvec_shlv, 2, 6);
@@ -2128,6 +2123,17 @@ static bool do_vx_vmuleo(DisasContext *ctx, arg_VX *a, bool even,
return true;
}
+static bool trans_VMULLD(DisasContext *ctx, arg_VX *a)
+{
+ REQUIRE_INSNS_FLAGS2(ctx, ISA310);
+ REQUIRE_VECTOR(ctx);
+
+ tcg_gen_gvec_mul(MO_64, avr_full_offset(a->vrt), avr_full_offset(a->vra),
+ avr_full_offset(a->vrb), 16, 16);
+
+ return true;
+}
+
TRANS_FLAGS2(ALTIVEC_207, VMULESB, do_vx_helper, gen_helper_VMULESB)
TRANS_FLAGS2(ALTIVEC_207, VMULOSB, do_vx_helper, gen_helper_VMULOSB)
TRANS_FLAGS2(ALTIVEC_207, VMULEUB, do_vx_helper, gen_helper_VMULEUB)
@@ -2145,6 +2151,11 @@ TRANS_FLAGS2(ISA310, VMULOSD, do_vx_vmuleo, false, tcg_gen_muls2_i64)
TRANS_FLAGS2(ISA310, VMULEUD, do_vx_vmuleo, true , tcg_gen_mulu2_i64)
TRANS_FLAGS2(ISA310, VMULOUD, do_vx_vmuleo, false, tcg_gen_mulu2_i64)
+TRANS_FLAGS2(ISA310, VMULHSW, do_vx_helper, gen_helper_VMULHSW)
+TRANS_FLAGS2(ISA310, VMULHSD, do_vx_helper, gen_helper_VMULHSD)
+TRANS_FLAGS2(ISA310, VMULHUW, do_vx_helper, gen_helper_VMULHUW)
+TRANS_FLAGS2(ISA310, VMULHUD, do_vx_helper, gen_helper_VMULHUD)
+
#undef GEN_VR_LDX
#undef GEN_VR_STX
#undef GEN_VR_LVE
diff --git a/target/ppc/translate/vmx-ops.c.inc b/target/ppc/translate/vmx-ops.c.inc
index f310b2fbde95..914e68e5b0be 100644
--- a/target/ppc/translate/vmx-ops.c.inc
+++ b/target/ppc/translate/vmx-ops.c.inc
@@ -102,11 +102,6 @@ GEN_VXFORM_300(vextubrx, 6, 28),
GEN_VXFORM_300(vextuhrx, 6, 29),
GEN_VXFORM_DUAL(vmrgew, vextuwrx, 6, 30, PPC_NONE, PPC2_ALTIVEC_207),
GEN_VXFORM_207(vmuluwm, 4, 2),
-GEN_VXFORM_310(vmulld, 4, 7),
-GEN_VXFORM_310(vmulhuw, 4, 10),
-GEN_VXFORM_310(vmulhud, 4, 11),
-GEN_VXFORM_310(vmulhsw, 4, 14),
-GEN_VXFORM_310(vmulhsd, 4, 15),
GEN_VXFORM(vslb, 2, 4),
GEN_VXFORM(vslh, 2, 5),
GEN_VXFORM_DUAL(vslw, vrlwnm, 2, 6, PPC_ALTIVEC, PPC_NONE),
--
2.34.1
^ permalink raw reply related [flat|nested] 89+ messages in thread* [PULL 10/87] target/ppc: vmulh* instructions without helpers
2022-03-02 11:06 [PULL 00/87] ppc queue Cédric Le Goater
` (8 preceding siblings ...)
2022-03-02 11:06 ` [PULL 09/87] target/ppc: Moved vector multiply high and low " Cédric Le Goater
@ 2022-03-02 11:06 ` Cédric Le Goater
2022-03-02 11:06 ` [PULL 11/87] target/ppc: Implement vmsumcud instruction Cédric Le Goater
` (77 subsequent siblings)
87 siblings, 0 replies; 89+ messages in thread
From: Cédric Le Goater @ 2022-03-02 11:06 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Lucas Mateus Castro (alqotel), Richard Henderson,
Lucas Mateus Castro, Cédric Le Goater, Matheus Ferst
From: "Lucas Mateus Castro (alqotel)" <lucas.castro@eldorado.org.br>
Changed vmulhuw, vmulhud, vmulhsw, vmulhsd to not
use helpers.
Signed-off-by: Lucas Mateus Castro (alqotel) <lucas.araujo@eldorado.org.br>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220225210936.1749575-5-matheus.ferst@eldorado.org.br>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/helper.h | 4 --
target/ppc/int_helper.c | 35 -----------
target/ppc/translate/vmx-impl.c.inc | 91 +++++++++++++++++++++++++++--
3 files changed, 87 insertions(+), 43 deletions(-)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 43c7a0263c6c..0fdf2e8a75a4 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -204,10 +204,6 @@ DEF_HELPER_FLAGS_3(VMULOSW, TCG_CALL_NO_RWG, void, avr, avr, avr)
DEF_HELPER_FLAGS_3(VMULOUB, TCG_CALL_NO_RWG, void, avr, avr, avr)
DEF_HELPER_FLAGS_3(VMULOUH, TCG_CALL_NO_RWG, void, avr, avr, avr)
DEF_HELPER_FLAGS_3(VMULOUW, TCG_CALL_NO_RWG, void, avr, avr, avr)
-DEF_HELPER_FLAGS_3(VMULHSW, TCG_CALL_NO_RWG, void, avr, avr, avr)
-DEF_HELPER_FLAGS_3(VMULHUW, TCG_CALL_NO_RWG, void, avr, avr, avr)
-DEF_HELPER_FLAGS_3(VMULHSD, TCG_CALL_NO_RWG, void, avr, avr, avr)
-DEF_HELPER_FLAGS_3(VMULHUD, TCG_CALL_NO_RWG, void, avr, avr, avr)
DEF_HELPER_3(vslo, void, avr, avr, avr)
DEF_HELPER_3(vsro, void, avr, avr, avr)
DEF_HELPER_3(vsrv, void, avr, avr, avr)
diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
index 873f957bf4ea..46ef3ffb3f62 100644
--- a/target/ppc/int_helper.c
+++ b/target/ppc/int_helper.c
@@ -1097,41 +1097,6 @@ VMUL(UW, u32, VsrW, VsrD, uint64_t)
#undef VMUL_DO_ODD
#undef VMUL
-void helper_VMULHSW(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
-{
- int i;
-
- for (i = 0; i < 4; i++) {
- r->s32[i] = (int32_t)(((int64_t)a->s32[i] * (int64_t)b->s32[i]) >> 32);
- }
-}
-
-void helper_VMULHUW(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
-{
- int i;
-
- for (i = 0; i < 4; i++) {
- r->u32[i] = (uint32_t)(((uint64_t)a->u32[i] *
- (uint64_t)b->u32[i]) >> 32);
- }
-}
-
-void helper_VMULHSD(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
-{
- uint64_t discard;
-
- muls64(&discard, &r->u64[0], a->s64[0], b->s64[0]);
- muls64(&discard, &r->u64[1], a->s64[1], b->s64[1]);
-}
-
-void helper_VMULHUD(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
-{
- uint64_t discard;
-
- mulu64(&discard, &r->u64[0], a->u64[0], b->u64[0]);
- mulu64(&discard, &r->u64[1], a->u64[1], b->u64[1]);
-}
-
void helper_vperm(CPUPPCState *env, ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b,
ppc_avr_t *c)
{
diff --git a/target/ppc/translate/vmx-impl.c.inc b/target/ppc/translate/vmx-impl.c.inc
index d493de3629e5..97a075efd1ef 100644
--- a/target/ppc/translate/vmx-impl.c.inc
+++ b/target/ppc/translate/vmx-impl.c.inc
@@ -2151,10 +2151,93 @@ TRANS_FLAGS2(ISA310, VMULOSD, do_vx_vmuleo, false, tcg_gen_muls2_i64)
TRANS_FLAGS2(ISA310, VMULEUD, do_vx_vmuleo, true , tcg_gen_mulu2_i64)
TRANS_FLAGS2(ISA310, VMULOUD, do_vx_vmuleo, false, tcg_gen_mulu2_i64)
-TRANS_FLAGS2(ISA310, VMULHSW, do_vx_helper, gen_helper_VMULHSW)
-TRANS_FLAGS2(ISA310, VMULHSD, do_vx_helper, gen_helper_VMULHSD)
-TRANS_FLAGS2(ISA310, VMULHUW, do_vx_helper, gen_helper_VMULHUW)
-TRANS_FLAGS2(ISA310, VMULHUD, do_vx_helper, gen_helper_VMULHUD)
+static void do_vx_vmulhw_i64(TCGv_i64 t, TCGv_i64 a, TCGv_i64 b, bool sign)
+{
+ TCGv_i64 hh, lh, temp;
+
+ uint64_t c;
+ hh = tcg_temp_new_i64();
+ lh = tcg_temp_new_i64();
+ temp = tcg_temp_new_i64();
+
+ c = 0xFFFFFFFF;
+
+ if (sign) {
+ tcg_gen_ext32s_i64(lh, a);
+ tcg_gen_ext32s_i64(temp, b);
+ } else {
+ tcg_gen_andi_i64(lh, a, c);
+ tcg_gen_andi_i64(temp, b, c);
+ }
+ tcg_gen_mul_i64(lh, lh, temp);
+
+ if (sign) {
+ tcg_gen_sari_i64(hh, a, 32);
+ tcg_gen_sari_i64(temp, b, 32);
+ } else {
+ tcg_gen_shri_i64(hh, a, 32);
+ tcg_gen_shri_i64(temp, b, 32);
+ }
+ tcg_gen_mul_i64(hh, hh, temp);
+
+ tcg_gen_shri_i64(lh, lh, 32);
+ tcg_gen_andi_i64(hh, hh, c << 32);
+ tcg_gen_or_i64(t, hh, lh);
+
+ tcg_temp_free_i64(hh);
+ tcg_temp_free_i64(lh);
+ tcg_temp_free_i64(temp);
+}
+
+static void do_vx_vmulhd_i64(TCGv_i64 t, TCGv_i64 a, TCGv_i64 b, bool sign)
+{
+ TCGv_i64 tlow;
+
+ tlow = tcg_temp_new_i64();
+ if (sign) {
+ tcg_gen_muls2_i64(tlow, t, a, b);
+ } else {
+ tcg_gen_mulu2_i64(tlow, t, a, b);
+ }
+
+ tcg_temp_free_i64(tlow);
+}
+
+static bool do_vx_mulh(DisasContext *ctx, arg_VX *a, bool sign,
+ void (*func)(TCGv_i64, TCGv_i64, TCGv_i64, bool))
+{
+ REQUIRE_INSNS_FLAGS2(ctx, ISA310);
+ REQUIRE_VECTOR(ctx);
+
+ TCGv_i64 vra, vrb, vrt;
+ int i;
+
+ vra = tcg_temp_new_i64();
+ vrb = tcg_temp_new_i64();
+ vrt = tcg_temp_new_i64();
+
+ for (i = 0; i < 2; i++) {
+ get_avr64(vra, a->vra, i);
+ get_avr64(vrb, a->vrb, i);
+ get_avr64(vrt, a->vrt, i);
+
+ func(vrt, vra, vrb, sign);
+
+ set_avr64(a->vrt, vrt, i);
+ }
+
+ tcg_temp_free_i64(vra);
+ tcg_temp_free_i64(vrb);
+ tcg_temp_free_i64(vrt);
+
+ return true;
+
+}
+
+TRANS(VMULHSW, do_vx_mulh, true , do_vx_vmulhw_i64)
+TRANS(VMULHSD, do_vx_mulh, true , do_vx_vmulhd_i64)
+TRANS(VMULHUW, do_vx_mulh, false, do_vx_vmulhw_i64)
+TRANS(VMULHUD, do_vx_mulh, false, do_vx_vmulhd_i64)
#undef GEN_VR_LDX
#undef GEN_VR_STX
--
2.34.1
^ permalink raw reply related [flat|nested] 89+ messages in thread* [PULL 11/87] target/ppc: Implement vmsumcud instruction
2022-03-02 11:06 [PULL 00/87] ppc queue Cédric Le Goater
` (9 preceding siblings ...)
2022-03-02 11:06 ` [PULL 10/87] target/ppc: vmulh* instructions without helpers Cédric Le Goater
@ 2022-03-02 11:06 ` Cédric Le Goater
2022-03-02 11:06 ` [PULL 12/87] target/ppc: Implement vmsumudm instruction Cédric Le Goater
` (76 subsequent siblings)
87 siblings, 0 replies; 89+ messages in thread
From: Cédric Le Goater @ 2022-03-02 11:06 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Víctor Colombo, Peter Maydell, Richard Henderson,
Matheus Ferst, Cédric Le Goater
From: Víctor Colombo <victor.colombo@eldorado.org.br>
Based on [1] by Lijun Pan <ljp@linux.ibm.com>, which was never merged
into master.
[1]: https://lists.gnu.org/archive/html/qemu-ppc/2020-07/msg00419.html
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20220225210936.1749575-6-matheus.ferst@eldorado.org.br>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/insn32.decode | 4 +++
target/ppc/translate/vmx-impl.c.inc | 53 +++++++++++++++++++++++++++++
2 files changed, 57 insertions(+)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index d817e44c7104..e85a75db2ff7 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -468,6 +468,10 @@ VMULHSD 000100 ..... ..... ..... 01111001001 @VX
VMULHUD 000100 ..... ..... ..... 01011001001 @VX
VMULLD 000100 ..... ..... ..... 00111001001 @VX
+## Vector Multiply-Sum Instructions
+
+VMSUMCUD 000100 ..... ..... ..... ..... 010111 @VA
+
# VSX Load/Store Instructions
LXV 111101 ..... ..... ............ . 001 @DQ_TSX
diff --git a/target/ppc/translate/vmx-impl.c.inc b/target/ppc/translate/vmx-impl.c.inc
index 97a075efd1ef..4f528dc82018 100644
--- a/target/ppc/translate/vmx-impl.c.inc
+++ b/target/ppc/translate/vmx-impl.c.inc
@@ -2081,6 +2081,59 @@ static bool trans_VPEXTD(DisasContext *ctx, arg_VX *a)
return true;
}
+static bool trans_VMSUMCUD(DisasContext *ctx, arg_VA *a)
+{
+ TCGv_i64 tmp0, tmp1, prod1h, prod1l, prod0h, prod0l, zero;
+
+ REQUIRE_INSNS_FLAGS2(ctx, ISA310);
+ REQUIRE_VECTOR(ctx);
+
+ tmp0 = tcg_temp_new_i64();
+ tmp1 = tcg_temp_new_i64();
+ prod1h = tcg_temp_new_i64();
+ prod1l = tcg_temp_new_i64();
+ prod0h = tcg_temp_new_i64();
+ prod0l = tcg_temp_new_i64();
+ zero = tcg_constant_i64(0);
+
+ /* prod1 = vsr[vra+32].dw[1] * vsr[vrb+32].dw[1] */
+ get_avr64(tmp0, a->vra, false);
+ get_avr64(tmp1, a->vrb, false);
+ tcg_gen_mulu2_i64(prod1l, prod1h, tmp0, tmp1);
+
+ /* prod0 = vsr[vra+32].dw[0] * vsr[vrb+32].dw[0] */
+ get_avr64(tmp0, a->vra, true);
+ get_avr64(tmp1, a->vrb, true);
+ tcg_gen_mulu2_i64(prod0l, prod0h, tmp0, tmp1);
+
+ /* Sum lower 64-bits elements */
+ get_avr64(tmp1, a->rc, false);
+ tcg_gen_add2_i64(tmp1, tmp0, tmp1, zero, prod1l, zero);
+ tcg_gen_add2_i64(tmp1, tmp0, tmp1, tmp0, prod0l, zero);
+
+ /*
+ * Discard lower 64-bits, leaving the carry into bit 64.
+ * Then sum the higher 64-bit elements.
+ */
+ get_avr64(tmp1, a->rc, true);
+ tcg_gen_add2_i64(tmp1, tmp0, tmp0, zero, tmp1, zero);
+ tcg_gen_add2_i64(tmp1, tmp0, tmp1, tmp0, prod1h, zero);
+ tcg_gen_add2_i64(tmp1, tmp0, tmp1, tmp0, prod0h, zero);
+
+ /* Discard 64 more bits to complete the CHOP128(temp >> 128) */
+ set_avr64(a->vrt, tmp0, false);
+ set_avr64(a->vrt, zero, true);
+
+ tcg_temp_free_i64(tmp0);
+ tcg_temp_free_i64(tmp1);
+ tcg_temp_free_i64(prod1h);
+ tcg_temp_free_i64(prod1l);
+ tcg_temp_free_i64(prod0h);
+ tcg_temp_free_i64(prod0l);
+
+ return true;
+}
+
static bool do_vx_helper(DisasContext *ctx, arg_VX *a,
void (*gen_helper)(TCGv_ptr, TCGv_ptr, TCGv_ptr))
{
--
2.34.1
^ permalink raw reply related [flat|nested] 89+ messages in thread* [PULL 12/87] target/ppc: Implement vmsumudm instruction
2022-03-02 11:06 [PULL 00/87] ppc queue Cédric Le Goater
` (10 preceding siblings ...)
2022-03-02 11:06 ` [PULL 11/87] target/ppc: Implement vmsumcud instruction Cédric Le Goater
@ 2022-03-02 11:06 ` Cédric Le Goater
2022-03-02 11:06 ` [PULL 13/87] target/ppc: Move vexts[bhw]2[wd] to decodetree Cédric Le Goater
` (75 subsequent siblings)
87 siblings, 0 replies; 89+ messages in thread
From: Cédric Le Goater @ 2022-03-02 11:06 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Víctor Colombo, Peter Maydell, Richard Henderson,
Matheus Ferst, Cédric Le Goater
From: Víctor Colombo <victor.colombo@eldorado.org.br>
Based on [1] by Lijun Pan <ljp@linux.ibm.com>, which was never merged
into master.
[1]: https://lists.gnu.org/archive/html/qemu-ppc/2020-07/msg00419.html
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20220225210936.1749575-7-matheus.ferst@eldorado.org.br>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/insn32.decode | 1 +
target/ppc/translate/vmx-impl.c.inc | 34 +++++++++++++++++++++++++++++
2 files changed, 35 insertions(+)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index e85a75db2ff7..732a2bb79ed4 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -471,6 +471,7 @@ VMULLD 000100 ..... ..... ..... 00111001001 @VX
## Vector Multiply-Sum Instructions
VMSUMCUD 000100 ..... ..... ..... ..... 010111 @VA
+VMSUMUDM 000100 ..... ..... ..... ..... 100011 @VA
# VSX Load/Store Instructions
diff --git a/target/ppc/translate/vmx-impl.c.inc b/target/ppc/translate/vmx-impl.c.inc
index 4f528dc82018..fcff3418c5c8 100644
--- a/target/ppc/translate/vmx-impl.c.inc
+++ b/target/ppc/translate/vmx-impl.c.inc
@@ -2081,6 +2081,40 @@ static bool trans_VPEXTD(DisasContext *ctx, arg_VX *a)
return true;
}
+static bool trans_VMSUMUDM(DisasContext *ctx, arg_VA *a)
+{
+ TCGv_i64 rl, rh, src1, src2;
+ int dw;
+
+ REQUIRE_INSNS_FLAGS2(ctx, ISA300);
+ REQUIRE_VECTOR(ctx);
+
+ rh = tcg_temp_new_i64();
+ rl = tcg_temp_new_i64();
+ src1 = tcg_temp_new_i64();
+ src2 = tcg_temp_new_i64();
+
+ get_avr64(rl, a->rc, false);
+ get_avr64(rh, a->rc, true);
+
+ for (dw = 0; dw < 2; dw++) {
+ get_avr64(src1, a->vra, dw);
+ get_avr64(src2, a->vrb, dw);
+ tcg_gen_mulu2_i64(src1, src2, src1, src2);
+ tcg_gen_add2_i64(rl, rh, rl, rh, src1, src2);
+ }
+
+ set_avr64(a->vrt, rl, false);
+ set_avr64(a->vrt, rh, true);
+
+ tcg_temp_free_i64(rl);
+ tcg_temp_free_i64(rh);
+ tcg_temp_free_i64(src1);
+ tcg_temp_free_i64(src2);
+
+ return true;
+}
+
static bool trans_VMSUMCUD(DisasContext *ctx, arg_VA *a)
{
TCGv_i64 tmp0, tmp1, prod1h, prod1l, prod0h, prod0l, zero;
--
2.34.1
^ permalink raw reply related [flat|nested] 89+ messages in thread* [PULL 13/87] target/ppc: Move vexts[bhw]2[wd] to decodetree
2022-03-02 11:06 [PULL 00/87] ppc queue Cédric Le Goater
` (11 preceding siblings ...)
2022-03-02 11:06 ` [PULL 12/87] target/ppc: Implement vmsumudm instruction Cédric Le Goater
@ 2022-03-02 11:06 ` Cédric Le Goater
2022-03-02 11:06 ` [PULL 14/87] target/ppc: Implement vextsd2q Cédric Le Goater
` (74 subsequent siblings)
87 siblings, 0 replies; 89+ messages in thread
From: Cédric Le Goater @ 2022-03-02 11:06 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Cédric Le Goater, Richard Henderson,
Lucas Coutinho, Matheus Ferst
From: Lucas Coutinho <lucas.coutinho@eldorado.org.br>
Move the following instructions to decodetree:
vextsb2w: Vector Extend Sign Byte To Word
vextsh2w: Vector Extend Sign Halfword To Word
vextsb2d: Vector Extend Sign Byte To Doubleword
vextsh2d: Vector Extend Sign Halfword To Doubleword
vextsw2d: Vector Extend Sign Word To Doubleword
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Lucas Coutinho <lucas.coutinho@eldorado.org.br>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20220225210936.1749575-8-matheus.ferst@eldorado.org.br>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/helper.h | 5 ---
target/ppc/insn32.decode | 8 ++++
target/ppc/int_helper.c | 15 --------
target/ppc/translate/vmx-impl.c.inc | 58 ++++++++++++++++++++++++++---
target/ppc/translate/vmx-ops.c.inc | 5 ---
5 files changed, 61 insertions(+), 30 deletions(-)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 0fdf2e8a75a4..5e64c8371d6e 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -242,11 +242,6 @@ DEF_HELPER_4(VINSBLX, void, env, avr, i64, tl)
DEF_HELPER_4(VINSHLX, void, env, avr, i64, tl)
DEF_HELPER_4(VINSWLX, void, env, avr, i64, tl)
DEF_HELPER_4(VINSDLX, void, env, avr, i64, tl)
-DEF_HELPER_2(vextsb2w, void, avr, avr)
-DEF_HELPER_2(vextsh2w, void, avr, avr)
-DEF_HELPER_2(vextsb2d, void, avr, avr)
-DEF_HELPER_2(vextsh2d, void, avr, avr)
-DEF_HELPER_2(vextsw2d, void, avr, avr)
DEF_HELPER_2(vnegw, void, avr, avr)
DEF_HELPER_2(vnegd, void, avr, avr)
DEF_HELPER_2(vupkhpx, void, avr, avr)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 732a2bb79ed4..1dcf9c61e9c7 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -419,6 +419,14 @@ VINSWVRX 000100 ..... ..... ..... 00110001111 @VX
VSLDBI 000100 ..... ..... ..... 00 ... 010110 @VN
VSRDBI 000100 ..... ..... ..... 01 ... 010110 @VN
+## Vector Integer Arithmetic Instructions
+
+VEXTSB2W 000100 ..... 10000 ..... 11000000010 @VX_tb
+VEXTSH2W 000100 ..... 10001 ..... 11000000010 @VX_tb
+VEXTSB2D 000100 ..... 11000 ..... 11000000010 @VX_tb
+VEXTSH2D 000100 ..... 11001 ..... 11000000010 @VX_tb
+VEXTSW2D 000100 ..... 11010 ..... 11000000010 @VX_tb
+
## Vector Mask Manipulation Instructions
MTVSRBM 000100 ..... 10000 ..... 11001000010 @VX_tb
diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
index 46ef3ffb3f62..a75a5482fcc6 100644
--- a/target/ppc/int_helper.c
+++ b/target/ppc/int_helper.c
@@ -1630,21 +1630,6 @@ XXBLEND(W, 32)
XXBLEND(D, 64)
#undef XXBLEND
-#define VEXT_SIGNED(name, element, cast) \
-void helper_##name(ppc_avr_t *r, ppc_avr_t *b) \
-{ \
- int i; \
- for (i = 0; i < ARRAY_SIZE(r->element); i++) { \
- r->element[i] = (cast)b->element[i]; \
- } \
-}
-VEXT_SIGNED(vextsb2w, s32, int8_t)
-VEXT_SIGNED(vextsb2d, s64, int8_t)
-VEXT_SIGNED(vextsh2w, s32, int16_t)
-VEXT_SIGNED(vextsh2d, s64, int16_t)
-VEXT_SIGNED(vextsw2d, s64, int32_t)
-#undef VEXT_SIGNED
-
#define VNEG(name, element) \
void helper_##name(ppc_avr_t *r, ppc_avr_t *b) \
{ \
diff --git a/target/ppc/translate/vmx-impl.c.inc b/target/ppc/translate/vmx-impl.c.inc
index fcff3418c5c8..aa021bdf542d 100644
--- a/target/ppc/translate/vmx-impl.c.inc
+++ b/target/ppc/translate/vmx-impl.c.inc
@@ -1772,11 +1772,59 @@ GEN_VXFORM_TRANS(vclzw, 1, 30)
GEN_VXFORM_TRANS(vclzd, 1, 31)
GEN_VXFORM_NOA_2(vnegw, 1, 24, 6)
GEN_VXFORM_NOA_2(vnegd, 1, 24, 7)
-GEN_VXFORM_NOA_2(vextsb2w, 1, 24, 16)
-GEN_VXFORM_NOA_2(vextsh2w, 1, 24, 17)
-GEN_VXFORM_NOA_2(vextsb2d, 1, 24, 24)
-GEN_VXFORM_NOA_2(vextsh2d, 1, 24, 25)
-GEN_VXFORM_NOA_2(vextsw2d, 1, 24, 26)
+
+static void gen_vexts_i64(TCGv_i64 t, TCGv_i64 b, int64_t s)
+{
+ tcg_gen_sextract_i64(t, b, 0, 64 - s);
+}
+
+static void gen_vexts_i32(TCGv_i32 t, TCGv_i32 b, int32_t s)
+{
+ tcg_gen_sextract_i32(t, b, 0, 32 - s);
+}
+
+static void gen_vexts_vec(unsigned vece, TCGv_vec t, TCGv_vec b, int64_t s)
+{
+ tcg_gen_shli_vec(vece, t, b, s);
+ tcg_gen_sari_vec(vece, t, t, s);
+}
+
+static bool do_vexts(DisasContext *ctx, arg_VX_tb *a, unsigned vece, int64_t s)
+{
+ static const TCGOpcode vecop_list[] = {
+ INDEX_op_shli_vec, INDEX_op_sari_vec, 0
+ };
+
+ static const GVecGen2i op[2] = {
+ {
+ .fni4 = gen_vexts_i32,
+ .fniv = gen_vexts_vec,
+ .opt_opc = vecop_list,
+ .vece = MO_32
+ },
+ {
+ .fni8 = gen_vexts_i64,
+ .fniv = gen_vexts_vec,
+ .opt_opc = vecop_list,
+ .vece = MO_64
+ },
+ };
+
+ REQUIRE_INSNS_FLAGS2(ctx, ISA300);
+ REQUIRE_VECTOR(ctx);
+
+ tcg_gen_gvec_2i(avr_full_offset(a->vrt), avr_full_offset(a->vrb),
+ 16, 16, s, &op[vece - MO_32]);
+
+ return true;
+}
+
+TRANS(VEXTSB2W, do_vexts, MO_32, 24);
+TRANS(VEXTSH2W, do_vexts, MO_32, 16);
+TRANS(VEXTSB2D, do_vexts, MO_64, 56);
+TRANS(VEXTSH2D, do_vexts, MO_64, 48);
+TRANS(VEXTSW2D, do_vexts, MO_64, 32);
+
GEN_VXFORM_NOA_2(vctzb, 1, 24, 28)
GEN_VXFORM_NOA_2(vctzh, 1, 24, 29)
GEN_VXFORM_NOA_2(vctzw, 1, 24, 30)
diff --git a/target/ppc/translate/vmx-ops.c.inc b/target/ppc/translate/vmx-ops.c.inc
index 914e68e5b0be..6787327f56ad 100644
--- a/target/ppc/translate/vmx-ops.c.inc
+++ b/target/ppc/translate/vmx-ops.c.inc
@@ -216,11 +216,6 @@ GEN_VXFORM(vspltish, 6, 13),
GEN_VXFORM(vspltisw, 6, 14),
GEN_VXFORM_300_EO(vnegw, 0x01, 0x18, 0x06),
GEN_VXFORM_300_EO(vnegd, 0x01, 0x18, 0x07),
-GEN_VXFORM_300_EO(vextsb2w, 0x01, 0x18, 0x10),
-GEN_VXFORM_300_EO(vextsh2w, 0x01, 0x18, 0x11),
-GEN_VXFORM_300_EO(vextsb2d, 0x01, 0x18, 0x18),
-GEN_VXFORM_300_EO(vextsh2d, 0x01, 0x18, 0x19),
-GEN_VXFORM_300_EO(vextsw2d, 0x01, 0x18, 0x1A),
GEN_VXFORM_300_EO(vctzb, 0x01, 0x18, 0x1C),
GEN_VXFORM_300_EO(vctzh, 0x01, 0x18, 0x1D),
GEN_VXFORM_300_EO(vctzw, 0x01, 0x18, 0x1E),
--
2.34.1
^ permalink raw reply related [flat|nested] 89+ messages in thread* [PULL 14/87] target/ppc: Implement vextsd2q
2022-03-02 11:06 [PULL 00/87] ppc queue Cédric Le Goater
` (12 preceding siblings ...)
2022-03-02 11:06 ` [PULL 13/87] target/ppc: Move vexts[bhw]2[wd] to decodetree Cédric Le Goater
@ 2022-03-02 11:06 ` Cédric Le Goater
2022-03-02 11:06 ` [PULL 15/87] target/ppc: Move Vector Compare Equal/Not Equal/Greater Than to decodetree Cédric Le Goater
` (73 subsequent siblings)
87 siblings, 0 replies; 89+ messages in thread
From: Cédric Le Goater @ 2022-03-02 11:06 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Cédric Le Goater, Richard Henderson,
Lucas Coutinho, Matheus Ferst
From: Lucas Coutinho <lucas.coutinho@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Lucas Coutinho <lucas.coutinho@eldorado.org.br>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20220225210936.1749575-9-matheus.ferst@eldorado.org.br>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/insn32.decode | 1 +
target/ppc/translate/vmx-impl.c.inc | 18 ++++++++++++++++++
2 files changed, 19 insertions(+)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 1dcf9c61e9c7..cba680075b23 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -426,6 +426,7 @@ VEXTSH2W 000100 ..... 10001 ..... 11000000010 @VX_tb
VEXTSB2D 000100 ..... 11000 ..... 11000000010 @VX_tb
VEXTSH2D 000100 ..... 11001 ..... 11000000010 @VX_tb
VEXTSW2D 000100 ..... 11010 ..... 11000000010 @VX_tb
+VEXTSD2Q 000100 ..... 11011 ..... 11000000010 @VX_tb
## Vector Mask Manipulation Instructions
diff --git a/target/ppc/translate/vmx-impl.c.inc b/target/ppc/translate/vmx-impl.c.inc
index aa021bdf542d..afe56a19d591 100644
--- a/target/ppc/translate/vmx-impl.c.inc
+++ b/target/ppc/translate/vmx-impl.c.inc
@@ -1825,6 +1825,24 @@ TRANS(VEXTSB2D, do_vexts, MO_64, 56);
TRANS(VEXTSH2D, do_vexts, MO_64, 48);
TRANS(VEXTSW2D, do_vexts, MO_64, 32);
+static bool trans_VEXTSD2Q(DisasContext *ctx, arg_VX_tb *a)
+{
+ TCGv_i64 tmp;
+
+ REQUIRE_INSNS_FLAGS2(ctx, ISA310);
+ REQUIRE_VECTOR(ctx);
+
+ tmp = tcg_temp_new_i64();
+
+ get_avr64(tmp, a->vrb, false);
+ set_avr64(a->vrt, tmp, false);
+ tcg_gen_sari_i64(tmp, tmp, 63);
+ set_avr64(a->vrt, tmp, true);
+
+ tcg_temp_free_i64(tmp);
+ return true;
+}
+
GEN_VXFORM_NOA_2(vctzb, 1, 24, 28)
GEN_VXFORM_NOA_2(vctzh, 1, 24, 29)
GEN_VXFORM_NOA_2(vctzw, 1, 24, 30)
--
2.34.1
^ permalink raw reply related [flat|nested] 89+ messages in thread* [PULL 15/87] target/ppc: Move Vector Compare Equal/Not Equal/Greater Than to decodetree
2022-03-02 11:06 [PULL 00/87] ppc queue Cédric Le Goater
` (13 preceding siblings ...)
2022-03-02 11:06 ` [PULL 14/87] target/ppc: Implement vextsd2q Cédric Le Goater
@ 2022-03-02 11:06 ` Cédric Le Goater
2022-03-02 11:06 ` [PULL 16/87] target/ppc: Move Vector Compare Not Equal or Zero " Cédric Le Goater
` (72 subsequent siblings)
87 siblings, 0 replies; 89+ messages in thread
From: Cédric Le Goater @ 2022-03-02 11:06 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Richard Henderson, Matheus Ferst,
Cédric Le Goater
From: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20220225210936.1749575-10-matheus.ferst@eldorado.org.br>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/helper.h | 30 ----------
target/ppc/insn32.decode | 24 ++++++++
target/ppc/int_helper.c | 54 -----------------
target/ppc/translate/vmx-impl.c.inc | 89 ++++++++++++++++++++---------
target/ppc/translate/vmx-ops.c.inc | 15 +----
5 files changed, 88 insertions(+), 124 deletions(-)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 5e64c8371d6e..9f56547d8c81 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -142,46 +142,16 @@ DEF_HELPER_3(vabsduw, void, avr, avr, avr)
DEF_HELPER_3(vavgsb, void, avr, avr, avr)
DEF_HELPER_3(vavgsh, void, avr, avr, avr)
DEF_HELPER_3(vavgsw, void, avr, avr, avr)
-DEF_HELPER_4(vcmpequb, void, env, avr, avr, avr)
-DEF_HELPER_4(vcmpequh, void, env, avr, avr, avr)
-DEF_HELPER_4(vcmpequw, void, env, avr, avr, avr)
-DEF_HELPER_4(vcmpequd, void, env, avr, avr, avr)
-DEF_HELPER_4(vcmpneb, void, env, avr, avr, avr)
-DEF_HELPER_4(vcmpneh, void, env, avr, avr, avr)
-DEF_HELPER_4(vcmpnew, void, env, avr, avr, avr)
DEF_HELPER_4(vcmpnezb, void, env, avr, avr, avr)
DEF_HELPER_4(vcmpnezh, void, env, avr, avr, avr)
DEF_HELPER_4(vcmpnezw, void, env, avr, avr, avr)
-DEF_HELPER_4(vcmpgtub, void, env, avr, avr, avr)
-DEF_HELPER_4(vcmpgtuh, void, env, avr, avr, avr)
-DEF_HELPER_4(vcmpgtuw, void, env, avr, avr, avr)
-DEF_HELPER_4(vcmpgtud, void, env, avr, avr, avr)
-DEF_HELPER_4(vcmpgtsb, void, env, avr, avr, avr)
-DEF_HELPER_4(vcmpgtsh, void, env, avr, avr, avr)
-DEF_HELPER_4(vcmpgtsw, void, env, avr, avr, avr)
-DEF_HELPER_4(vcmpgtsd, void, env, avr, avr, avr)
DEF_HELPER_4(vcmpeqfp, void, env, avr, avr, avr)
DEF_HELPER_4(vcmpgefp, void, env, avr, avr, avr)
DEF_HELPER_4(vcmpgtfp, void, env, avr, avr, avr)
DEF_HELPER_4(vcmpbfp, void, env, avr, avr, avr)
-DEF_HELPER_4(vcmpequb_dot, void, env, avr, avr, avr)
-DEF_HELPER_4(vcmpequh_dot, void, env, avr, avr, avr)
-DEF_HELPER_4(vcmpequw_dot, void, env, avr, avr, avr)
-DEF_HELPER_4(vcmpequd_dot, void, env, avr, avr, avr)
-DEF_HELPER_4(vcmpneb_dot, void, env, avr, avr, avr)
-DEF_HELPER_4(vcmpneh_dot, void, env, avr, avr, avr)
-DEF_HELPER_4(vcmpnew_dot, void, env, avr, avr, avr)
DEF_HELPER_4(vcmpnezb_dot, void, env, avr, avr, avr)
DEF_HELPER_4(vcmpnezh_dot, void, env, avr, avr, avr)
DEF_HELPER_4(vcmpnezw_dot, void, env, avr, avr, avr)
-DEF_HELPER_4(vcmpgtub_dot, void, env, avr, avr, avr)
-DEF_HELPER_4(vcmpgtuh_dot, void, env, avr, avr, avr)
-DEF_HELPER_4(vcmpgtuw_dot, void, env, avr, avr, avr)
-DEF_HELPER_4(vcmpgtud_dot, void, env, avr, avr, avr)
-DEF_HELPER_4(vcmpgtsb_dot, void, env, avr, avr, avr)
-DEF_HELPER_4(vcmpgtsh_dot, void, env, avr, avr, avr)
-DEF_HELPER_4(vcmpgtsw_dot, void, env, avr, avr, avr)
-DEF_HELPER_4(vcmpgtsd_dot, void, env, avr, avr, avr)
DEF_HELPER_4(vcmpeqfp_dot, void, env, avr, avr, avr)
DEF_HELPER_4(vcmpgefp_dot, void, env, avr, avr, avr)
DEF_HELPER_4(vcmpgtfp_dot, void, env, avr, avr, avr)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index cba680075b23..5443ee0394be 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -51,6 +51,9 @@
&VA vrt vra vrb rc
@VA ...... vrt:5 vra:5 vrb:5 rc:5 ...... &VA
+&VC vrt vra vrb rc:bool
+@VC ...... vrt:5 vra:5 vrb:5 rc:1 .......... &VC
+
&VN vrt vra vrb sh
@VN ...... vrt:5 vra:5 vrb:5 .. sh:3 ...... &VN
@@ -373,6 +376,27 @@ DSCLIQ 111111 ..... ..... ...... 001000010 . @Z22_tap_sh_rc
DSCRI 111011 ..... ..... ...... 001100010 . @Z22_ta_sh_rc
DSCRIQ 111111 ..... ..... ...... 001100010 . @Z22_tap_sh_rc
+## Vector Integer Instructions
+
+VCMPEQUB 000100 ..... ..... ..... . 0000000110 @VC
+VCMPEQUH 000100 ..... ..... ..... . 0001000110 @VC
+VCMPEQUW 000100 ..... ..... ..... . 0010000110 @VC
+VCMPEQUD 000100 ..... ..... ..... . 0011000111 @VC
+
+VCMPGTSB 000100 ..... ..... ..... . 1100000110 @VC
+VCMPGTSH 000100 ..... ..... ..... . 1101000110 @VC
+VCMPGTSW 000100 ..... ..... ..... . 1110000110 @VC
+VCMPGTSD 000100 ..... ..... ..... . 1111000111 @VC
+
+VCMPGTUB 000100 ..... ..... ..... . 1000000110 @VC
+VCMPGTUH 000100 ..... ..... ..... . 1001000110 @VC
+VCMPGTUW 000100 ..... ..... ..... . 1010000110 @VC
+VCMPGTUD 000100 ..... ..... ..... . 1011000111 @VC
+
+VCMPNEB 000100 ..... ..... ..... . 0000000111 @VC
+VCMPNEH 000100 ..... ..... ..... . 0001000111 @VC
+VCMPNEW 000100 ..... ..... ..... . 0010000111 @VC
+
## Vector Bit Manipulation Instruction
VCFUGED 000100 ..... ..... ..... 10101001101 @VX
diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
index a75a5482fcc6..734b817b68d2 100644
--- a/target/ppc/int_helper.c
+++ b/target/ppc/int_helper.c
@@ -662,57 +662,6 @@ VCF(ux, uint32_to_float32, u32)
VCF(sx, int32_to_float32, s32)
#undef VCF
-#define VCMP_DO(suffix, compare, element, record) \
- void helper_vcmp##suffix(CPUPPCState *env, ppc_avr_t *r, \
- ppc_avr_t *a, ppc_avr_t *b) \
- { \
- uint64_t ones = (uint64_t)-1; \
- uint64_t all = ones; \
- uint64_t none = 0; \
- int i; \
- \
- for (i = 0; i < ARRAY_SIZE(r->element); i++) { \
- uint64_t result = (a->element[i] compare b->element[i] ? \
- ones : 0x0); \
- switch (sizeof(a->element[0])) { \
- case 8: \
- r->u64[i] = result; \
- break; \
- case 4: \
- r->u32[i] = result; \
- break; \
- case 2: \
- r->u16[i] = result; \
- break; \
- case 1: \
- r->u8[i] = result; \
- break; \
- } \
- all &= result; \
- none |= result; \
- } \
- if (record) { \
- env->crf[6] = ((all != 0) << 3) | ((none == 0) << 1); \
- } \
- }
-#define VCMP(suffix, compare, element) \
- VCMP_DO(suffix, compare, element, 0) \
- VCMP_DO(suffix##_dot, compare, element, 1)
-VCMP(equb, ==, u8)
-VCMP(equh, ==, u16)
-VCMP(equw, ==, u32)
-VCMP(equd, ==, u64)
-VCMP(gtub, >, u8)
-VCMP(gtuh, >, u16)
-VCMP(gtuw, >, u32)
-VCMP(gtud, >, u64)
-VCMP(gtsb, >, s8)
-VCMP(gtsh, >, s16)
-VCMP(gtsw, >, s32)
-VCMP(gtsd, >, s64)
-#undef VCMP_DO
-#undef VCMP
-
#define VCMPNE_DO(suffix, element, etype, cmpzero, record) \
void helper_vcmpne##suffix(CPUPPCState *env, ppc_avr_t *r, \
ppc_avr_t *a, ppc_avr_t *b) \
@@ -751,9 +700,6 @@ void helper_vcmpne##suffix(CPUPPCState *env, ppc_avr_t *r, \
VCMPNE(zb, u8, uint8_t, 1)
VCMPNE(zh, u16, uint16_t, 1)
VCMPNE(zw, u32, uint32_t, 1)
-VCMPNE(b, u8, uint8_t, 0)
-VCMPNE(h, u16, uint16_t, 0)
-VCMPNE(w, u32, uint32_t, 0)
#undef VCMPNE_DO
#undef VCMPNE
diff --git a/target/ppc/translate/vmx-impl.c.inc b/target/ppc/translate/vmx-impl.c.inc
index afe56a19d591..7593b93eabb8 100644
--- a/target/ppc/translate/vmx-impl.c.inc
+++ b/target/ppc/translate/vmx-impl.c.inc
@@ -985,41 +985,74 @@ static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
} \
}
-GEN_VXRFORM(vcmpequb, 3, 0)
-GEN_VXRFORM(vcmpequh, 3, 1)
-GEN_VXRFORM(vcmpequw, 3, 2)
-GEN_VXRFORM(vcmpequd, 3, 3)
GEN_VXRFORM(vcmpnezb, 3, 4)
GEN_VXRFORM(vcmpnezh, 3, 5)
GEN_VXRFORM(vcmpnezw, 3, 6)
-GEN_VXRFORM(vcmpgtsb, 3, 12)
-GEN_VXRFORM(vcmpgtsh, 3, 13)
-GEN_VXRFORM(vcmpgtsw, 3, 14)
-GEN_VXRFORM(vcmpgtsd, 3, 15)
-GEN_VXRFORM(vcmpgtub, 3, 8)
-GEN_VXRFORM(vcmpgtuh, 3, 9)
-GEN_VXRFORM(vcmpgtuw, 3, 10)
-GEN_VXRFORM(vcmpgtud, 3, 11)
+
+static void do_vcmp_rc(int vrt)
+{
+ TCGv_i64 tmp, set, clr;
+
+ tmp = tcg_temp_new_i64();
+ set = tcg_temp_new_i64();
+ clr = tcg_temp_new_i64();
+
+ get_avr64(tmp, vrt, true);
+ tcg_gen_mov_i64(set, tmp);
+ get_avr64(tmp, vrt, false);
+ tcg_gen_or_i64(clr, set, tmp);
+ tcg_gen_and_i64(set, set, tmp);
+
+ tcg_gen_setcondi_i64(TCG_COND_EQ, clr, clr, 0);
+ tcg_gen_shli_i64(clr, clr, 1);
+
+ tcg_gen_setcondi_i64(TCG_COND_EQ, set, set, -1);
+ tcg_gen_shli_i64(set, set, 3);
+
+ tcg_gen_or_i64(tmp, set, clr);
+ tcg_gen_extrl_i64_i32(cpu_crf[6], tmp);
+
+ tcg_temp_free_i64(tmp);
+ tcg_temp_free_i64(set);
+ tcg_temp_free_i64(clr);
+}
+
+static bool do_vcmp(DisasContext *ctx, arg_VC *a, TCGCond cond, int vece)
+{
+ REQUIRE_VECTOR(ctx);
+
+ tcg_gen_gvec_cmp(cond, vece, avr_full_offset(a->vrt),
+ avr_full_offset(a->vra), avr_full_offset(a->vrb), 16, 16);
+
+ if (a->rc) {
+ do_vcmp_rc(a->vrt);
+ }
+
+ return true;
+}
+
+TRANS_FLAGS(ALTIVEC, VCMPEQUB, do_vcmp, TCG_COND_EQ, MO_8)
+TRANS_FLAGS(ALTIVEC, VCMPEQUH, do_vcmp, TCG_COND_EQ, MO_16)
+TRANS_FLAGS(ALTIVEC, VCMPEQUW, do_vcmp, TCG_COND_EQ, MO_32)
+TRANS_FLAGS2(ALTIVEC_207, VCMPEQUD, do_vcmp, TCG_COND_EQ, MO_64)
+
+TRANS_FLAGS(ALTIVEC, VCMPGTSB, do_vcmp, TCG_COND_GT, MO_8)
+TRANS_FLAGS(ALTIVEC, VCMPGTSH, do_vcmp, TCG_COND_GT, MO_16)
+TRANS_FLAGS(ALTIVEC, VCMPGTSW, do_vcmp, TCG_COND_GT, MO_32)
+TRANS_FLAGS2(ALTIVEC_207, VCMPGTSD, do_vcmp, TCG_COND_GT, MO_64)
+TRANS_FLAGS(ALTIVEC, VCMPGTUB, do_vcmp, TCG_COND_GTU, MO_8)
+TRANS_FLAGS(ALTIVEC, VCMPGTUH, do_vcmp, TCG_COND_GTU, MO_16)
+TRANS_FLAGS(ALTIVEC, VCMPGTUW, do_vcmp, TCG_COND_GTU, MO_32)
+TRANS_FLAGS2(ALTIVEC_207, VCMPGTUD, do_vcmp, TCG_COND_GTU, MO_64)
+
+TRANS_FLAGS2(ISA300, VCMPNEB, do_vcmp, TCG_COND_NE, MO_8)
+TRANS_FLAGS2(ISA300, VCMPNEH, do_vcmp, TCG_COND_NE, MO_16)
+TRANS_FLAGS2(ISA300, VCMPNEW, do_vcmp, TCG_COND_NE, MO_32)
+
GEN_VXRFORM(vcmpeqfp, 3, 3)
GEN_VXRFORM(vcmpgefp, 3, 7)
GEN_VXRFORM(vcmpgtfp, 3, 11)
GEN_VXRFORM(vcmpbfp, 3, 15)
-GEN_VXRFORM(vcmpneb, 3, 0)
-GEN_VXRFORM(vcmpneh, 3, 1)
-GEN_VXRFORM(vcmpnew, 3, 2)
-
-GEN_VXRFORM_DUAL(vcmpequb, PPC_ALTIVEC, PPC_NONE, \
- vcmpneb, PPC_NONE, PPC2_ISA300)
-GEN_VXRFORM_DUAL(vcmpequh, PPC_ALTIVEC, PPC_NONE, \
- vcmpneh, PPC_NONE, PPC2_ISA300)
-GEN_VXRFORM_DUAL(vcmpequw, PPC_ALTIVEC, PPC_NONE, \
- vcmpnew, PPC_NONE, PPC2_ISA300)
-GEN_VXRFORM_DUAL(vcmpeqfp, PPC_ALTIVEC, PPC_NONE, \
- vcmpequd, PPC_NONE, PPC2_ALTIVEC_207)
-GEN_VXRFORM_DUAL(vcmpbfp, PPC_ALTIVEC, PPC_NONE, \
- vcmpgtsd, PPC_NONE, PPC2_ALTIVEC_207)
-GEN_VXRFORM_DUAL(vcmpgtfp, PPC_ALTIVEC, PPC_NONE, \
- vcmpgtud, PPC_NONE, PPC2_ALTIVEC_207)
static void gen_vsplti(DisasContext *ctx, int vece)
{
diff --git a/target/ppc/translate/vmx-ops.c.inc b/target/ppc/translate/vmx-ops.c.inc
index 6787327f56ad..80d460c34ee2 100644
--- a/target/ppc/translate/vmx-ops.c.inc
+++ b/target/ppc/translate/vmx-ops.c.inc
@@ -187,19 +187,10 @@ GEN_HANDLER2_E(name, str, 0x4, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ISA300),
GEN_VXRFORM_300(vcmpnezb, 3, 4)
GEN_VXRFORM_300(vcmpnezh, 3, 5)
GEN_VXRFORM_300(vcmpnezw, 3, 6)
-GEN_VXRFORM(vcmpgtsb, 3, 12)
-GEN_VXRFORM(vcmpgtsh, 3, 13)
-GEN_VXRFORM(vcmpgtsw, 3, 14)
-GEN_VXRFORM(vcmpgtub, 3, 8)
-GEN_VXRFORM(vcmpgtuh, 3, 9)
-GEN_VXRFORM(vcmpgtuw, 3, 10)
-GEN_VXRFORM_DUAL(vcmpeqfp, vcmpequd, 3, 3, PPC_ALTIVEC, PPC_NONE)
+GEN_VXRFORM(vcmpeqfp, 3, 3)
GEN_VXRFORM(vcmpgefp, 3, 7)
-GEN_VXRFORM_DUAL(vcmpgtfp, vcmpgtud, 3, 11, PPC_ALTIVEC, PPC_NONE)
-GEN_VXRFORM_DUAL(vcmpbfp, vcmpgtsd, 3, 15, PPC_ALTIVEC, PPC_NONE)
-GEN_VXRFORM_DUAL(vcmpequb, vcmpneb, 3, 0, PPC_ALTIVEC, PPC_NONE)
-GEN_VXRFORM_DUAL(vcmpequh, vcmpneh, 3, 1, PPC_ALTIVEC, PPC_NONE)
-GEN_VXRFORM_DUAL(vcmpequw, vcmpnew, 3, 2, PPC_ALTIVEC, PPC_NONE)
+GEN_VXRFORM(vcmpgtfp, 3, 11)
+GEN_VXRFORM(vcmpbfp, 3, 15)
#define GEN_VXFORM_DUAL_INV(name0, name1, opc2, opc3, inval0, inval1, type) \
GEN_OPCODE_DUAL(name0##_##name1, 0x04, opc2, opc3, inval0, inval1, type, \
--
2.34.1
^ permalink raw reply related [flat|nested] 89+ messages in thread* [PULL 16/87] target/ppc: Move Vector Compare Not Equal or Zero to decodetree
2022-03-02 11:06 [PULL 00/87] ppc queue Cédric Le Goater
` (14 preceding siblings ...)
2022-03-02 11:06 ` [PULL 15/87] target/ppc: Move Vector Compare Equal/Not Equal/Greater Than to decodetree Cédric Le Goater
@ 2022-03-02 11:06 ` Cédric Le Goater
2022-03-02 11:06 ` [PULL 17/87] target/ppc: Implement Vector Compare Equal Quadword Cédric Le Goater
` (71 subsequent siblings)
87 siblings, 0 replies; 89+ messages in thread
From: Cédric Le Goater @ 2022-03-02 11:06 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Richard Henderson, Matheus Ferst,
Cédric Le Goater
From: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20220225210936.1749575-11-matheus.ferst@eldorado.org.br>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/helper.h | 9 ++--
target/ppc/insn32.decode | 4 ++
target/ppc/int_helper.c | 50 +++++-----------------
target/ppc/translate/vmx-impl.c.inc | 66 +++++++++++++++++++++++++++--
target/ppc/translate/vmx-ops.c.inc | 3 --
5 files changed, 80 insertions(+), 52 deletions(-)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 9f56547d8c81..e5dd1c53f5ba 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -142,16 +142,13 @@ DEF_HELPER_3(vabsduw, void, avr, avr, avr)
DEF_HELPER_3(vavgsb, void, avr, avr, avr)
DEF_HELPER_3(vavgsh, void, avr, avr, avr)
DEF_HELPER_3(vavgsw, void, avr, avr, avr)
-DEF_HELPER_4(vcmpnezb, void, env, avr, avr, avr)
-DEF_HELPER_4(vcmpnezh, void, env, avr, avr, avr)
-DEF_HELPER_4(vcmpnezw, void, env, avr, avr, avr)
DEF_HELPER_4(vcmpeqfp, void, env, avr, avr, avr)
DEF_HELPER_4(vcmpgefp, void, env, avr, avr, avr)
DEF_HELPER_4(vcmpgtfp, void, env, avr, avr, avr)
DEF_HELPER_4(vcmpbfp, void, env, avr, avr, avr)
-DEF_HELPER_4(vcmpnezb_dot, void, env, avr, avr, avr)
-DEF_HELPER_4(vcmpnezh_dot, void, env, avr, avr, avr)
-DEF_HELPER_4(vcmpnezw_dot, void, env, avr, avr, avr)
+DEF_HELPER_FLAGS_4(VCMPNEZB, TCG_CALL_NO_RWG, void, avr, avr, avr, i32)
+DEF_HELPER_FLAGS_4(VCMPNEZH, TCG_CALL_NO_RWG, void, avr, avr, avr, i32)
+DEF_HELPER_FLAGS_4(VCMPNEZW, TCG_CALL_NO_RWG, void, avr, avr, avr, i32)
DEF_HELPER_4(vcmpeqfp_dot, void, env, avr, avr, avr)
DEF_HELPER_4(vcmpgefp_dot, void, env, avr, avr, avr)
DEF_HELPER_4(vcmpgtfp_dot, void, env, avr, avr, avr)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 5443ee0394be..be9e05cc73b3 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -397,6 +397,10 @@ VCMPNEB 000100 ..... ..... ..... . 0000000111 @VC
VCMPNEH 000100 ..... ..... ..... . 0001000111 @VC
VCMPNEW 000100 ..... ..... ..... . 0010000111 @VC
+VCMPNEZB 000100 ..... ..... ..... . 0100000111 @VC
+VCMPNEZH 000100 ..... ..... ..... . 0101000111 @VC
+VCMPNEZW 000100 ..... ..... ..... . 0110000111 @VC
+
## Vector Bit Manipulation Instruction
VCFUGED 000100 ..... ..... ..... 10101001101 @VX
diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
index 734b817b68d2..f31dba946942 100644
--- a/target/ppc/int_helper.c
+++ b/target/ppc/int_helper.c
@@ -662,46 +662,18 @@ VCF(ux, uint32_to_float32, u32)
VCF(sx, int32_to_float32, s32)
#undef VCF
-#define VCMPNE_DO(suffix, element, etype, cmpzero, record) \
-void helper_vcmpne##suffix(CPUPPCState *env, ppc_avr_t *r, \
- ppc_avr_t *a, ppc_avr_t *b) \
-{ \
- etype ones = (etype)-1; \
- etype all = ones; \
- etype result, none = 0; \
- int i; \
- \
- for (i = 0; i < ARRAY_SIZE(r->element); i++) { \
- if (cmpzero) { \
- result = ((a->element[i] == 0) \
- || (b->element[i] == 0) \
- || (a->element[i] != b->element[i]) ? \
- ones : 0x0); \
- } else { \
- result = (a->element[i] != b->element[i]) ? ones : 0x0; \
- } \
- r->element[i] = result; \
- all &= result; \
- none |= result; \
- } \
- if (record) { \
- env->crf[6] = ((all != 0) << 3) | ((none == 0) << 1); \
- } \
+#define VCMPNEZ(NAME, ELEM) \
+void helper_##NAME(ppc_vsr_t *t, ppc_vsr_t *a, ppc_vsr_t *b, uint32_t desc) \
+{ \
+ for (int i = 0; i < ARRAY_SIZE(t->ELEM); i++) { \
+ t->ELEM[i] = ((a->ELEM[i] == 0) || (b->ELEM[i] == 0) || \
+ (a->ELEM[i] != b->ELEM[i])) ? -1 : 0; \
+ } \
}
-
-/*
- * VCMPNEZ - Vector compare not equal to zero
- * suffix - instruction mnemonic suffix (b: byte, h: halfword, w: word)
- * element - element type to access from vector
- */
-#define VCMPNE(suffix, element, etype, cmpzero) \
- VCMPNE_DO(suffix, element, etype, cmpzero, 0) \
- VCMPNE_DO(suffix##_dot, element, etype, cmpzero, 1)
-VCMPNE(zb, u8, uint8_t, 1)
-VCMPNE(zh, u16, uint16_t, 1)
-VCMPNE(zw, u32, uint32_t, 1)
-#undef VCMPNE_DO
-#undef VCMPNE
+VCMPNEZ(VCMPNEZB, u8)
+VCMPNEZ(VCMPNEZH, u16)
+VCMPNEZ(VCMPNEZW, u32)
+#undef VCMPNEZ
#define VCMPFP_DO(suffix, compare, order, record) \
void helper_vcmp##suffix(CPUPPCState *env, ppc_avr_t *r, \
diff --git a/target/ppc/translate/vmx-impl.c.inc b/target/ppc/translate/vmx-impl.c.inc
index 7593b93eabb8..0574bb8bab7b 100644
--- a/target/ppc/translate/vmx-impl.c.inc
+++ b/target/ppc/translate/vmx-impl.c.inc
@@ -985,10 +985,6 @@ static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
} \
}
-GEN_VXRFORM(vcmpnezb, 3, 4)
-GEN_VXRFORM(vcmpnezh, 3, 5)
-GEN_VXRFORM(vcmpnezw, 3, 6)
-
static void do_vcmp_rc(int vrt)
{
TCGv_i64 tmp, set, clr;
@@ -1049,6 +1045,68 @@ TRANS_FLAGS2(ISA300, VCMPNEB, do_vcmp, TCG_COND_NE, MO_8)
TRANS_FLAGS2(ISA300, VCMPNEH, do_vcmp, TCG_COND_NE, MO_16)
TRANS_FLAGS2(ISA300, VCMPNEW, do_vcmp, TCG_COND_NE, MO_32)
+static void gen_vcmpnez_vec(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b)
+{
+ TCGv_vec t0, t1, zero;
+
+ t0 = tcg_temp_new_vec_matching(t);
+ t1 = tcg_temp_new_vec_matching(t);
+ zero = tcg_constant_vec_matching(t, vece, 0);
+
+ tcg_gen_cmp_vec(TCG_COND_EQ, vece, t0, a, zero);
+ tcg_gen_cmp_vec(TCG_COND_EQ, vece, t1, b, zero);
+ tcg_gen_cmp_vec(TCG_COND_NE, vece, t, a, b);
+
+ tcg_gen_or_vec(vece, t, t, t0);
+ tcg_gen_or_vec(vece, t, t, t1);
+
+ tcg_temp_free_vec(t0);
+ tcg_temp_free_vec(t1);
+}
+
+static bool do_vcmpnez(DisasContext *ctx, arg_VC *a, int vece)
+{
+ static const TCGOpcode vecop_list[] = {
+ INDEX_op_cmp_vec, 0
+ };
+ static const GVecGen3 ops[3] = {
+ {
+ .fniv = gen_vcmpnez_vec,
+ .fno = gen_helper_VCMPNEZB,
+ .opt_opc = vecop_list,
+ .vece = MO_8
+ },
+ {
+ .fniv = gen_vcmpnez_vec,
+ .fno = gen_helper_VCMPNEZH,
+ .opt_opc = vecop_list,
+ .vece = MO_16
+ },
+ {
+ .fniv = gen_vcmpnez_vec,
+ .fno = gen_helper_VCMPNEZW,
+ .opt_opc = vecop_list,
+ .vece = MO_32
+ }
+ };
+
+ REQUIRE_INSNS_FLAGS2(ctx, ISA300);
+ REQUIRE_VECTOR(ctx);
+
+ tcg_gen_gvec_3(avr_full_offset(a->vrt), avr_full_offset(a->vra),
+ avr_full_offset(a->vrb), 16, 16, &ops[vece]);
+
+ if (a->rc) {
+ do_vcmp_rc(a->vrt);
+ }
+
+ return true;
+}
+
+TRANS(VCMPNEZB, do_vcmpnez, MO_8)
+TRANS(VCMPNEZH, do_vcmpnez, MO_16)
+TRANS(VCMPNEZW, do_vcmpnez, MO_32)
+
GEN_VXRFORM(vcmpeqfp, 3, 3)
GEN_VXRFORM(vcmpgefp, 3, 7)
GEN_VXRFORM(vcmpgtfp, 3, 11)
diff --git a/target/ppc/translate/vmx-ops.c.inc b/target/ppc/translate/vmx-ops.c.inc
index 80d460c34ee2..cb4c5bb953c1 100644
--- a/target/ppc/translate/vmx-ops.c.inc
+++ b/target/ppc/translate/vmx-ops.c.inc
@@ -184,9 +184,6 @@ GEN_HANDLER2_E(name, str, 0x4, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ISA300),
GEN_VXRFORM1_300(name, name, #name, opc2, opc3) \
GEN_VXRFORM1_300(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
-GEN_VXRFORM_300(vcmpnezb, 3, 4)
-GEN_VXRFORM_300(vcmpnezh, 3, 5)
-GEN_VXRFORM_300(vcmpnezw, 3, 6)
GEN_VXRFORM(vcmpeqfp, 3, 3)
GEN_VXRFORM(vcmpgefp, 3, 7)
GEN_VXRFORM(vcmpgtfp, 3, 11)
--
2.34.1
^ permalink raw reply related [flat|nested] 89+ messages in thread* [PULL 17/87] target/ppc: Implement Vector Compare Equal Quadword
2022-03-02 11:06 [PULL 00/87] ppc queue Cédric Le Goater
` (15 preceding siblings ...)
2022-03-02 11:06 ` [PULL 16/87] target/ppc: Move Vector Compare Not Equal or Zero " Cédric Le Goater
@ 2022-03-02 11:06 ` Cédric Le Goater
2022-03-02 11:06 ` [PULL 18/87] target/ppc: Implement Vector Compare Greater Than Quadword Cédric Le Goater
` (70 subsequent siblings)
87 siblings, 0 replies; 89+ messages in thread
From: Cédric Le Goater @ 2022-03-02 11:06 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Richard Henderson, Matheus Ferst,
Cédric Le Goater
From: Matheus Ferst <matheus.ferst@eldorado.org.br>
Implement the following PowerISA v3.1 instructions:
vcmpequq: Vector Compare Equal Quadword
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20220225210936.1749575-12-matheus.ferst@eldorado.org.br>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/insn32.decode | 1 +
target/ppc/translate/vmx-impl.c.inc | 36 +++++++++++++++++++++++++++++
2 files changed, 37 insertions(+)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index be9e05cc73b3..437a3e29e059 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -382,6 +382,7 @@ VCMPEQUB 000100 ..... ..... ..... . 0000000110 @VC
VCMPEQUH 000100 ..... ..... ..... . 0001000110 @VC
VCMPEQUW 000100 ..... ..... ..... . 0010000110 @VC
VCMPEQUD 000100 ..... ..... ..... . 0011000111 @VC
+VCMPEQUQ 000100 ..... ..... ..... . 0111000111 @VC
VCMPGTSB 000100 ..... ..... ..... . 1100000110 @VC
VCMPGTSH 000100 ..... ..... ..... . 1101000110 @VC
diff --git a/target/ppc/translate/vmx-impl.c.inc b/target/ppc/translate/vmx-impl.c.inc
index 0574bb8bab7b..b7e9afb97897 100644
--- a/target/ppc/translate/vmx-impl.c.inc
+++ b/target/ppc/translate/vmx-impl.c.inc
@@ -1107,6 +1107,42 @@ TRANS(VCMPNEZB, do_vcmpnez, MO_8)
TRANS(VCMPNEZH, do_vcmpnez, MO_16)
TRANS(VCMPNEZW, do_vcmpnez, MO_32)
+static bool trans_VCMPEQUQ(DisasContext *ctx, arg_VC *a)
+{
+ TCGv_i64 t0, t1, t2;
+
+ t0 = tcg_temp_new_i64();
+ t1 = tcg_temp_new_i64();
+ t2 = tcg_temp_new_i64();
+
+ get_avr64(t0, a->vra, true);
+ get_avr64(t1, a->vrb, true);
+ tcg_gen_xor_i64(t2, t0, t1);
+
+ get_avr64(t0, a->vra, false);
+ get_avr64(t1, a->vrb, false);
+ tcg_gen_xor_i64(t1, t0, t1);
+
+ tcg_gen_or_i64(t1, t1, t2);
+ tcg_gen_setcondi_i64(TCG_COND_EQ, t1, t1, 0);
+ tcg_gen_neg_i64(t1, t1);
+
+ set_avr64(a->vrt, t1, true);
+ set_avr64(a->vrt, t1, false);
+
+ if (a->rc) {
+ tcg_gen_extrl_i64_i32(cpu_crf[6], t1);
+ tcg_gen_andi_i32(cpu_crf[6], cpu_crf[6], 0xa);
+ tcg_gen_xori_i32(cpu_crf[6], cpu_crf[6], 0x2);
+ }
+
+ tcg_temp_free_i64(t0);
+ tcg_temp_free_i64(t1);
+ tcg_temp_free_i64(t2);
+
+ return true;
+}
+
GEN_VXRFORM(vcmpeqfp, 3, 3)
GEN_VXRFORM(vcmpgefp, 3, 7)
GEN_VXRFORM(vcmpgtfp, 3, 11)
--
2.34.1
^ permalink raw reply related [flat|nested] 89+ messages in thread* [PULL 18/87] target/ppc: Implement Vector Compare Greater Than Quadword
2022-03-02 11:06 [PULL 00/87] ppc queue Cédric Le Goater
` (16 preceding siblings ...)
2022-03-02 11:06 ` [PULL 17/87] target/ppc: Implement Vector Compare Equal Quadword Cédric Le Goater
@ 2022-03-02 11:06 ` Cédric Le Goater
2022-03-02 11:06 ` [PULL 19/87] target/ppc: Implement Vector Compare Quadword Cédric Le Goater
` (69 subsequent siblings)
87 siblings, 0 replies; 89+ messages in thread
From: Cédric Le Goater @ 2022-03-02 11:06 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Richard Henderson, Matheus Ferst,
Cédric Le Goater
From: Matheus Ferst <matheus.ferst@eldorado.org.br>
Implement the following PowerISA v3.1 instructions:
vcmpgtsq: Vector Compare Greater Than Signed Quadword
vcmpgtuq: Vector Compare Greater Than Unsigned Quadword
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20220225210936.1749575-13-matheus.ferst@eldorado.org.br>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/insn32.decode | 2 ++
target/ppc/translate/vmx-impl.c.inc | 39 +++++++++++++++++++++++++++++
2 files changed, 41 insertions(+)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 437a3e29e059..07a4ef910342 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -388,11 +388,13 @@ VCMPGTSB 000100 ..... ..... ..... . 1100000110 @VC
VCMPGTSH 000100 ..... ..... ..... . 1101000110 @VC
VCMPGTSW 000100 ..... ..... ..... . 1110000110 @VC
VCMPGTSD 000100 ..... ..... ..... . 1111000111 @VC
+VCMPGTSQ 000100 ..... ..... ..... . 1110000111 @VC
VCMPGTUB 000100 ..... ..... ..... . 1000000110 @VC
VCMPGTUH 000100 ..... ..... ..... . 1001000110 @VC
VCMPGTUW 000100 ..... ..... ..... . 1010000110 @VC
VCMPGTUD 000100 ..... ..... ..... . 1011000111 @VC
+VCMPGTUQ 000100 ..... ..... ..... . 1010000111 @VC
VCMPNEB 000100 ..... ..... ..... . 0000000111 @VC
VCMPNEH 000100 ..... ..... ..... . 0001000111 @VC
diff --git a/target/ppc/translate/vmx-impl.c.inc b/target/ppc/translate/vmx-impl.c.inc
index b7e9afb97897..7f9913235e97 100644
--- a/target/ppc/translate/vmx-impl.c.inc
+++ b/target/ppc/translate/vmx-impl.c.inc
@@ -1143,6 +1143,45 @@ static bool trans_VCMPEQUQ(DisasContext *ctx, arg_VC *a)
return true;
}
+static bool do_vcmpgtq(DisasContext *ctx, arg_VC *a, bool sign)
+{
+ TCGv_i64 t0, t1, t2;
+
+ t0 = tcg_temp_new_i64();
+ t1 = tcg_temp_new_i64();
+ t2 = tcg_temp_new_i64();
+
+ get_avr64(t0, a->vra, false);
+ get_avr64(t1, a->vrb, false);
+ tcg_gen_setcond_i64(TCG_COND_GTU, t2, t0, t1);
+
+ get_avr64(t0, a->vra, true);
+ get_avr64(t1, a->vrb, true);
+ tcg_gen_movcond_i64(TCG_COND_EQ, t2, t0, t1, t2, tcg_constant_i64(0));
+ tcg_gen_setcond_i64(sign ? TCG_COND_GT : TCG_COND_GTU, t1, t0, t1);
+
+ tcg_gen_or_i64(t1, t1, t2);
+ tcg_gen_neg_i64(t1, t1);
+
+ set_avr64(a->vrt, t1, true);
+ set_avr64(a->vrt, t1, false);
+
+ if (a->rc) {
+ tcg_gen_extrl_i64_i32(cpu_crf[6], t1);
+ tcg_gen_andi_i32(cpu_crf[6], cpu_crf[6], 0xa);
+ tcg_gen_xori_i32(cpu_crf[6], cpu_crf[6], 0x2);
+ }
+
+ tcg_temp_free_i64(t0);
+ tcg_temp_free_i64(t1);
+ tcg_temp_free_i64(t2);
+
+ return true;
+}
+
+TRANS(VCMPGTSQ, do_vcmpgtq, true)
+TRANS(VCMPGTUQ, do_vcmpgtq, false)
+
GEN_VXRFORM(vcmpeqfp, 3, 3)
GEN_VXRFORM(vcmpgefp, 3, 7)
GEN_VXRFORM(vcmpgtfp, 3, 11)
--
2.34.1
^ permalink raw reply related [flat|nested] 89+ messages in thread* [PULL 19/87] target/ppc: Implement Vector Compare Quadword
2022-03-02 11:06 [PULL 00/87] ppc queue Cédric Le Goater
` (17 preceding siblings ...)
2022-03-02 11:06 ` [PULL 18/87] target/ppc: Implement Vector Compare Greater Than Quadword Cédric Le Goater
@ 2022-03-02 11:06 ` Cédric Le Goater
2022-03-02 11:06 ` [PULL 20/87] target/ppc: implement vstri[bh][lr] Cédric Le Goater
` (68 subsequent siblings)
87 siblings, 0 replies; 89+ messages in thread
From: Cédric Le Goater @ 2022-03-02 11:06 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Richard Henderson, Matheus Ferst,
Cédric Le Goater
From: Matheus Ferst <matheus.ferst@eldorado.org.br>
Implement the following PowerISA v3.1 instructions:
vcmpsq: Vector Compare Signed Quadword
vcmpuq: Vector Compare Unsigned Quadword
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20220225210936.1749575-14-matheus.ferst@eldorado.org.br>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/insn32.decode | 6 ++++
target/ppc/translate/vmx-impl.c.inc | 45 +++++++++++++++++++++++++++++
2 files changed, 51 insertions(+)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 07a4ef910342..f0cb6602e25a 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -60,6 +60,9 @@
&VX vrt vra vrb
@VX ...... vrt:5 vra:5 vrb:5 .......... . &VX
+&VX_bf bf vra vrb
+@VX_bf ...... bf:3 .. vra:5 vrb:5 ........... &VX_bf
+
&VX_uim4 vrt uim vrb
@VX_uim4 ...... vrt:5 . uim:4 vrb:5 ........... &VX_uim4
@@ -404,6 +407,9 @@ VCMPNEZB 000100 ..... ..... ..... . 0100000111 @VC
VCMPNEZH 000100 ..... ..... ..... . 0101000111 @VC
VCMPNEZW 000100 ..... ..... ..... . 0110000111 @VC
+VCMPSQ 000100 ... -- ..... ..... 00101000001 @VX_bf
+VCMPUQ 000100 ... -- ..... ..... 00100000001 @VX_bf
+
## Vector Bit Manipulation Instruction
VCFUGED 000100 ..... ..... ..... 10101001101 @VX
diff --git a/target/ppc/translate/vmx-impl.c.inc b/target/ppc/translate/vmx-impl.c.inc
index 7f9913235e97..ba2106dc7c5e 100644
--- a/target/ppc/translate/vmx-impl.c.inc
+++ b/target/ppc/translate/vmx-impl.c.inc
@@ -1182,6 +1182,51 @@ static bool do_vcmpgtq(DisasContext *ctx, arg_VC *a, bool sign)
TRANS(VCMPGTSQ, do_vcmpgtq, true)
TRANS(VCMPGTUQ, do_vcmpgtq, false)
+static bool do_vcmpq(DisasContext *ctx, arg_VX_bf *a, bool sign)
+{
+ TCGv_i64 vra, vrb;
+ TCGLabel *gt, *lt, *done;
+
+ REQUIRE_INSNS_FLAGS2(ctx, ISA310);
+ REQUIRE_VECTOR(ctx);
+
+ vra = tcg_temp_local_new_i64();
+ vrb = tcg_temp_local_new_i64();
+ gt = gen_new_label();
+ lt = gen_new_label();
+ done = gen_new_label();
+
+ get_avr64(vra, a->vra, true);
+ get_avr64(vrb, a->vrb, true);
+ tcg_gen_brcond_i64((sign ? TCG_COND_GT : TCG_COND_GTU), vra, vrb, gt);
+ tcg_gen_brcond_i64((sign ? TCG_COND_LT : TCG_COND_LTU), vra, vrb, lt);
+
+ get_avr64(vra, a->vra, false);
+ get_avr64(vrb, a->vrb, false);
+ tcg_gen_brcond_i64(TCG_COND_GTU, vra, vrb, gt);
+ tcg_gen_brcond_i64(TCG_COND_LTU, vra, vrb, lt);
+
+ tcg_gen_movi_i32(cpu_crf[a->bf], CRF_EQ);
+ tcg_gen_br(done);
+
+ gen_set_label(gt);
+ tcg_gen_movi_i32(cpu_crf[a->bf], CRF_GT);
+ tcg_gen_br(done);
+
+ gen_set_label(lt);
+ tcg_gen_movi_i32(cpu_crf[a->bf], CRF_LT);
+ tcg_gen_br(done);
+
+ gen_set_label(done);
+ tcg_temp_free_i64(vra);
+ tcg_temp_free_i64(vrb);
+
+ return true;
+}
+
+TRANS(VCMPSQ, do_vcmpq, true)
+TRANS(VCMPUQ, do_vcmpq, false)
+
GEN_VXRFORM(vcmpeqfp, 3, 3)
GEN_VXRFORM(vcmpgefp, 3, 7)
GEN_VXRFORM(vcmpgtfp, 3, 11)
--
2.34.1
^ permalink raw reply related [flat|nested] 89+ messages in thread* [PULL 20/87] target/ppc: implement vstri[bh][lr]
2022-03-02 11:06 [PULL 00/87] ppc queue Cédric Le Goater
` (18 preceding siblings ...)
2022-03-02 11:06 ` [PULL 19/87] target/ppc: Implement Vector Compare Quadword Cédric Le Goater
@ 2022-03-02 11:06 ` Cédric Le Goater
2022-03-02 11:06 ` [PULL 21/87] target/ppc: implement vclrlb Cédric Le Goater
` (67 subsequent siblings)
87 siblings, 0 replies; 89+ messages in thread
From: Cédric Le Goater @ 2022-03-02 11:06 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Richard Henderson, Matheus Ferst,
Cédric Le Goater
From: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20220225210936.1749575-15-matheus.ferst@eldorado.org.br>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/helper.h | 4 ++++
target/ppc/insn32.decode | 10 ++++++++++
target/ppc/int_helper.c | 28 +++++++++++++++++++++++++++
target/ppc/translate/vmx-impl.c.inc | 30 +++++++++++++++++++++++++++++
4 files changed, 72 insertions(+)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index e5dd1c53f5ba..2c6146d55eb0 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -209,6 +209,10 @@ DEF_HELPER_4(VINSBLX, void, env, avr, i64, tl)
DEF_HELPER_4(VINSHLX, void, env, avr, i64, tl)
DEF_HELPER_4(VINSWLX, void, env, avr, i64, tl)
DEF_HELPER_4(VINSDLX, void, env, avr, i64, tl)
+DEF_HELPER_FLAGS_2(VSTRIBL, TCG_CALL_NO_RWG, i32, avr, avr)
+DEF_HELPER_FLAGS_2(VSTRIBR, TCG_CALL_NO_RWG, i32, avr, avr)
+DEF_HELPER_FLAGS_2(VSTRIHL, TCG_CALL_NO_RWG, i32, avr, avr)
+DEF_HELPER_FLAGS_2(VSTRIHR, TCG_CALL_NO_RWG, i32, avr, avr)
DEF_HELPER_2(vnegw, void, avr, avr)
DEF_HELPER_2(vnegd, void, avr, avr)
DEF_HELPER_2(vupkhpx, void, avr, avr)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index f0cb6602e25a..d844d868291a 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -63,6 +63,9 @@
&VX_bf bf vra vrb
@VX_bf ...... bf:3 .. vra:5 vrb:5 ........... &VX_bf
+&VX_tb_rc vrt vrb rc:bool
+@VX_tb_rc ...... vrt:5 ..... vrb:5 rc:1 .......... &VX_tb_rc
+
&VX_uim4 vrt uim vrb
@VX_uim4 ...... vrt:5 . uim:4 vrb:5 ........... &VX_uim4
@@ -519,6 +522,13 @@ VMULLD 000100 ..... ..... ..... 00111001001 @VX
VMSUMCUD 000100 ..... ..... ..... ..... 010111 @VA
VMSUMUDM 000100 ..... ..... ..... ..... 100011 @VA
+## Vector String Instructions
+
+VSTRIBL 000100 ..... 00000 ..... . 0000001101 @VX_tb_rc
+VSTRIBR 000100 ..... 00001 ..... . 0000001101 @VX_tb_rc
+VSTRIHL 000100 ..... 00010 ..... . 0000001101 @VX_tb_rc
+VSTRIHR 000100 ..... 00011 ..... . 0000001101 @VX_tb_rc
+
# VSX Load/Store Instructions
LXV 111101 ..... ..... ............ . 001 @DQ_TSX
diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
index f31dba946942..71b31fbd891d 100644
--- a/target/ppc/int_helper.c
+++ b/target/ppc/int_helper.c
@@ -1502,6 +1502,34 @@ VEXTRACT(uw, u32)
VEXTRACT(d, u64)
#undef VEXTRACT
+#define VSTRI(NAME, ELEM, NUM_ELEMS, LEFT) \
+uint32_t helper_##NAME(ppc_avr_t *t, ppc_avr_t *b) \
+{ \
+ int i, idx, crf = 0; \
+ \
+ for (i = 0; i < NUM_ELEMS; i++) { \
+ idx = LEFT ? i : NUM_ELEMS - i - 1; \
+ if (b->Vsr##ELEM(idx)) { \
+ t->Vsr##ELEM(idx) = b->Vsr##ELEM(idx); \
+ } else { \
+ crf = 0b0010; \
+ break; \
+ } \
+ } \
+ \
+ for (; i < NUM_ELEMS; i++) { \
+ idx = LEFT ? i : NUM_ELEMS - i - 1; \
+ t->Vsr##ELEM(idx) = 0; \
+ } \
+ \
+ return crf; \
+}
+VSTRI(VSTRIBL, B, 16, true)
+VSTRI(VSTRIBR, B, 16, false)
+VSTRI(VSTRIHL, H, 8, true)
+VSTRI(VSTRIHR, H, 8, false)
+#undef VSTRI
+
void helper_xxextractuw(CPUPPCState *env, ppc_vsr_t *xt,
ppc_vsr_t *xb, uint32_t index)
{
diff --git a/target/ppc/translate/vmx-impl.c.inc b/target/ppc/translate/vmx-impl.c.inc
index ba2106dc7c5e..6962929826ff 100644
--- a/target/ppc/translate/vmx-impl.c.inc
+++ b/target/ppc/translate/vmx-impl.c.inc
@@ -1910,6 +1910,36 @@ static bool trans_MTVSRBMI(DisasContext *ctx, arg_DX_b *a)
return true;
}
+static bool do_vstri(DisasContext *ctx, arg_VX_tb_rc *a,
+ void (*gen_helper)(TCGv_i32, TCGv_ptr, TCGv_ptr))
+{
+ TCGv_ptr vrt, vrb;
+
+ REQUIRE_INSNS_FLAGS2(ctx, ISA310);
+ REQUIRE_VECTOR(ctx);
+
+ vrt = gen_avr_ptr(a->vrt);
+ vrb = gen_avr_ptr(a->vrb);
+
+ if (a->rc) {
+ gen_helper(cpu_crf[6], vrt, vrb);
+ } else {
+ TCGv_i32 discard = tcg_temp_new_i32();
+ gen_helper(discard, vrt, vrb);
+ tcg_temp_free_i32(discard);
+ }
+
+ tcg_temp_free_ptr(vrt);
+ tcg_temp_free_ptr(vrb);
+
+ return true;
+}
+
+TRANS(VSTRIBL, do_vstri, gen_helper_VSTRIBL)
+TRANS(VSTRIBR, do_vstri, gen_helper_VSTRIBR)
+TRANS(VSTRIHL, do_vstri, gen_helper_VSTRIHL)
+TRANS(VSTRIHR, do_vstri, gen_helper_VSTRIHR)
+
#define GEN_VAFORM_PAIRED(name0, name1, opc2) \
static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
{ \
--
2.34.1
^ permalink raw reply related [flat|nested] 89+ messages in thread* [PULL 21/87] target/ppc: implement vclrlb
2022-03-02 11:06 [PULL 00/87] ppc queue Cédric Le Goater
` (19 preceding siblings ...)
2022-03-02 11:06 ` [PULL 20/87] target/ppc: implement vstri[bh][lr] Cédric Le Goater
@ 2022-03-02 11:06 ` Cédric Le Goater
2022-03-02 11:06 ` [PULL 22/87] target/ppc: implement vclrrb Cédric Le Goater
` (66 subsequent siblings)
87 siblings, 0 replies; 89+ messages in thread
From: Cédric Le Goater @ 2022-03-02 11:06 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Richard Henderson, Matheus Ferst,
Cédric Le Goater
From: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20220225210936.1749575-16-matheus.ferst@eldorado.org.br>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/insn32.decode | 2 ++
target/ppc/translate/vmx-impl.c.inc | 40 +++++++++++++++++++++++++++++
2 files changed, 42 insertions(+)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index d844d868291a..31cdbba86bfb 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -529,6 +529,8 @@ VSTRIBR 000100 ..... 00001 ..... . 0000001101 @VX_tb_rc
VSTRIHL 000100 ..... 00010 ..... . 0000001101 @VX_tb_rc
VSTRIHR 000100 ..... 00011 ..... . 0000001101 @VX_tb_rc
+VCLRLB 000100 ..... ..... ..... 00110001101 @VX
+
# VSX Load/Store Instructions
LXV 111101 ..... ..... ............ . 001 @DQ_TSX
diff --git a/target/ppc/translate/vmx-impl.c.inc b/target/ppc/translate/vmx-impl.c.inc
index 6962929826ff..d43fba00ed43 100644
--- a/target/ppc/translate/vmx-impl.c.inc
+++ b/target/ppc/translate/vmx-impl.c.inc
@@ -1940,6 +1940,46 @@ TRANS(VSTRIBR, do_vstri, gen_helper_VSTRIBR)
TRANS(VSTRIHL, do_vstri, gen_helper_VSTRIHL)
TRANS(VSTRIHR, do_vstri, gen_helper_VSTRIHR)
+static bool trans_VCLRLB(DisasContext *ctx, arg_VX *a)
+{
+ TCGv_i64 rb, mh, ml, tmp,
+ ones = tcg_constant_i64(-1),
+ zero = tcg_constant_i64(0);
+
+ rb = tcg_temp_new_i64();
+ mh = tcg_temp_new_i64();
+ ml = tcg_temp_new_i64();
+ tmp = tcg_temp_new_i64();
+
+ tcg_gen_extu_tl_i64(rb, cpu_gpr[a->vrb]);
+ tcg_gen_andi_i64(tmp, rb, 7);
+ tcg_gen_shli_i64(tmp, tmp, 3);
+ tcg_gen_shl_i64(tmp, ones, tmp);
+ tcg_gen_not_i64(tmp, tmp);
+
+ tcg_gen_movcond_i64(TCG_COND_LTU, ml, rb, tcg_constant_i64(8),
+ tmp, ones);
+ tcg_gen_movcond_i64(TCG_COND_LTU, mh, rb, tcg_constant_i64(8),
+ zero, tmp);
+ tcg_gen_movcond_i64(TCG_COND_LTU, mh, rb, tcg_constant_i64(16),
+ mh, ones);
+
+ get_avr64(tmp, a->vra, true);
+ tcg_gen_and_i64(tmp, tmp, mh);
+ set_avr64(a->vrt, tmp, true);
+
+ get_avr64(tmp, a->vra, false);
+ tcg_gen_and_i64(tmp, tmp, ml);
+ set_avr64(a->vrt, tmp, false);
+
+ tcg_temp_free_i64(rb);
+ tcg_temp_free_i64(mh);
+ tcg_temp_free_i64(ml);
+ tcg_temp_free_i64(tmp);
+
+ return true;
+}
+
#define GEN_VAFORM_PAIRED(name0, name1, opc2) \
static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
{ \
--
2.34.1
^ permalink raw reply related [flat|nested] 89+ messages in thread* [PULL 22/87] target/ppc: implement vclrrb
2022-03-02 11:06 [PULL 00/87] ppc queue Cédric Le Goater
` (20 preceding siblings ...)
2022-03-02 11:06 ` [PULL 21/87] target/ppc: implement vclrlb Cédric Le Goater
@ 2022-03-02 11:06 ` Cédric Le Goater
2022-03-02 11:06 ` [PULL 23/87] target/ppc: implement vcntmb[bhwd] Cédric Le Goater
` (65 subsequent siblings)
87 siblings, 0 replies; 89+ messages in thread
From: Cédric Le Goater @ 2022-03-02 11:06 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Richard Henderson, Matheus Ferst,
Cédric Le Goater
From: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20220225210936.1749575-17-matheus.ferst@eldorado.org.br>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/insn32.decode | 1 +
target/ppc/translate/vmx-impl.c.inc | 32 +++++++++++++++++++++--------
2 files changed, 25 insertions(+), 8 deletions(-)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 31cdbba86bfb..b20f1eaa8e9c 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -530,6 +530,7 @@ VSTRIHL 000100 ..... 00010 ..... . 0000001101 @VX_tb_rc
VSTRIHR 000100 ..... 00011 ..... . 0000001101 @VX_tb_rc
VCLRLB 000100 ..... ..... ..... 00110001101 @VX
+VCLRRB 000100 ..... ..... ..... 00111001101 @VX
# VSX Load/Store Instructions
diff --git a/target/ppc/translate/vmx-impl.c.inc b/target/ppc/translate/vmx-impl.c.inc
index d43fba00ed43..4db5656669c7 100644
--- a/target/ppc/translate/vmx-impl.c.inc
+++ b/target/ppc/translate/vmx-impl.c.inc
@@ -1940,7 +1940,7 @@ TRANS(VSTRIBR, do_vstri, gen_helper_VSTRIBR)
TRANS(VSTRIHL, do_vstri, gen_helper_VSTRIHL)
TRANS(VSTRIHR, do_vstri, gen_helper_VSTRIHR)
-static bool trans_VCLRLB(DisasContext *ctx, arg_VX *a)
+static bool do_vclrb(DisasContext *ctx, arg_VX *a, bool right)
{
TCGv_i64 rb, mh, ml, tmp,
ones = tcg_constant_i64(-1),
@@ -1954,15 +1954,28 @@ static bool trans_VCLRLB(DisasContext *ctx, arg_VX *a)
tcg_gen_extu_tl_i64(rb, cpu_gpr[a->vrb]);
tcg_gen_andi_i64(tmp, rb, 7);
tcg_gen_shli_i64(tmp, tmp, 3);
- tcg_gen_shl_i64(tmp, ones, tmp);
+ if (right) {
+ tcg_gen_shr_i64(tmp, ones, tmp);
+ } else {
+ tcg_gen_shl_i64(tmp, ones, tmp);
+ }
tcg_gen_not_i64(tmp, tmp);
- tcg_gen_movcond_i64(TCG_COND_LTU, ml, rb, tcg_constant_i64(8),
- tmp, ones);
- tcg_gen_movcond_i64(TCG_COND_LTU, mh, rb, tcg_constant_i64(8),
- zero, tmp);
- tcg_gen_movcond_i64(TCG_COND_LTU, mh, rb, tcg_constant_i64(16),
- mh, ones);
+ if (right) {
+ tcg_gen_movcond_i64(TCG_COND_LTU, mh, rb, tcg_constant_i64(8),
+ tmp, ones);
+ tcg_gen_movcond_i64(TCG_COND_LTU, ml, rb, tcg_constant_i64(8),
+ zero, tmp);
+ tcg_gen_movcond_i64(TCG_COND_LTU, ml, rb, tcg_constant_i64(16),
+ ml, ones);
+ } else {
+ tcg_gen_movcond_i64(TCG_COND_LTU, ml, rb, tcg_constant_i64(8),
+ tmp, ones);
+ tcg_gen_movcond_i64(TCG_COND_LTU, mh, rb, tcg_constant_i64(8),
+ zero, tmp);
+ tcg_gen_movcond_i64(TCG_COND_LTU, mh, rb, tcg_constant_i64(16),
+ mh, ones);
+ }
get_avr64(tmp, a->vra, true);
tcg_gen_and_i64(tmp, tmp, mh);
@@ -1980,6 +1993,9 @@ static bool trans_VCLRLB(DisasContext *ctx, arg_VX *a)
return true;
}
+TRANS(VCLRLB, do_vclrb, false)
+TRANS(VCLRRB, do_vclrb, true)
+
#define GEN_VAFORM_PAIRED(name0, name1, opc2) \
static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
{ \
--
2.34.1
^ permalink raw reply related [flat|nested] 89+ messages in thread* [PULL 23/87] target/ppc: implement vcntmb[bhwd]
2022-03-02 11:06 [PULL 00/87] ppc queue Cédric Le Goater
` (21 preceding siblings ...)
2022-03-02 11:06 ` [PULL 22/87] target/ppc: implement vclrrb Cédric Le Goater
@ 2022-03-02 11:06 ` Cédric Le Goater
2022-03-02 11:07 ` [PULL 24/87] target/ppc: implement vgnb Cédric Le Goater
` (64 subsequent siblings)
87 siblings, 0 replies; 89+ messages in thread
From: Cédric Le Goater @ 2022-03-02 11:06 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Richard Henderson, Matheus Ferst,
Cédric Le Goater
From: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20220225210936.1749575-18-matheus.ferst@eldorado.org.br>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/insn32.decode | 8 ++++++++
target/ppc/translate/vmx-impl.c.inc | 32 +++++++++++++++++++++++++++++
2 files changed, 40 insertions(+)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index b20f1eaa8e9c..31a3c3b5084c 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -63,6 +63,9 @@
&VX_bf bf vra vrb
@VX_bf ...... bf:3 .. vra:5 vrb:5 ........... &VX_bf
+&VX_mp rt mp:bool vrb
+@VX_mp ...... rt:5 .... mp:1 vrb:5 ........... &VX_mp
+
&VX_tb_rc vrt vrb rc:bool
@VX_tb_rc ...... vrt:5 ..... vrb:5 rc:1 .......... &VX_tb_rc
@@ -489,6 +492,11 @@ VEXTRACTWM 000100 ..... 01010 ..... 11001000010 @VX_tb
VEXTRACTDM 000100 ..... 01011 ..... 11001000010 @VX_tb
VEXTRACTQM 000100 ..... 01100 ..... 11001000010 @VX_tb
+VCNTMBB 000100 ..... 1100 . ..... 11001000010 @VX_mp
+VCNTMBH 000100 ..... 1101 . ..... 11001000010 @VX_mp
+VCNTMBW 000100 ..... 1110 . ..... 11001000010 @VX_mp
+VCNTMBD 000100 ..... 1111 . ..... 11001000010 @VX_mp
+
## Vector Multiply Instruction
VMULESB 000100 ..... ..... ..... 01100001000 @VX
diff --git a/target/ppc/translate/vmx-impl.c.inc b/target/ppc/translate/vmx-impl.c.inc
index 4db5656669c7..e45bd194f430 100644
--- a/target/ppc/translate/vmx-impl.c.inc
+++ b/target/ppc/translate/vmx-impl.c.inc
@@ -1910,6 +1910,38 @@ static bool trans_MTVSRBMI(DisasContext *ctx, arg_DX_b *a)
return true;
}
+static bool do_vcntmb(DisasContext *ctx, arg_VX_mp *a, int vece)
+{
+ TCGv_i64 rt, vrb, mask;
+ rt = tcg_const_i64(0);
+ vrb = tcg_temp_new_i64();
+ mask = tcg_constant_i64(dup_const(vece, 1ULL << ((8 << vece) - 1)));
+
+ for (int i = 0; i < 2; i++) {
+ get_avr64(vrb, a->vrb, i);
+ if (a->mp) {
+ tcg_gen_and_i64(vrb, mask, vrb);
+ } else {
+ tcg_gen_andc_i64(vrb, mask, vrb);
+ }
+ tcg_gen_ctpop_i64(vrb, vrb);
+ tcg_gen_add_i64(rt, rt, vrb);
+ }
+
+ tcg_gen_shli_i64(rt, rt, TARGET_LONG_BITS - 8 + vece);
+ tcg_gen_trunc_i64_tl(cpu_gpr[a->rt], rt);
+
+ tcg_temp_free_i64(vrb);
+ tcg_temp_free_i64(rt);
+
+ return true;
+}
+
+TRANS(VCNTMBB, do_vcntmb, MO_8)
+TRANS(VCNTMBH, do_vcntmb, MO_16)
+TRANS(VCNTMBW, do_vcntmb, MO_32)
+TRANS(VCNTMBD, do_vcntmb, MO_64)
+
static bool do_vstri(DisasContext *ctx, arg_VX_tb_rc *a,
void (*gen_helper)(TCGv_i32, TCGv_ptr, TCGv_ptr))
{
--
2.34.1
^ permalink raw reply related [flat|nested] 89+ messages in thread* [PULL 24/87] target/ppc: implement vgnb
2022-03-02 11:06 [PULL 00/87] ppc queue Cédric Le Goater
` (22 preceding siblings ...)
2022-03-02 11:06 ` [PULL 23/87] target/ppc: implement vcntmb[bhwd] Cédric Le Goater
@ 2022-03-02 11:07 ` Cédric Le Goater
2022-03-02 11:07 ` [PULL 25/87] target/ppc: move vs[lr][a][bhwd] to decodetree Cédric Le Goater
` (63 subsequent siblings)
87 siblings, 0 replies; 89+ messages in thread
From: Cédric Le Goater @ 2022-03-02 11:07 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Richard Henderson, Matheus Ferst,
Cédric Le Goater
From: Matheus Ferst <matheus.ferst@eldorado.org.br>
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20220225210936.1749575-19-matheus.ferst@eldorado.org.br>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/insn32.decode | 5 ++
target/ppc/translate/vmx-impl.c.inc | 135 ++++++++++++++++++++++++++++
2 files changed, 140 insertions(+)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 31a3c3b5084c..02df4a98e665 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -66,6 +66,9 @@
&VX_mp rt mp:bool vrb
@VX_mp ...... rt:5 .... mp:1 vrb:5 ........... &VX_mp
+&VX_n rt vrb n
+@VX_n ...... rt:5 .. n:3 vrb:5 ........... &VX_n
+
&VX_tb_rc vrt vrb rc:bool
@VX_tb_rc ...... vrt:5 ..... vrb:5 rc:1 .......... &VX_tb_rc
@@ -418,6 +421,8 @@ VCMPUQ 000100 ... -- ..... ..... 00100000001 @VX_bf
## Vector Bit Manipulation Instruction
+VGNB 000100 ..... -- ... ..... 10011001100 @VX_n
+
VCFUGED 000100 ..... ..... ..... 10101001101 @VX
VCLZDM 000100 ..... ..... ..... 11110000100 @VX
VCTZDM 000100 ..... ..... ..... 11111000100 @VX
diff --git a/target/ppc/translate/vmx-impl.c.inc b/target/ppc/translate/vmx-impl.c.inc
index e45bd194f430..52774cdd4dfb 100644
--- a/target/ppc/translate/vmx-impl.c.inc
+++ b/target/ppc/translate/vmx-impl.c.inc
@@ -1416,6 +1416,141 @@ GEN_VXFORM_DUAL(vsplth, PPC_ALTIVEC, PPC_NONE,
GEN_VXFORM_DUAL(vspltw, PPC_ALTIVEC, PPC_NONE,
vextractuw, PPC_NONE, PPC2_ISA300);
+static bool trans_VGNB(DisasContext *ctx, arg_VX_n *a)
+{
+ /*
+ * Similar to do_vextractm, we'll use a sequence of mask-shift-or operations
+ * to gather the bits. The masks can be created with
+ *
+ * uint64_t mask(uint64_t n, uint64_t step)
+ * {
+ * uint64_t p = ((1UL << (1UL << step)) - 1UL) << ((n - 1UL) << step),
+ * plen = n << step, m = 0;
+ * for(int i = 0; i < 64/plen; i++) {
+ * m |= p;
+ * m = ror64(m, plen);
+ * }
+ * p >>= plen * DIV_ROUND_UP(64, plen) - 64;
+ * return m | p;
+ * }
+ *
+ * But since there are few values of N, we'll use a lookup table to avoid
+ * these calculations at runtime.
+ */
+ static const uint64_t mask[6][5] = {
+ {
+ 0xAAAAAAAAAAAAAAAAULL, 0xccccccccccccccccULL, 0xf0f0f0f0f0f0f0f0ULL,
+ 0xff00ff00ff00ff00ULL, 0xffff0000ffff0000ULL
+ },
+ {
+ 0x9249249249249249ULL, 0xC30C30C30C30C30CULL, 0xF00F00F00F00F00FULL,
+ 0xFF0000FF0000FF00ULL, 0xFFFF00000000FFFFULL
+ },
+ {
+ /* For N >= 4, some mask operations can be elided */
+ 0x8888888888888888ULL, 0, 0xf000f000f000f000ULL, 0,
+ 0xFFFF000000000000ULL
+ },
+ {
+ 0x8421084210842108ULL, 0, 0xF0000F0000F0000FULL, 0, 0
+ },
+ {
+ 0x8208208208208208ULL, 0, 0xF00000F00000F000ULL, 0, 0
+ },
+ {
+ 0x8102040810204081ULL, 0, 0xF000000F000000F0ULL, 0, 0
+ }
+ };
+ uint64_t m;
+ int i, sh, nbits = DIV_ROUND_UP(64, a->n);
+ TCGv_i64 hi, lo, t0, t1;
+
+ REQUIRE_INSNS_FLAGS2(ctx, ISA310);
+ REQUIRE_VECTOR(ctx);
+
+ if (a->n < 2) {
+ /*
+ * "N can be any value between 2 and 7, inclusive." Otherwise, the
+ * result is undefined, so we don't need to change RT. Also, N > 7 is
+ * impossible since the immediate field is 3 bits only.
+ */
+ return true;
+ }
+
+ hi = tcg_temp_new_i64();
+ lo = tcg_temp_new_i64();
+ t0 = tcg_temp_new_i64();
+ t1 = tcg_temp_new_i64();
+
+ get_avr64(hi, a->vrb, true);
+ get_avr64(lo, a->vrb, false);
+
+ /* Align the lower doubleword so we can use the same mask */
+ tcg_gen_shli_i64(lo, lo, a->n * nbits - 64);
+
+ /*
+ * Starting from the most significant bit, gather every Nth bit with a
+ * sequence of mask-shift-or operation. E.g.: for N=3
+ * AxxBxxCxxDxxExxFxxGxxHxxIxxJxxKxxLxxMxxNxxOxxPxxQxxRxxSxxTxxUxxV
+ * & rep(0b100)
+ * A..B..C..D..E..F..G..H..I..J..K..L..M..N..O..P..Q..R..S..T..U..V
+ * << 2
+ * .B..C..D..E..F..G..H..I..J..K..L..M..N..O..P..Q..R..S..T..U..V..
+ * |
+ * AB.BC.CD.DE.EF.FG.GH.HI.IJ.JK.KL.LM.MN.NO.OP.PQ.QR.RS.ST.TU.UV.V
+ * & rep(0b110000)
+ * AB....CD....EF....GH....IJ....KL....MN....OP....QR....ST....UV..
+ * << 4
+ * ..CD....EF....GH....IJ....KL....MN....OP....QR....ST....UV......
+ * |
+ * ABCD..CDEF..EFGH..GHIJ..IJKL..KLMN..MNOP..OPQR..QRST..STUV..UV..
+ * & rep(0b111100000000)
+ * ABCD........EFGH........IJKL........MNOP........QRST........UV..
+ * << 8
+ * ....EFGH........IJKL........MNOP........QRST........UV..........
+ * |
+ * ABCDEFGH....EFGHIJKL....IJKLMNOP....MNOPQRST....QRSTUV......UV..
+ * & rep(0b111111110000000000000000)
+ * ABCDEFGH................IJKLMNOP................QRSTUV..........
+ * << 16
+ * ........IJKLMNOP................QRSTUV..........................
+ * |
+ * ABCDEFGHIJKLMNOP........IJKLMNOPQRSTUV..........QRSTUV..........
+ * & rep(0b111111111111111100000000000000000000000000000000)
+ * ABCDEFGHIJKLMNOP................................QRSTUV..........
+ * << 32
+ * ................QRSTUV..........................................
+ * |
+ * ABCDEFGHIJKLMNOPQRSTUV..........................QRSTUV..........
+ */
+ for (i = 0, sh = a->n - 1; i < 5; i++, sh <<= 1) {
+ m = mask[a->n - 2][i];
+ if (m) {
+ tcg_gen_andi_i64(hi, hi, m);
+ tcg_gen_andi_i64(lo, lo, m);
+ }
+ if (sh < 64) {
+ tcg_gen_shli_i64(t0, hi, sh);
+ tcg_gen_shli_i64(t1, lo, sh);
+ tcg_gen_or_i64(hi, t0, hi);
+ tcg_gen_or_i64(lo, t1, lo);
+ }
+ }
+
+ tcg_gen_andi_i64(hi, hi, ~(~0ULL >> nbits));
+ tcg_gen_andi_i64(lo, lo, ~(~0ULL >> nbits));
+ tcg_gen_shri_i64(lo, lo, nbits);
+ tcg_gen_or_i64(hi, hi, lo);
+ tcg_gen_trunc_i64_tl(cpu_gpr[a->rt], hi);
+
+ tcg_temp_free_i64(hi);
+ tcg_temp_free_i64(lo);
+ tcg_temp_free_i64(t0);
+ tcg_temp_free_i64(t1);
+
+ return true;
+}
+
static bool do_vextdx(DisasContext *ctx, arg_VA *a, int size, bool right,
void (*gen_helper)(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv))
{
--
2.34.1
^ permalink raw reply related [flat|nested] 89+ messages in thread* [PULL 25/87] target/ppc: move vs[lr][a][bhwd] to decodetree
2022-03-02 11:06 [PULL 00/87] ppc queue Cédric Le Goater
` (23 preceding siblings ...)
2022-03-02 11:07 ` [PULL 24/87] target/ppc: implement vgnb Cédric Le Goater
@ 2022-03-02 11:07 ` Cédric Le Goater
2022-03-02 11:07 ` [PULL 26/87] target/ppc: implement vslq Cédric Le Goater
` (62 subsequent siblings)
87 siblings, 0 replies; 89+ messages in thread
From: Cédric Le Goater @ 2022-03-02 11:07 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Richard Henderson, Matheus Ferst,
Cédric Le Goater
From: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20220225210936.1749575-20-matheus.ferst@eldorado.org.br>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/insn32.decode | 17 ++++++++++++
target/ppc/translate/vmx-impl.c.inc | 41 +++++++++++++++++++----------
target/ppc/translate/vmx-ops.c.inc | 13 +--------
3 files changed, 45 insertions(+), 26 deletions(-)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 02df4a98e665..88baebe35e4c 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -467,6 +467,23 @@ VINSWVRX 000100 ..... ..... ..... 00110001111 @VX
VSLDBI 000100 ..... ..... ..... 00 ... 010110 @VN
VSRDBI 000100 ..... ..... ..... 01 ... 010110 @VN
+## Vector Integer Shift Instruction
+
+VSLB 000100 ..... ..... ..... 00100000100 @VX
+VSLH 000100 ..... ..... ..... 00101000100 @VX
+VSLW 000100 ..... ..... ..... 00110000100 @VX
+VSLD 000100 ..... ..... ..... 10111000100 @VX
+
+VSRB 000100 ..... ..... ..... 01000000100 @VX
+VSRH 000100 ..... ..... ..... 01001000100 @VX
+VSRW 000100 ..... ..... ..... 01010000100 @VX
+VSRD 000100 ..... ..... ..... 11011000100 @VX
+
+VSRAB 000100 ..... ..... ..... 01100000100 @VX
+VSRAH 000100 ..... ..... ..... 01101000100 @VX
+VSRAW 000100 ..... ..... ..... 01110000100 @VX
+VSRAD 000100 ..... ..... ..... 01111000100 @VX
+
## Vector Integer Arithmetic Instructions
VEXTSB2W 000100 ..... 10000 ..... 11000000010 @VX_tb
diff --git a/target/ppc/translate/vmx-impl.c.inc b/target/ppc/translate/vmx-impl.c.inc
index 52774cdd4dfb..1b05b0b3a35e 100644
--- a/target/ppc/translate/vmx-impl.c.inc
+++ b/target/ppc/translate/vmx-impl.c.inc
@@ -799,21 +799,7 @@ static void trans_vclzd(DisasContext *ctx)
}
GEN_VXFORM_V(vmuluwm, MO_32, tcg_gen_gvec_mul, 4, 2);
-GEN_VXFORM_V(vslb, MO_8, tcg_gen_gvec_shlv, 2, 4);
-GEN_VXFORM_V(vslh, MO_16, tcg_gen_gvec_shlv, 2, 5);
-GEN_VXFORM_V(vslw, MO_32, tcg_gen_gvec_shlv, 2, 6);
GEN_VXFORM(vrlwnm, 2, 6);
-GEN_VXFORM_DUAL(vslw, PPC_ALTIVEC, PPC_NONE, \
- vrlwnm, PPC_NONE, PPC2_ISA300)
-GEN_VXFORM_V(vsld, MO_64, tcg_gen_gvec_shlv, 2, 23);
-GEN_VXFORM_V(vsrb, MO_8, tcg_gen_gvec_shrv, 2, 8);
-GEN_VXFORM_V(vsrh, MO_16, tcg_gen_gvec_shrv, 2, 9);
-GEN_VXFORM_V(vsrw, MO_32, tcg_gen_gvec_shrv, 2, 10);
-GEN_VXFORM_V(vsrd, MO_64, tcg_gen_gvec_shrv, 2, 27);
-GEN_VXFORM_V(vsrab, MO_8, tcg_gen_gvec_sarv, 2, 12);
-GEN_VXFORM_V(vsrah, MO_16, tcg_gen_gvec_sarv, 2, 13);
-GEN_VXFORM_V(vsraw, MO_32, tcg_gen_gvec_sarv, 2, 14);
-GEN_VXFORM_V(vsrad, MO_64, tcg_gen_gvec_sarv, 2, 15);
GEN_VXFORM(vsrv, 2, 28);
GEN_VXFORM(vslv, 2, 29);
GEN_VXFORM(vslo, 6, 16);
@@ -821,6 +807,33 @@ GEN_VXFORM(vsro, 6, 17);
GEN_VXFORM(vaddcuw, 0, 6);
GEN_VXFORM(vsubcuw, 0, 22);
+static bool do_vector_gvec3_VX(DisasContext *ctx, arg_VX *a, int vece,
+ void (*gen_gvec)(unsigned, uint32_t, uint32_t,
+ uint32_t, uint32_t, uint32_t))
+{
+ REQUIRE_VECTOR(ctx);
+
+ gen_gvec(vece, avr_full_offset(a->vrt), avr_full_offset(a->vra),
+ avr_full_offset(a->vrb), 16, 16);
+
+ return true;
+}
+
+TRANS_FLAGS(ALTIVEC, VSLB, do_vector_gvec3_VX, MO_8, tcg_gen_gvec_shlv);
+TRANS_FLAGS(ALTIVEC, VSLH, do_vector_gvec3_VX, MO_16, tcg_gen_gvec_shlv);
+TRANS_FLAGS(ALTIVEC, VSLW, do_vector_gvec3_VX, MO_32, tcg_gen_gvec_shlv);
+TRANS_FLAGS2(ALTIVEC_207, VSLD, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_shlv);
+
+TRANS_FLAGS(ALTIVEC, VSRB, do_vector_gvec3_VX, MO_8, tcg_gen_gvec_shrv);
+TRANS_FLAGS(ALTIVEC, VSRH, do_vector_gvec3_VX, MO_16, tcg_gen_gvec_shrv);
+TRANS_FLAGS(ALTIVEC, VSRW, do_vector_gvec3_VX, MO_32, tcg_gen_gvec_shrv);
+TRANS_FLAGS2(ALTIVEC_207, VSRD, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_shrv);
+
+TRANS_FLAGS(ALTIVEC, VSRAB, do_vector_gvec3_VX, MO_8, tcg_gen_gvec_sarv);
+TRANS_FLAGS(ALTIVEC, VSRAH, do_vector_gvec3_VX, MO_16, tcg_gen_gvec_sarv);
+TRANS_FLAGS(ALTIVEC, VSRAW, do_vector_gvec3_VX, MO_32, tcg_gen_gvec_sarv);
+TRANS_FLAGS2(ALTIVEC_207, VSRAD, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_sarv);
+
#define GEN_VXFORM_SAT(NAME, VECE, NORM, SAT, OPC2, OPC3) \
static void glue(glue(gen_, NAME), _vec)(unsigned vece, TCGv_vec t, \
TCGv_vec sat, TCGv_vec a, \
diff --git a/target/ppc/translate/vmx-ops.c.inc b/target/ppc/translate/vmx-ops.c.inc
index cb4c5bb953c1..878bce92c6a4 100644
--- a/target/ppc/translate/vmx-ops.c.inc
+++ b/target/ppc/translate/vmx-ops.c.inc
@@ -102,18 +102,7 @@ GEN_VXFORM_300(vextubrx, 6, 28),
GEN_VXFORM_300(vextuhrx, 6, 29),
GEN_VXFORM_DUAL(vmrgew, vextuwrx, 6, 30, PPC_NONE, PPC2_ALTIVEC_207),
GEN_VXFORM_207(vmuluwm, 4, 2),
-GEN_VXFORM(vslb, 2, 4),
-GEN_VXFORM(vslh, 2, 5),
-GEN_VXFORM_DUAL(vslw, vrlwnm, 2, 6, PPC_ALTIVEC, PPC_NONE),
-GEN_VXFORM_207(vsld, 2, 23),
-GEN_VXFORM(vsrb, 2, 8),
-GEN_VXFORM(vsrh, 2, 9),
-GEN_VXFORM(vsrw, 2, 10),
-GEN_VXFORM_207(vsrd, 2, 27),
-GEN_VXFORM(vsrab, 2, 12),
-GEN_VXFORM(vsrah, 2, 13),
-GEN_VXFORM(vsraw, 2, 14),
-GEN_VXFORM_207(vsrad, 2, 15),
+GEN_VXFORM_300(vrlwnm, 2, 6),
GEN_VXFORM_300(vsrv, 2, 28),
GEN_VXFORM_300(vslv, 2, 29),
GEN_VXFORM(vslo, 6, 16),
--
2.34.1
^ permalink raw reply related [flat|nested] 89+ messages in thread* [PULL 26/87] target/ppc: implement vslq
2022-03-02 11:06 [PULL 00/87] ppc queue Cédric Le Goater
` (24 preceding siblings ...)
2022-03-02 11:07 ` [PULL 25/87] target/ppc: move vs[lr][a][bhwd] to decodetree Cédric Le Goater
@ 2022-03-02 11:07 ` Cédric Le Goater
2022-03-02 11:07 ` [PULL 27/87] target/ppc: implement vsrq Cédric Le Goater
` (61 subsequent siblings)
87 siblings, 0 replies; 89+ messages in thread
From: Cédric Le Goater @ 2022-03-02 11:07 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Richard Henderson, Matheus Ferst,
Cédric Le Goater
From: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20220225210936.1749575-21-matheus.ferst@eldorado.org.br>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/insn32.decode | 1 +
target/ppc/translate/vmx-impl.c.inc | 40 +++++++++++++++++++++++++++++
2 files changed, 41 insertions(+)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 88baebe35e4c..379906550877 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -473,6 +473,7 @@ VSLB 000100 ..... ..... ..... 00100000100 @VX
VSLH 000100 ..... ..... ..... 00101000100 @VX
VSLW 000100 ..... ..... ..... 00110000100 @VX
VSLD 000100 ..... ..... ..... 10111000100 @VX
+VSLQ 000100 ..... ..... ..... 00100000101 @VX
VSRB 000100 ..... ..... ..... 01000000100 @VX
VSRH 000100 ..... ..... ..... 01001000100 @VX
diff --git a/target/ppc/translate/vmx-impl.c.inc b/target/ppc/translate/vmx-impl.c.inc
index 1b05b0b3a35e..49c722e8625c 100644
--- a/target/ppc/translate/vmx-impl.c.inc
+++ b/target/ppc/translate/vmx-impl.c.inc
@@ -834,6 +834,46 @@ TRANS_FLAGS(ALTIVEC, VSRAH, do_vector_gvec3_VX, MO_16, tcg_gen_gvec_sarv);
TRANS_FLAGS(ALTIVEC, VSRAW, do_vector_gvec3_VX, MO_32, tcg_gen_gvec_sarv);
TRANS_FLAGS2(ALTIVEC_207, VSRAD, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_sarv);
+static bool trans_VSLQ(DisasContext *ctx, arg_VX *a)
+{
+ TCGv_i64 hi, lo, t0, n, zero = tcg_constant_i64(0);
+
+ REQUIRE_INSNS_FLAGS2(ctx, ISA310);
+ REQUIRE_VECTOR(ctx);
+
+ n = tcg_temp_new_i64();
+ hi = tcg_temp_new_i64();
+ lo = tcg_temp_new_i64();
+ t0 = tcg_temp_new_i64();
+
+ get_avr64(lo, a->vra, false);
+ get_avr64(hi, a->vra, true);
+
+ get_avr64(n, a->vrb, true);
+
+ tcg_gen_andi_i64(t0, n, 64);
+ tcg_gen_movcond_i64(TCG_COND_NE, hi, t0, zero, lo, hi);
+ tcg_gen_movcond_i64(TCG_COND_NE, lo, t0, zero, zero, lo);
+ tcg_gen_andi_i64(n, n, 0x3F);
+
+ tcg_gen_shl_i64(t0, lo, n);
+ set_avr64(a->vrt, t0, false);
+
+ tcg_gen_shl_i64(hi, hi, n);
+ tcg_gen_xori_i64(n, n, 63);
+ tcg_gen_shr_i64(lo, lo, n);
+ tcg_gen_shri_i64(lo, lo, 1);
+ tcg_gen_or_i64(hi, hi, lo);
+ set_avr64(a->vrt, hi, true);
+
+ tcg_temp_free_i64(hi);
+ tcg_temp_free_i64(lo);
+ tcg_temp_free_i64(t0);
+ tcg_temp_free_i64(n);
+
+ return true;
+}
+
#define GEN_VXFORM_SAT(NAME, VECE, NORM, SAT, OPC2, OPC3) \
static void glue(glue(gen_, NAME), _vec)(unsigned vece, TCGv_vec t, \
TCGv_vec sat, TCGv_vec a, \
--
2.34.1
^ permalink raw reply related [flat|nested] 89+ messages in thread* [PULL 27/87] target/ppc: implement vsrq
2022-03-02 11:06 [PULL 00/87] ppc queue Cédric Le Goater
` (25 preceding siblings ...)
2022-03-02 11:07 ` [PULL 26/87] target/ppc: implement vslq Cédric Le Goater
@ 2022-03-02 11:07 ` Cédric Le Goater
2022-03-02 11:07 ` [PULL 28/87] target/ppc: implement vsraq Cédric Le Goater
` (60 subsequent siblings)
87 siblings, 0 replies; 89+ messages in thread
From: Cédric Le Goater @ 2022-03-02 11:07 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Richard Henderson, Matheus Ferst,
Cédric Le Goater
From: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20220225210936.1749575-22-matheus.ferst@eldorado.org.br>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/insn32.decode | 1 +
target/ppc/translate/vmx-impl.c.inc | 40 +++++++++++++++++++++--------
2 files changed, 31 insertions(+), 10 deletions(-)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 379906550877..96ee73024218 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -479,6 +479,7 @@ VSRB 000100 ..... ..... ..... 01000000100 @VX
VSRH 000100 ..... ..... ..... 01001000100 @VX
VSRW 000100 ..... ..... ..... 01010000100 @VX
VSRD 000100 ..... ..... ..... 11011000100 @VX
+VSRQ 000100 ..... ..... ..... 01000000101 @VX
VSRAB 000100 ..... ..... ..... 01100000100 @VX
VSRAH 000100 ..... ..... ..... 01101000100 @VX
diff --git a/target/ppc/translate/vmx-impl.c.inc b/target/ppc/translate/vmx-impl.c.inc
index 49c722e8625c..8a1e64d7f2e0 100644
--- a/target/ppc/translate/vmx-impl.c.inc
+++ b/target/ppc/translate/vmx-impl.c.inc
@@ -834,11 +834,10 @@ TRANS_FLAGS(ALTIVEC, VSRAH, do_vector_gvec3_VX, MO_16, tcg_gen_gvec_sarv);
TRANS_FLAGS(ALTIVEC, VSRAW, do_vector_gvec3_VX, MO_32, tcg_gen_gvec_sarv);
TRANS_FLAGS2(ALTIVEC_207, VSRAD, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_sarv);
-static bool trans_VSLQ(DisasContext *ctx, arg_VX *a)
+static bool do_vector_shift_quad(DisasContext *ctx, arg_VX *a, bool right)
{
TCGv_i64 hi, lo, t0, n, zero = tcg_constant_i64(0);
- REQUIRE_INSNS_FLAGS2(ctx, ISA310);
REQUIRE_VECTOR(ctx);
n = tcg_temp_new_i64();
@@ -852,19 +851,37 @@ static bool trans_VSLQ(DisasContext *ctx, arg_VX *a)
get_avr64(n, a->vrb, true);
tcg_gen_andi_i64(t0, n, 64);
- tcg_gen_movcond_i64(TCG_COND_NE, hi, t0, zero, lo, hi);
- tcg_gen_movcond_i64(TCG_COND_NE, lo, t0, zero, zero, lo);
+ if (right) {
+ tcg_gen_movcond_i64(TCG_COND_NE, lo, t0, zero, hi, lo);
+ tcg_gen_movcond_i64(TCG_COND_NE, hi, t0, zero, zero, hi);
+ } else {
+ tcg_gen_movcond_i64(TCG_COND_NE, hi, t0, zero, lo, hi);
+ tcg_gen_movcond_i64(TCG_COND_NE, lo, t0, zero, zero, lo);
+ }
tcg_gen_andi_i64(n, n, 0x3F);
- tcg_gen_shl_i64(t0, lo, n);
- set_avr64(a->vrt, t0, false);
+ if (right) {
+ tcg_gen_shr_i64(t0, hi, n);
+ } else {
+ tcg_gen_shl_i64(t0, lo, n);
+ }
+ set_avr64(a->vrt, t0, right);
- tcg_gen_shl_i64(hi, hi, n);
+ if (right) {
+ tcg_gen_shr_i64(lo, lo, n);
+ } else {
+ tcg_gen_shl_i64(hi, hi, n);
+ }
tcg_gen_xori_i64(n, n, 63);
- tcg_gen_shr_i64(lo, lo, n);
- tcg_gen_shri_i64(lo, lo, 1);
+ if (right) {
+ tcg_gen_shl_i64(hi, hi, n);
+ tcg_gen_shli_i64(hi, hi, 1);
+ } else {
+ tcg_gen_shr_i64(lo, lo, n);
+ tcg_gen_shri_i64(lo, lo, 1);
+ }
tcg_gen_or_i64(hi, hi, lo);
- set_avr64(a->vrt, hi, true);
+ set_avr64(a->vrt, hi, !right);
tcg_temp_free_i64(hi);
tcg_temp_free_i64(lo);
@@ -874,6 +891,9 @@ static bool trans_VSLQ(DisasContext *ctx, arg_VX *a)
return true;
}
+TRANS_FLAGS2(ISA310, VSLQ, do_vector_shift_quad, false);
+TRANS_FLAGS2(ISA310, VSRQ, do_vector_shift_quad, true);
+
#define GEN_VXFORM_SAT(NAME, VECE, NORM, SAT, OPC2, OPC3) \
static void glue(glue(gen_, NAME), _vec)(unsigned vece, TCGv_vec t, \
TCGv_vec sat, TCGv_vec a, \
--
2.34.1
^ permalink raw reply related [flat|nested] 89+ messages in thread* [PULL 28/87] target/ppc: implement vsraq
2022-03-02 11:06 [PULL 00/87] ppc queue Cédric Le Goater
` (26 preceding siblings ...)
2022-03-02 11:07 ` [PULL 27/87] target/ppc: implement vsrq Cédric Le Goater
@ 2022-03-02 11:07 ` Cédric Le Goater
2022-03-02 11:07 ` [PULL 29/87] target/ppc: move vrl[bhwd] to decodetree Cédric Le Goater
` (59 subsequent siblings)
87 siblings, 0 replies; 89+ messages in thread
From: Cédric Le Goater @ 2022-03-02 11:07 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Richard Henderson, Matheus Ferst,
Cédric Le Goater
From: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20220225210936.1749575-23-matheus.ferst@eldorado.org.br>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/insn32.decode | 1 +
target/ppc/translate/vmx-impl.c.inc | 23 +++++++++++++++++------
2 files changed, 18 insertions(+), 6 deletions(-)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 96ee73024218..7a9fc1dffa38 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -485,6 +485,7 @@ VSRAB 000100 ..... ..... ..... 01100000100 @VX
VSRAH 000100 ..... ..... ..... 01101000100 @VX
VSRAW 000100 ..... ..... ..... 01110000100 @VX
VSRAD 000100 ..... ..... ..... 01111000100 @VX
+VSRAQ 000100 ..... ..... ..... 01100000101 @VX
## Vector Integer Arithmetic Instructions
diff --git a/target/ppc/translate/vmx-impl.c.inc b/target/ppc/translate/vmx-impl.c.inc
index 8a1e64d7f2e0..27ed87fcd6db 100644
--- a/target/ppc/translate/vmx-impl.c.inc
+++ b/target/ppc/translate/vmx-impl.c.inc
@@ -834,9 +834,10 @@ TRANS_FLAGS(ALTIVEC, VSRAH, do_vector_gvec3_VX, MO_16, tcg_gen_gvec_sarv);
TRANS_FLAGS(ALTIVEC, VSRAW, do_vector_gvec3_VX, MO_32, tcg_gen_gvec_sarv);
TRANS_FLAGS2(ALTIVEC_207, VSRAD, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_sarv);
-static bool do_vector_shift_quad(DisasContext *ctx, arg_VX *a, bool right)
+static bool do_vector_shift_quad(DisasContext *ctx, arg_VX *a, bool right,
+ bool alg)
{
- TCGv_i64 hi, lo, t0, n, zero = tcg_constant_i64(0);
+ TCGv_i64 hi, lo, t0, t1, n, zero = tcg_constant_i64(0);
REQUIRE_VECTOR(ctx);
@@ -844,6 +845,7 @@ static bool do_vector_shift_quad(DisasContext *ctx, arg_VX *a, bool right)
hi = tcg_temp_new_i64();
lo = tcg_temp_new_i64();
t0 = tcg_temp_new_i64();
+ t1 = tcg_const_i64(0);
get_avr64(lo, a->vra, false);
get_avr64(hi, a->vra, true);
@@ -853,7 +855,10 @@ static bool do_vector_shift_quad(DisasContext *ctx, arg_VX *a, bool right)
tcg_gen_andi_i64(t0, n, 64);
if (right) {
tcg_gen_movcond_i64(TCG_COND_NE, lo, t0, zero, hi, lo);
- tcg_gen_movcond_i64(TCG_COND_NE, hi, t0, zero, zero, hi);
+ if (alg) {
+ tcg_gen_sari_i64(t1, lo, 63);
+ }
+ tcg_gen_movcond_i64(TCG_COND_NE, hi, t0, zero, t1, hi);
} else {
tcg_gen_movcond_i64(TCG_COND_NE, hi, t0, zero, lo, hi);
tcg_gen_movcond_i64(TCG_COND_NE, lo, t0, zero, zero, lo);
@@ -861,7 +866,11 @@ static bool do_vector_shift_quad(DisasContext *ctx, arg_VX *a, bool right)
tcg_gen_andi_i64(n, n, 0x3F);
if (right) {
- tcg_gen_shr_i64(t0, hi, n);
+ if (alg) {
+ tcg_gen_sar_i64(t0, hi, n);
+ } else {
+ tcg_gen_shr_i64(t0, hi, n);
+ }
} else {
tcg_gen_shl_i64(t0, lo, n);
}
@@ -886,13 +895,15 @@ static bool do_vector_shift_quad(DisasContext *ctx, arg_VX *a, bool right)
tcg_temp_free_i64(hi);
tcg_temp_free_i64(lo);
tcg_temp_free_i64(t0);
+ tcg_temp_free_i64(t1);
tcg_temp_free_i64(n);
return true;
}
-TRANS_FLAGS2(ISA310, VSLQ, do_vector_shift_quad, false);
-TRANS_FLAGS2(ISA310, VSRQ, do_vector_shift_quad, true);
+TRANS_FLAGS2(ISA310, VSLQ, do_vector_shift_quad, false, false);
+TRANS_FLAGS2(ISA310, VSRQ, do_vector_shift_quad, true, false);
+TRANS_FLAGS2(ISA310, VSRAQ, do_vector_shift_quad, true, true);
#define GEN_VXFORM_SAT(NAME, VECE, NORM, SAT, OPC2, OPC3) \
static void glue(glue(gen_, NAME), _vec)(unsigned vece, TCGv_vec t, \
--
2.34.1
^ permalink raw reply related [flat|nested] 89+ messages in thread* [PULL 29/87] target/ppc: move vrl[bhwd] to decodetree
2022-03-02 11:06 [PULL 00/87] ppc queue Cédric Le Goater
` (27 preceding siblings ...)
2022-03-02 11:07 ` [PULL 28/87] target/ppc: implement vsraq Cédric Le Goater
@ 2022-03-02 11:07 ` Cédric Le Goater
2022-03-02 11:07 ` [PULL 30/87] target/ppc: move vrl[bhwd]nm/vrl[bhwd]mi " Cédric Le Goater
` (58 subsequent siblings)
87 siblings, 0 replies; 89+ messages in thread
From: Cédric Le Goater @ 2022-03-02 11:07 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Richard Henderson, Matheus Ferst,
Cédric Le Goater
From: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20220225210936.1749575-24-matheus.ferst@eldorado.org.br>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/insn32.decode | 5 +++++
target/ppc/translate/vmx-impl.c.inc | 13 +++++--------
target/ppc/translate/vmx-ops.c.inc | 6 ++----
3 files changed, 12 insertions(+), 12 deletions(-)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 7a9fc1dffa38..d918e2d0f29f 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -487,6 +487,11 @@ VSRAW 000100 ..... ..... ..... 01110000100 @VX
VSRAD 000100 ..... ..... ..... 01111000100 @VX
VSRAQ 000100 ..... ..... ..... 01100000101 @VX
+VRLB 000100 ..... ..... ..... 00000000100 @VX
+VRLH 000100 ..... ..... ..... 00001000100 @VX
+VRLW 000100 ..... ..... ..... 00010000100 @VX
+VRLD 000100 ..... ..... ..... 00011000100 @VX
+
## Vector Integer Arithmetic Instructions
VEXTSB2W 000100 ..... 10000 ..... 11000000010 @VX_tb
diff --git a/target/ppc/translate/vmx-impl.c.inc b/target/ppc/translate/vmx-impl.c.inc
index 27ed87fcd6db..f24b78d42efc 100644
--- a/target/ppc/translate/vmx-impl.c.inc
+++ b/target/ppc/translate/vmx-impl.c.inc
@@ -834,6 +834,11 @@ TRANS_FLAGS(ALTIVEC, VSRAH, do_vector_gvec3_VX, MO_16, tcg_gen_gvec_sarv);
TRANS_FLAGS(ALTIVEC, VSRAW, do_vector_gvec3_VX, MO_32, tcg_gen_gvec_sarv);
TRANS_FLAGS2(ALTIVEC_207, VSRAD, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_sarv);
+TRANS_FLAGS(ALTIVEC, VRLB, do_vector_gvec3_VX, MO_8, tcg_gen_gvec_rotlv)
+TRANS_FLAGS(ALTIVEC, VRLH, do_vector_gvec3_VX, MO_16, tcg_gen_gvec_rotlv)
+TRANS_FLAGS(ALTIVEC, VRLW, do_vector_gvec3_VX, MO_32, tcg_gen_gvec_rotlv)
+TRANS_FLAGS2(ALTIVEC_207, VRLD, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_rotlv)
+
static bool do_vector_shift_quad(DisasContext *ctx, arg_VX *a, bool right,
bool alg)
{
@@ -970,16 +975,8 @@ GEN_VXFORM3(vsubeuqm, 31, 0);
GEN_VXFORM3(vsubecuq, 31, 0);
GEN_VXFORM_DUAL(vsubeuqm, PPC_NONE, PPC2_ALTIVEC_207, \
vsubecuq, PPC_NONE, PPC2_ALTIVEC_207)
-GEN_VXFORM_V(vrlb, MO_8, tcg_gen_gvec_rotlv, 2, 0);
-GEN_VXFORM_V(vrlh, MO_16, tcg_gen_gvec_rotlv, 2, 1);
-GEN_VXFORM_V(vrlw, MO_32, tcg_gen_gvec_rotlv, 2, 2);
GEN_VXFORM(vrlwmi, 2, 2);
-GEN_VXFORM_DUAL(vrlw, PPC_ALTIVEC, PPC_NONE, \
- vrlwmi, PPC_NONE, PPC2_ISA300)
-GEN_VXFORM_V(vrld, MO_64, tcg_gen_gvec_rotlv, 2, 3);
GEN_VXFORM(vrldmi, 2, 3);
-GEN_VXFORM_DUAL(vrld, PPC_NONE, PPC2_ALTIVEC_207, \
- vrldmi, PPC_NONE, PPC2_ISA300)
GEN_VXFORM_TRANS(vsl, 2, 7);
GEN_VXFORM(vrldnm, 2, 7);
GEN_VXFORM_DUAL(vsl, PPC_ALTIVEC, PPC_NONE, \
diff --git a/target/ppc/translate/vmx-ops.c.inc b/target/ppc/translate/vmx-ops.c.inc
index 878bce92c6a4..a7acea3ca78e 100644
--- a/target/ppc/translate/vmx-ops.c.inc
+++ b/target/ppc/translate/vmx-ops.c.inc
@@ -133,10 +133,8 @@ GEN_VXFORM_DUAL(vaddeuqm, vaddecuq, 30, 0xFF, PPC_NONE, PPC2_ALTIVEC_207),
GEN_VXFORM_DUAL(vsubuqm, bcdtrunc, 0, 20, PPC2_ALTIVEC_207, PPC2_ISA300),
GEN_VXFORM_DUAL(vsubcuq, bcdutrunc, 0, 21, PPC2_ALTIVEC_207, PPC2_ISA300),
GEN_VXFORM_DUAL(vsubeuqm, vsubecuq, 31, 0xFF, PPC_NONE, PPC2_ALTIVEC_207),
-GEN_VXFORM(vrlb, 2, 0),
-GEN_VXFORM(vrlh, 2, 1),
-GEN_VXFORM_DUAL(vrlw, vrlwmi, 2, 2, PPC_ALTIVEC, PPC_NONE),
-GEN_VXFORM_DUAL(vrld, vrldmi, 2, 3, PPC_NONE, PPC2_ALTIVEC_207),
+GEN_VXFORM_300(vrlwmi, 2, 2),
+GEN_VXFORM_300(vrldmi, 2, 3),
GEN_VXFORM_DUAL(vsl, vrldnm, 2, 7, PPC_ALTIVEC, PPC_NONE),
GEN_VXFORM(vsr, 2, 11),
GEN_VXFORM(vpkuhum, 7, 0),
--
2.34.1
^ permalink raw reply related [flat|nested] 89+ messages in thread* [PULL 30/87] target/ppc: move vrl[bhwd]nm/vrl[bhwd]mi to decodetree
2022-03-02 11:06 [PULL 00/87] ppc queue Cédric Le Goater
` (28 preceding siblings ...)
2022-03-02 11:07 ` [PULL 29/87] target/ppc: move vrl[bhwd] to decodetree Cédric Le Goater
@ 2022-03-02 11:07 ` Cédric Le Goater
2022-03-02 11:07 ` [PULL 31/87] target/ppc: implement vrlq Cédric Le Goater
` (57 subsequent siblings)
87 siblings, 0 replies; 89+ messages in thread
From: Cédric Le Goater @ 2022-03-02 11:07 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Richard Henderson, Matheus Ferst,
Cédric Le Goater
From: Matheus Ferst <matheus.ferst@eldorado.org.br>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220225210936.1749575-25-matheus.ferst@eldorado.org.br>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/helper.h | 8 +-
target/ppc/insn32.decode | 6 ++
target/ppc/int_helper.c | 54 +++++-----
target/ppc/translate/vmx-impl.c.inc | 152 ++++++++++++++++++++++++++--
target/ppc/translate/vmx-ops.c.inc | 5 +-
5 files changed, 184 insertions(+), 41 deletions(-)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 2c6146d55eb0..4fa81093ca3b 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -273,10 +273,10 @@ DEF_HELPER_4(vmaxfp, void, env, avr, avr, avr)
DEF_HELPER_4(vminfp, void, env, avr, avr, avr)
DEF_HELPER_3(vrefp, void, env, avr, avr)
DEF_HELPER_3(vrsqrtefp, void, env, avr, avr)
-DEF_HELPER_3(vrlwmi, void, avr, avr, avr)
-DEF_HELPER_3(vrldmi, void, avr, avr, avr)
-DEF_HELPER_3(vrldnm, void, avr, avr, avr)
-DEF_HELPER_3(vrlwnm, void, avr, avr, avr)
+DEF_HELPER_FLAGS_4(VRLWMI, TCG_CALL_NO_RWG, void, avr, avr, avr, i32)
+DEF_HELPER_FLAGS_4(VRLDMI, TCG_CALL_NO_RWG, void, avr, avr, avr, i32)
+DEF_HELPER_FLAGS_4(VRLDNM, TCG_CALL_NO_RWG, void, avr, avr, avr, i32)
+DEF_HELPER_FLAGS_4(VRLWNM, TCG_CALL_NO_RWG, void, avr, avr, avr, i32)
DEF_HELPER_5(vmaddfp, void, env, avr, avr, avr, avr)
DEF_HELPER_5(vnmsubfp, void, env, avr, avr, avr, avr)
DEF_HELPER_3(vexptefp, void, env, avr, avr)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index d918e2d0f29f..e788dc51523d 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -492,6 +492,12 @@ VRLH 000100 ..... ..... ..... 00001000100 @VX
VRLW 000100 ..... ..... ..... 00010000100 @VX
VRLD 000100 ..... ..... ..... 00011000100 @VX
+VRLWMI 000100 ..... ..... ..... 00010000101 @VX
+VRLDMI 000100 ..... ..... ..... 00011000101 @VX
+
+VRLWNM 000100 ..... ..... ..... 00110000101 @VX
+VRLDNM 000100 ..... ..... ..... 00111000101 @VX
+
## Vector Integer Arithmetic Instructions
VEXTSB2W 000100 ..... 10000 ..... 11000000010 @VX_tb
diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
index 71b31fbd891d..f52242ca812e 100644
--- a/target/ppc/int_helper.c
+++ b/target/ppc/int_helper.c
@@ -1275,33 +1275,33 @@ void helper_vrsqrtefp(CPUPPCState *env, ppc_avr_t *r, ppc_avr_t *b)
}
}
-#define VRLMI(name, size, element, insert) \
-void helper_##name(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
-{ \
- int i; \
- for (i = 0; i < ARRAY_SIZE(r->element); i++) { \
- uint##size##_t src1 = a->element[i]; \
- uint##size##_t src2 = b->element[i]; \
- uint##size##_t src3 = r->element[i]; \
- uint##size##_t begin, end, shift, mask, rot_val; \
- \
- shift = extract##size(src2, 0, 6); \
- end = extract##size(src2, 8, 6); \
- begin = extract##size(src2, 16, 6); \
- rot_val = rol##size(src1, shift); \
- mask = mask_u##size(begin, end); \
- if (insert) { \
- r->element[i] = (rot_val & mask) | (src3 & ~mask); \
- } else { \
- r->element[i] = (rot_val & mask); \
- } \
- } \
-}
-
-VRLMI(vrldmi, 64, u64, 1);
-VRLMI(vrlwmi, 32, u32, 1);
-VRLMI(vrldnm, 64, u64, 0);
-VRLMI(vrlwnm, 32, u32, 0);
+#define VRLMI(name, size, element, insert) \
+void helper_##name(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, uint32_t desc) \
+{ \
+ int i; \
+ for (i = 0; i < ARRAY_SIZE(r->element); i++) { \
+ uint##size##_t src1 = a->element[i]; \
+ uint##size##_t src2 = b->element[i]; \
+ uint##size##_t src3 = r->element[i]; \
+ uint##size##_t begin, end, shift, mask, rot_val; \
+ \
+ shift = extract##size(src2, 0, 6); \
+ end = extract##size(src2, 8, 6); \
+ begin = extract##size(src2, 16, 6); \
+ rot_val = rol##size(src1, shift); \
+ mask = mask_u##size(begin, end); \
+ if (insert) { \
+ r->element[i] = (rot_val & mask) | (src3 & ~mask); \
+ } else { \
+ r->element[i] = (rot_val & mask); \
+ } \
+ } \
+}
+
+VRLMI(VRLDMI, 64, u64, 1);
+VRLMI(VRLWMI, 32, u32, 1);
+VRLMI(VRLDNM, 64, u64, 0);
+VRLMI(VRLWNM, 32, u32, 0);
void helper_vsel(CPUPPCState *env, ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b,
ppc_avr_t *c)
diff --git a/target/ppc/translate/vmx-impl.c.inc b/target/ppc/translate/vmx-impl.c.inc
index f24b78d42efc..09d6c88e62a8 100644
--- a/target/ppc/translate/vmx-impl.c.inc
+++ b/target/ppc/translate/vmx-impl.c.inc
@@ -799,7 +799,6 @@ static void trans_vclzd(DisasContext *ctx)
}
GEN_VXFORM_V(vmuluwm, MO_32, tcg_gen_gvec_mul, 4, 2);
-GEN_VXFORM(vrlwnm, 2, 6);
GEN_VXFORM(vsrv, 2, 28);
GEN_VXFORM(vslv, 2, 29);
GEN_VXFORM(vslo, 6, 16);
@@ -839,6 +838,152 @@ TRANS_FLAGS(ALTIVEC, VRLH, do_vector_gvec3_VX, MO_16, tcg_gen_gvec_rotlv)
TRANS_FLAGS(ALTIVEC, VRLW, do_vector_gvec3_VX, MO_32, tcg_gen_gvec_rotlv)
TRANS_FLAGS2(ALTIVEC_207, VRLD, do_vector_gvec3_VX, MO_64, tcg_gen_gvec_rotlv)
+static TCGv_vec do_vrl_mask_vec(unsigned vece, TCGv_vec vrb)
+{
+ TCGv_vec t0 = tcg_temp_new_vec_matching(vrb),
+ t1 = tcg_temp_new_vec_matching(vrb),
+ t2 = tcg_temp_new_vec_matching(vrb),
+ ones = tcg_constant_vec_matching(vrb, vece, -1);
+
+ /* Extract b and e */
+ tcg_gen_dupi_vec(vece, t2, (8 << vece) - 1);
+
+ tcg_gen_shri_vec(vece, t0, vrb, 16);
+ tcg_gen_and_vec(vece, t0, t0, t2);
+
+ tcg_gen_shri_vec(vece, t1, vrb, 8);
+ tcg_gen_and_vec(vece, t1, t1, t2);
+
+ /* Compare b and e to negate the mask where begin > end */
+ tcg_gen_cmp_vec(TCG_COND_GT, vece, t2, t0, t1);
+
+ /* Create the mask with (~0 >> b) ^ ((~0 >> e) >> 1) */
+ tcg_gen_shrv_vec(vece, t0, ones, t0);
+ tcg_gen_shrv_vec(vece, t1, ones, t1);
+ tcg_gen_shri_vec(vece, t1, t1, 1);
+ tcg_gen_xor_vec(vece, t0, t0, t1);
+
+ /* negate the mask */
+ tcg_gen_xor_vec(vece, t0, t0, t2);
+
+ tcg_temp_free_vec(t1);
+ tcg_temp_free_vec(t2);
+
+ return t0;
+}
+
+static void gen_vrlnm_vec(unsigned vece, TCGv_vec vrt, TCGv_vec vra,
+ TCGv_vec vrb)
+{
+ TCGv_vec mask, n = tcg_temp_new_vec_matching(vrt);
+
+ /* Create the mask */
+ mask = do_vrl_mask_vec(vece, vrb);
+
+ /* Extract n */
+ tcg_gen_dupi_vec(vece, n, (8 << vece) - 1);
+ tcg_gen_and_vec(vece, n, vrb, n);
+
+ /* Rotate and mask */
+ tcg_gen_rotlv_vec(vece, vrt, vra, n);
+ tcg_gen_and_vec(vece, vrt, vrt, mask);
+
+ tcg_temp_free_vec(n);
+ tcg_temp_free_vec(mask);
+}
+
+static bool do_vrlnm(DisasContext *ctx, arg_VX *a, int vece)
+{
+ static const TCGOpcode vecop_list[] = {
+ INDEX_op_cmp_vec, INDEX_op_rotlv_vec, INDEX_op_sari_vec,
+ INDEX_op_shli_vec, INDEX_op_shri_vec, INDEX_op_shrv_vec, 0
+ };
+ static const GVecGen3 ops[2] = {
+ {
+ .fniv = gen_vrlnm_vec,
+ .fno = gen_helper_VRLWNM,
+ .opt_opc = vecop_list,
+ .load_dest = true,
+ .vece = MO_32
+ },
+ {
+ .fniv = gen_vrlnm_vec,
+ .fno = gen_helper_VRLDNM,
+ .opt_opc = vecop_list,
+ .load_dest = true,
+ .vece = MO_64
+ }
+ };
+
+ REQUIRE_INSNS_FLAGS2(ctx, ISA300);
+ REQUIRE_VSX(ctx);
+
+ tcg_gen_gvec_3(avr_full_offset(a->vrt), avr_full_offset(a->vra),
+ avr_full_offset(a->vrb), 16, 16, &ops[vece - 2]);
+
+ return true;
+}
+
+TRANS(VRLWNM, do_vrlnm, MO_32)
+TRANS(VRLDNM, do_vrlnm, MO_64)
+
+static void gen_vrlmi_vec(unsigned vece, TCGv_vec vrt, TCGv_vec vra,
+ TCGv_vec vrb)
+{
+ TCGv_vec mask, n = tcg_temp_new_vec_matching(vrt),
+ tmp = tcg_temp_new_vec_matching(vrt);
+
+ /* Create the mask */
+ mask = do_vrl_mask_vec(vece, vrb);
+
+ /* Extract n */
+ tcg_gen_dupi_vec(vece, n, (8 << vece) - 1);
+ tcg_gen_and_vec(vece, n, vrb, n);
+
+ /* Rotate and insert */
+ tcg_gen_rotlv_vec(vece, tmp, vra, n);
+ tcg_gen_bitsel_vec(vece, vrt, mask, tmp, vrt);
+
+ tcg_temp_free_vec(n);
+ tcg_temp_free_vec(tmp);
+ tcg_temp_free_vec(mask);
+}
+
+static bool do_vrlmi(DisasContext *ctx, arg_VX *a, int vece)
+{
+ static const TCGOpcode vecop_list[] = {
+ INDEX_op_cmp_vec, INDEX_op_rotlv_vec, INDEX_op_sari_vec,
+ INDEX_op_shli_vec, INDEX_op_shri_vec, INDEX_op_shrv_vec, 0
+ };
+ static const GVecGen3 ops[2] = {
+ {
+ .fniv = gen_vrlmi_vec,
+ .fno = gen_helper_VRLWMI,
+ .opt_opc = vecop_list,
+ .load_dest = true,
+ .vece = MO_32
+ },
+ {
+ .fniv = gen_vrlnm_vec,
+ .fno = gen_helper_VRLDMI,
+ .opt_opc = vecop_list,
+ .load_dest = true,
+ .vece = MO_64
+ }
+ };
+
+ REQUIRE_INSNS_FLAGS2(ctx, ISA300);
+ REQUIRE_VSX(ctx);
+
+ tcg_gen_gvec_3(avr_full_offset(a->vrt), avr_full_offset(a->vra),
+ avr_full_offset(a->vrb), 16, 16, &ops[vece - 2]);
+
+ return true;
+}
+
+TRANS(VRLWMI, do_vrlmi, MO_32)
+TRANS(VRLDMI, do_vrlmi, MO_64)
+
static bool do_vector_shift_quad(DisasContext *ctx, arg_VX *a, bool right,
bool alg)
{
@@ -975,12 +1120,7 @@ GEN_VXFORM3(vsubeuqm, 31, 0);
GEN_VXFORM3(vsubecuq, 31, 0);
GEN_VXFORM_DUAL(vsubeuqm, PPC_NONE, PPC2_ALTIVEC_207, \
vsubecuq, PPC_NONE, PPC2_ALTIVEC_207)
-GEN_VXFORM(vrlwmi, 2, 2);
-GEN_VXFORM(vrldmi, 2, 3);
GEN_VXFORM_TRANS(vsl, 2, 7);
-GEN_VXFORM(vrldnm, 2, 7);
-GEN_VXFORM_DUAL(vsl, PPC_ALTIVEC, PPC_NONE, \
- vrldnm, PPC_NONE, PPC2_ISA300)
GEN_VXFORM_TRANS(vsr, 2, 11);
GEN_VXFORM_ENV(vpkuhum, 7, 0);
GEN_VXFORM_ENV(vpkuwum, 7, 1);
diff --git a/target/ppc/translate/vmx-ops.c.inc b/target/ppc/translate/vmx-ops.c.inc
index a7acea3ca78e..3a8a9cc564a2 100644
--- a/target/ppc/translate/vmx-ops.c.inc
+++ b/target/ppc/translate/vmx-ops.c.inc
@@ -102,7 +102,6 @@ GEN_VXFORM_300(vextubrx, 6, 28),
GEN_VXFORM_300(vextuhrx, 6, 29),
GEN_VXFORM_DUAL(vmrgew, vextuwrx, 6, 30, PPC_NONE, PPC2_ALTIVEC_207),
GEN_VXFORM_207(vmuluwm, 4, 2),
-GEN_VXFORM_300(vrlwnm, 2, 6),
GEN_VXFORM_300(vsrv, 2, 28),
GEN_VXFORM_300(vslv, 2, 29),
GEN_VXFORM(vslo, 6, 16),
@@ -133,9 +132,7 @@ GEN_VXFORM_DUAL(vaddeuqm, vaddecuq, 30, 0xFF, PPC_NONE, PPC2_ALTIVEC_207),
GEN_VXFORM_DUAL(vsubuqm, bcdtrunc, 0, 20, PPC2_ALTIVEC_207, PPC2_ISA300),
GEN_VXFORM_DUAL(vsubcuq, bcdutrunc, 0, 21, PPC2_ALTIVEC_207, PPC2_ISA300),
GEN_VXFORM_DUAL(vsubeuqm, vsubecuq, 31, 0xFF, PPC_NONE, PPC2_ALTIVEC_207),
-GEN_VXFORM_300(vrlwmi, 2, 2),
-GEN_VXFORM_300(vrldmi, 2, 3),
-GEN_VXFORM_DUAL(vsl, vrldnm, 2, 7, PPC_ALTIVEC, PPC_NONE),
+GEN_VXFORM(vsl, 2, 7),
GEN_VXFORM(vsr, 2, 11),
GEN_VXFORM(vpkuhum, 7, 0),
GEN_VXFORM(vpkuwum, 7, 1),
--
2.34.1
^ permalink raw reply related [flat|nested] 89+ messages in thread* [PULL 31/87] target/ppc: implement vrlq
2022-03-02 11:06 [PULL 00/87] ppc queue Cédric Le Goater
` (29 preceding siblings ...)
2022-03-02 11:07 ` [PULL 30/87] target/ppc: move vrl[bhwd]nm/vrl[bhwd]mi " Cédric Le Goater
@ 2022-03-02 11:07 ` Cédric Le Goater
2022-03-02 11:07 ` [PULL 32/87] target/ppc: implement vrlqnm Cédric Le Goater
` (56 subsequent siblings)
87 siblings, 0 replies; 89+ messages in thread
From: Cédric Le Goater @ 2022-03-02 11:07 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Richard Henderson, Matheus Ferst,
Cédric Le Goater
From: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20220225210936.1749575-26-matheus.ferst@eldorado.org.br>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/insn32.decode | 1 +
target/ppc/translate/vmx-impl.c.inc | 48 +++++++++++++++++++++++++++++
2 files changed, 49 insertions(+)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index e788dc51523d..c3d47a881573 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -491,6 +491,7 @@ VRLB 000100 ..... ..... ..... 00000000100 @VX
VRLH 000100 ..... ..... ..... 00001000100 @VX
VRLW 000100 ..... ..... ..... 00010000100 @VX
VRLD 000100 ..... ..... ..... 00011000100 @VX
+VRLQ 000100 ..... ..... ..... 00000000101 @VX
VRLWMI 000100 ..... ..... ..... 00010000101 @VX
VRLDMI 000100 ..... ..... ..... 00011000101 @VX
diff --git a/target/ppc/translate/vmx-impl.c.inc b/target/ppc/translate/vmx-impl.c.inc
index 09d6c88e62a8..478a62440db3 100644
--- a/target/ppc/translate/vmx-impl.c.inc
+++ b/target/ppc/translate/vmx-impl.c.inc
@@ -1055,6 +1055,54 @@ TRANS_FLAGS2(ISA310, VSLQ, do_vector_shift_quad, false, false);
TRANS_FLAGS2(ISA310, VSRQ, do_vector_shift_quad, true, false);
TRANS_FLAGS2(ISA310, VSRAQ, do_vector_shift_quad, true, true);
+static bool trans_VRLQ(DisasContext *ctx, arg_VX *a)
+{
+ TCGv_i64 ah, al, n, t0, t1, zero = tcg_constant_i64(0);
+
+ REQUIRE_VECTOR(ctx);
+ REQUIRE_INSNS_FLAGS2(ctx, ISA310);
+
+ ah = tcg_temp_new_i64();
+ al = tcg_temp_new_i64();
+ n = tcg_temp_new_i64();
+ t0 = tcg_temp_new_i64();
+ t1 = tcg_temp_new_i64();
+
+ get_avr64(ah, a->vra, true);
+ get_avr64(al, a->vra, false);
+ get_avr64(n, a->vrb, true);
+
+ tcg_gen_mov_i64(t0, ah);
+ tcg_gen_andi_i64(t1, n, 64);
+ tcg_gen_movcond_i64(TCG_COND_NE, ah, t1, zero, al, ah);
+ tcg_gen_movcond_i64(TCG_COND_NE, al, t1, zero, t0, al);
+ tcg_gen_andi_i64(n, n, 0x3F);
+
+ tcg_gen_shl_i64(t0, ah, n);
+ tcg_gen_shl_i64(t1, al, n);
+
+ tcg_gen_xori_i64(n, n, 63);
+
+ tcg_gen_shr_i64(al, al, n);
+ tcg_gen_shri_i64(al, al, 1);
+ tcg_gen_or_i64(t0, al, t0);
+
+ tcg_gen_shr_i64(ah, ah, n);
+ tcg_gen_shri_i64(ah, ah, 1);
+ tcg_gen_or_i64(t1, ah, t1);
+
+ set_avr64(a->vrt, t0, true);
+ set_avr64(a->vrt, t1, false);
+
+ tcg_temp_free_i64(ah);
+ tcg_temp_free_i64(al);
+ tcg_temp_free_i64(n);
+ tcg_temp_free_i64(t0);
+ tcg_temp_free_i64(t1);
+
+ return true;
+}
+
#define GEN_VXFORM_SAT(NAME, VECE, NORM, SAT, OPC2, OPC3) \
static void glue(glue(gen_, NAME), _vec)(unsigned vece, TCGv_vec t, \
TCGv_vec sat, TCGv_vec a, \
--
2.34.1
^ permalink raw reply related [flat|nested] 89+ messages in thread* [PULL 32/87] target/ppc: implement vrlqnm
2022-03-02 11:06 [PULL 00/87] ppc queue Cédric Le Goater
` (30 preceding siblings ...)
2022-03-02 11:07 ` [PULL 31/87] target/ppc: implement vrlq Cédric Le Goater
@ 2022-03-02 11:07 ` Cédric Le Goater
2022-03-02 11:07 ` [PULL 33/87] target/ppc: implement vrlqmi Cédric Le Goater
` (55 subsequent siblings)
87 siblings, 0 replies; 89+ messages in thread
From: Cédric Le Goater @ 2022-03-02 11:07 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Richard Henderson, Matheus Ferst,
Cédric Le Goater
From: Matheus Ferst <matheus.ferst@eldorado.org.br>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220225210936.1749575-27-matheus.ferst@eldorado.org.br>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/insn32.decode | 1 +
target/ppc/translate/vmx-impl.c.inc | 81 +++++++++++++++++++++++++++--
2 files changed, 77 insertions(+), 5 deletions(-)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index c3d47a881573..87d482c5d961 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -498,6 +498,7 @@ VRLDMI 000100 ..... ..... ..... 00011000101 @VX
VRLWNM 000100 ..... ..... ..... 00110000101 @VX
VRLDNM 000100 ..... ..... ..... 00111000101 @VX
+VRLQNM 000100 ..... ..... ..... 00101000101 @VX
## Vector Integer Arithmetic Instructions
diff --git a/target/ppc/translate/vmx-impl.c.inc b/target/ppc/translate/vmx-impl.c.inc
index 478a62440db3..eb305e84da9a 100644
--- a/target/ppc/translate/vmx-impl.c.inc
+++ b/target/ppc/translate/vmx-impl.c.inc
@@ -1055,28 +1055,83 @@ TRANS_FLAGS2(ISA310, VSLQ, do_vector_shift_quad, false, false);
TRANS_FLAGS2(ISA310, VSRQ, do_vector_shift_quad, true, false);
TRANS_FLAGS2(ISA310, VSRAQ, do_vector_shift_quad, true, true);
-static bool trans_VRLQ(DisasContext *ctx, arg_VX *a)
+static void do_vrlq_mask(TCGv_i64 mh, TCGv_i64 ml, TCGv_i64 b, TCGv_i64 e)
{
- TCGv_i64 ah, al, n, t0, t1, zero = tcg_constant_i64(0);
+ TCGv_i64 th, tl, t0, t1, zero = tcg_constant_i64(0),
+ ones = tcg_constant_i64(-1);
+
+ th = tcg_temp_new_i64();
+ tl = tcg_temp_new_i64();
+ t0 = tcg_temp_new_i64();
+ t1 = tcg_temp_new_i64();
+
+ /* m = ~0 >> b */
+ tcg_gen_andi_i64(t0, b, 64);
+ tcg_gen_movcond_i64(TCG_COND_NE, t1, t0, zero, zero, ones);
+ tcg_gen_andi_i64(t0, b, 0x3F);
+ tcg_gen_shr_i64(mh, t1, t0);
+ tcg_gen_shr_i64(ml, ones, t0);
+ tcg_gen_xori_i64(t0, t0, 63);
+ tcg_gen_shl_i64(t1, t1, t0);
+ tcg_gen_shli_i64(t1, t1, 1);
+ tcg_gen_or_i64(ml, t1, ml);
+
+ /* t = ~0 >> e */
+ tcg_gen_andi_i64(t0, e, 64);
+ tcg_gen_movcond_i64(TCG_COND_NE, t1, t0, zero, zero, ones);
+ tcg_gen_andi_i64(t0, e, 0x3F);
+ tcg_gen_shr_i64(th, t1, t0);
+ tcg_gen_shr_i64(tl, ones, t0);
+ tcg_gen_xori_i64(t0, t0, 63);
+ tcg_gen_shl_i64(t1, t1, t0);
+ tcg_gen_shli_i64(t1, t1, 1);
+ tcg_gen_or_i64(tl, t1, tl);
+
+ /* t = t >> 1 */
+ tcg_gen_shli_i64(t0, th, 63);
+ tcg_gen_shri_i64(tl, tl, 1);
+ tcg_gen_shri_i64(th, th, 1);
+ tcg_gen_or_i64(tl, t0, tl);
+
+ /* m = m ^ t */
+ tcg_gen_xor_i64(mh, mh, th);
+ tcg_gen_xor_i64(ml, ml, tl);
+
+ /* Negate the mask if begin > end */
+ tcg_gen_movcond_i64(TCG_COND_GT, t0, b, e, ones, zero);
+
+ tcg_gen_xor_i64(mh, mh, t0);
+ tcg_gen_xor_i64(ml, ml, t0);
+
+ tcg_temp_free_i64(th);
+ tcg_temp_free_i64(tl);
+ tcg_temp_free_i64(t0);
+ tcg_temp_free_i64(t1);
+}
+
+static bool do_vector_rotl_quad(DisasContext *ctx, arg_VX *a, bool mask)
+{
+ TCGv_i64 ah, al, vrb, n, t0, t1, zero = tcg_constant_i64(0);
REQUIRE_VECTOR(ctx);
REQUIRE_INSNS_FLAGS2(ctx, ISA310);
ah = tcg_temp_new_i64();
al = tcg_temp_new_i64();
+ vrb = tcg_temp_new_i64();
n = tcg_temp_new_i64();
t0 = tcg_temp_new_i64();
t1 = tcg_temp_new_i64();
get_avr64(ah, a->vra, true);
get_avr64(al, a->vra, false);
- get_avr64(n, a->vrb, true);
+ get_avr64(vrb, a->vrb, true);
tcg_gen_mov_i64(t0, ah);
- tcg_gen_andi_i64(t1, n, 64);
+ tcg_gen_andi_i64(t1, vrb, 64);
tcg_gen_movcond_i64(TCG_COND_NE, ah, t1, zero, al, ah);
tcg_gen_movcond_i64(TCG_COND_NE, al, t1, zero, t0, al);
- tcg_gen_andi_i64(n, n, 0x3F);
+ tcg_gen_andi_i64(n, vrb, 0x3F);
tcg_gen_shl_i64(t0, ah, n);
tcg_gen_shl_i64(t1, al, n);
@@ -1091,11 +1146,24 @@ static bool trans_VRLQ(DisasContext *ctx, arg_VX *a)
tcg_gen_shri_i64(ah, ah, 1);
tcg_gen_or_i64(t1, ah, t1);
+ if (mask) {
+ tcg_gen_shri_i64(n, vrb, 8);
+ tcg_gen_shri_i64(vrb, vrb, 16);
+ tcg_gen_andi_i64(n, n, 0x7f);
+ tcg_gen_andi_i64(vrb, vrb, 0x7f);
+
+ do_vrlq_mask(ah, al, vrb, n);
+
+ tcg_gen_and_i64(t0, t0, ah);
+ tcg_gen_and_i64(t1, t1, al);
+ }
+
set_avr64(a->vrt, t0, true);
set_avr64(a->vrt, t1, false);
tcg_temp_free_i64(ah);
tcg_temp_free_i64(al);
+ tcg_temp_free_i64(vrb);
tcg_temp_free_i64(n);
tcg_temp_free_i64(t0);
tcg_temp_free_i64(t1);
@@ -1103,6 +1171,9 @@ static bool trans_VRLQ(DisasContext *ctx, arg_VX *a)
return true;
}
+TRANS(VRLQ, do_vector_rotl_quad, false)
+TRANS(VRLQNM, do_vector_rotl_quad, true)
+
#define GEN_VXFORM_SAT(NAME, VECE, NORM, SAT, OPC2, OPC3) \
static void glue(glue(gen_, NAME), _vec)(unsigned vece, TCGv_vec t, \
TCGv_vec sat, TCGv_vec a, \
--
2.34.1
^ permalink raw reply related [flat|nested] 89+ messages in thread* [PULL 33/87] target/ppc: implement vrlqmi
2022-03-02 11:06 [PULL 00/87] ppc queue Cédric Le Goater
` (31 preceding siblings ...)
2022-03-02 11:07 ` [PULL 32/87] target/ppc: implement vrlqnm Cédric Le Goater
@ 2022-03-02 11:07 ` Cédric Le Goater
2022-03-02 11:07 ` [PULL 34/87] target/ppc: Move vsel and vperm/vpermr to decodetree Cédric Le Goater
` (54 subsequent siblings)
87 siblings, 0 replies; 89+ messages in thread
From: Cédric Le Goater @ 2022-03-02 11:07 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Richard Henderson, Matheus Ferst,
Cédric Le Goater
From: Matheus Ferst <matheus.ferst@eldorado.org.br>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220225210936.1749575-28-matheus.ferst@eldorado.org.br>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/insn32.decode | 1 +
target/ppc/translate/vmx-impl.c.inc | 21 +++++++++++++++++----
2 files changed, 18 insertions(+), 4 deletions(-)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 87d482c5d961..abc2007129d9 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -495,6 +495,7 @@ VRLQ 000100 ..... ..... ..... 00000000101 @VX
VRLWMI 000100 ..... ..... ..... 00010000101 @VX
VRLDMI 000100 ..... ..... ..... 00011000101 @VX
+VRLQMI 000100 ..... ..... ..... 00001000101 @VX
VRLWNM 000100 ..... ..... ..... 00110000101 @VX
VRLDNM 000100 ..... ..... ..... 00111000101 @VX
diff --git a/target/ppc/translate/vmx-impl.c.inc b/target/ppc/translate/vmx-impl.c.inc
index eb305e84da9a..352250fad087 100644
--- a/target/ppc/translate/vmx-impl.c.inc
+++ b/target/ppc/translate/vmx-impl.c.inc
@@ -1109,7 +1109,8 @@ static void do_vrlq_mask(TCGv_i64 mh, TCGv_i64 ml, TCGv_i64 b, TCGv_i64 e)
tcg_temp_free_i64(t1);
}
-static bool do_vector_rotl_quad(DisasContext *ctx, arg_VX *a, bool mask)
+static bool do_vector_rotl_quad(DisasContext *ctx, arg_VX *a, bool mask,
+ bool insert)
{
TCGv_i64 ah, al, vrb, n, t0, t1, zero = tcg_constant_i64(0);
@@ -1146,7 +1147,7 @@ static bool do_vector_rotl_quad(DisasContext *ctx, arg_VX *a, bool mask)
tcg_gen_shri_i64(ah, ah, 1);
tcg_gen_or_i64(t1, ah, t1);
- if (mask) {
+ if (mask || insert) {
tcg_gen_shri_i64(n, vrb, 8);
tcg_gen_shri_i64(vrb, vrb, 16);
tcg_gen_andi_i64(n, n, 0x7f);
@@ -1156,6 +1157,17 @@ static bool do_vector_rotl_quad(DisasContext *ctx, arg_VX *a, bool mask)
tcg_gen_and_i64(t0, t0, ah);
tcg_gen_and_i64(t1, t1, al);
+
+ if (insert) {
+ get_avr64(n, a->vrt, true);
+ get_avr64(vrb, a->vrt, false);
+ tcg_gen_not_i64(ah, ah);
+ tcg_gen_not_i64(al, al);
+ tcg_gen_and_i64(n, n, ah);
+ tcg_gen_and_i64(vrb, vrb, al);
+ tcg_gen_or_i64(t0, t0, n);
+ tcg_gen_or_i64(t1, t1, vrb);
+ }
}
set_avr64(a->vrt, t0, true);
@@ -1171,8 +1183,9 @@ static bool do_vector_rotl_quad(DisasContext *ctx, arg_VX *a, bool mask)
return true;
}
-TRANS(VRLQ, do_vector_rotl_quad, false)
-TRANS(VRLQNM, do_vector_rotl_quad, true)
+TRANS(VRLQ, do_vector_rotl_quad, false, false)
+TRANS(VRLQNM, do_vector_rotl_quad, true, false)
+TRANS(VRLQMI, do_vector_rotl_quad, false, true)
#define GEN_VXFORM_SAT(NAME, VECE, NORM, SAT, OPC2, OPC3) \
static void glue(glue(gen_, NAME), _vec)(unsigned vece, TCGv_vec t, \
--
2.34.1
^ permalink raw reply related [flat|nested] 89+ messages in thread* [PULL 34/87] target/ppc: Move vsel and vperm/vpermr to decodetree
2022-03-02 11:06 [PULL 00/87] ppc queue Cédric Le Goater
` (32 preceding siblings ...)
2022-03-02 11:07 ` [PULL 33/87] target/ppc: implement vrlqmi Cédric Le Goater
@ 2022-03-02 11:07 ` Cédric Le Goater
2022-03-02 11:07 ` [PULL 35/87] target/ppc: Move xxsel " Cédric Le Goater
` (53 subsequent siblings)
87 siblings, 0 replies; 89+ messages in thread
From: Cédric Le Goater @ 2022-03-02 11:07 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Richard Henderson, Matheus Ferst,
Cédric Le Goater
From: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20220225210936.1749575-29-matheus.ferst@eldorado.org.br>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/helper.h | 5 +--
target/ppc/insn32.decode | 5 +++
target/ppc/int_helper.c | 13 +-----
target/ppc/translate/vmx-impl.c.inc | 69 ++++++++++++++++++++++-------
target/ppc/translate/vmx-ops.c.inc | 2 -
5 files changed, 62 insertions(+), 32 deletions(-)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 4fa81093ca3b..430e75b31f25 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -225,9 +225,8 @@ DEF_HELPER_2(vupklsh, void, avr, avr)
DEF_HELPER_2(vupklsw, void, avr, avr)
DEF_HELPER_5(vmsumubm, void, env, avr, avr, avr, avr)
DEF_HELPER_5(vmsummbm, void, env, avr, avr, avr, avr)
-DEF_HELPER_5(vsel, void, env, avr, avr, avr, avr)
-DEF_HELPER_5(vperm, void, env, avr, avr, avr, avr)
-DEF_HELPER_5(vpermr, void, env, avr, avr, avr, avr)
+DEF_HELPER_FLAGS_4(VPERM, TCG_CALL_NO_RWG, void, avr, avr, avr, avr)
+DEF_HELPER_FLAGS_4(VPERMR, TCG_CALL_NO_RWG, void, avr, avr, avr, avr)
DEF_HELPER_4(vpkshss, void, env, avr, avr, avr)
DEF_HELPER_4(vpkshus, void, env, avr, avr, avr)
DEF_HELPER_4(vpkswss, void, env, avr, avr, avr)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index abc2007129d9..0a3ada2b663a 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -467,6 +467,11 @@ VINSWVRX 000100 ..... ..... ..... 00110001111 @VX
VSLDBI 000100 ..... ..... ..... 00 ... 010110 @VN
VSRDBI 000100 ..... ..... ..... 01 ... 010110 @VN
+VPERM 000100 ..... ..... ..... ..... 101011 @VA
+VPERMR 000100 ..... ..... ..... ..... 111011 @VA
+
+VSEL 000100 ..... ..... ..... ..... 101010 @VA
+
## Vector Integer Shift Instruction
VSLB 000100 ..... ..... ..... 00100000100 @VX
diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
index f52242ca812e..6c63c7b2278c 100644
--- a/target/ppc/int_helper.c
+++ b/target/ppc/int_helper.c
@@ -1015,8 +1015,7 @@ VMUL(UW, u32, VsrW, VsrD, uint64_t)
#undef VMUL_DO_ODD
#undef VMUL
-void helper_vperm(CPUPPCState *env, ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b,
- ppc_avr_t *c)
+void helper_VPERM(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c)
{
ppc_avr_t result;
int i;
@@ -1034,8 +1033,7 @@ void helper_vperm(CPUPPCState *env, ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b,
*r = result;
}
-void helper_vpermr(CPUPPCState *env, ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b,
- ppc_avr_t *c)
+void helper_VPERMR(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c)
{
ppc_avr_t result;
int i;
@@ -1303,13 +1301,6 @@ VRLMI(VRLWMI, 32, u32, 1);
VRLMI(VRLDNM, 64, u64, 0);
VRLMI(VRLWNM, 32, u32, 0);
-void helper_vsel(CPUPPCState *env, ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b,
- ppc_avr_t *c)
-{
- r->u64[0] = (a->u64[0] & ~c->u64[0]) | (b->u64[0] & c->u64[0]);
- r->u64[1] = (a->u64[1] & ~c->u64[1]) | (b->u64[1] & c->u64[1]);
-}
-
void helper_vexptefp(CPUPPCState *env, ppc_avr_t *r, ppc_avr_t *b)
{
int i;
diff --git a/target/ppc/translate/vmx-impl.c.inc b/target/ppc/translate/vmx-impl.c.inc
index 352250fad087..f91bee839d94 100644
--- a/target/ppc/translate/vmx-impl.c.inc
+++ b/target/ppc/translate/vmx-impl.c.inc
@@ -2559,28 +2559,65 @@ static void gen_vmladduhm(DisasContext *ctx)
tcg_temp_free_ptr(rd);
}
-static void gen_vpermr(DisasContext *ctx)
+static bool trans_VPERM(DisasContext *ctx, arg_VA *a)
{
- TCGv_ptr ra, rb, rc, rd;
- if (unlikely(!ctx->altivec_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_VPU);
- return;
- }
- ra = gen_avr_ptr(rA(ctx->opcode));
- rb = gen_avr_ptr(rB(ctx->opcode));
- rc = gen_avr_ptr(rC(ctx->opcode));
- rd = gen_avr_ptr(rD(ctx->opcode));
- gen_helper_vpermr(cpu_env, rd, ra, rb, rc);
- tcg_temp_free_ptr(ra);
- tcg_temp_free_ptr(rb);
- tcg_temp_free_ptr(rc);
- tcg_temp_free_ptr(rd);
+ TCGv_ptr vrt, vra, vrb, vrc;
+
+ REQUIRE_INSNS_FLAGS(ctx, ALTIVEC);
+ REQUIRE_VECTOR(ctx);
+
+ vrt = gen_avr_ptr(a->vrt);
+ vra = gen_avr_ptr(a->vra);
+ vrb = gen_avr_ptr(a->vrb);
+ vrc = gen_avr_ptr(a->rc);
+
+ gen_helper_VPERM(vrt, vra, vrb, vrc);
+
+ tcg_temp_free_ptr(vrt);
+ tcg_temp_free_ptr(vra);
+ tcg_temp_free_ptr(vrb);
+ tcg_temp_free_ptr(vrc);
+
+ return true;
+}
+
+static bool trans_VPERMR(DisasContext *ctx, arg_VA *a)
+{
+ TCGv_ptr vrt, vra, vrb, vrc;
+
+ REQUIRE_INSNS_FLAGS2(ctx, ISA300);
+ REQUIRE_VECTOR(ctx);
+
+ vrt = gen_avr_ptr(a->vrt);
+ vra = gen_avr_ptr(a->vra);
+ vrb = gen_avr_ptr(a->vrb);
+ vrc = gen_avr_ptr(a->rc);
+
+ gen_helper_VPERMR(vrt, vra, vrb, vrc);
+
+ tcg_temp_free_ptr(vrt);
+ tcg_temp_free_ptr(vra);
+ tcg_temp_free_ptr(vrb);
+ tcg_temp_free_ptr(vrc);
+
+ return true;
+}
+
+static bool trans_VSEL(DisasContext *ctx, arg_VA *a)
+{
+ REQUIRE_INSNS_FLAGS(ctx, ALTIVEC);
+ REQUIRE_VECTOR(ctx);
+
+ tcg_gen_gvec_bitsel(MO_64, avr_full_offset(a->vrt), avr_full_offset(a->rc),
+ avr_full_offset(a->vrb), avr_full_offset(a->vra),
+ 16, 16);
+
+ return true;
}
GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18)
GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19)
GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20)
-GEN_VAFORM_PAIRED(vsel, vperm, 21)
GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23)
GEN_VXFORM_NOA(vclzb, 1, 28)
diff --git a/target/ppc/translate/vmx-ops.c.inc b/target/ppc/translate/vmx-ops.c.inc
index 3a8a9cc564a2..d960648d5231 100644
--- a/target/ppc/translate/vmx-ops.c.inc
+++ b/target/ppc/translate/vmx-ops.c.inc
@@ -194,7 +194,6 @@ GEN_VXFORM_300_EO(vctzw, 0x01, 0x18, 0x1E),
GEN_VXFORM_300_EO(vctzd, 0x01, 0x18, 0x1F),
GEN_VXFORM_300_EO(vclzlsbb, 0x01, 0x18, 0x0),
GEN_VXFORM_300_EO(vctzlsbb, 0x01, 0x18, 0x1),
-GEN_VXFORM_300(vpermr, 0x1D, 0xFF),
#define GEN_VXFORM_NOA(name, opc2, opc3) \
GEN_HANDLER(name, 0x04, opc2, opc3, 0x001f0000, PPC_ALTIVEC)
@@ -229,7 +228,6 @@ GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16),
GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18),
GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19),
GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20),
-GEN_VAFORM_PAIRED(vsel, vperm, 21),
GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23),
GEN_VXFORM_DUAL(vclzb, vpopcntb, 1, 28, PPC_NONE, PPC2_ALTIVEC_207),
--
2.34.1
^ permalink raw reply related [flat|nested] 89+ messages in thread* [PULL 35/87] target/ppc: Move xxsel to decodetree
2022-03-02 11:06 [PULL 00/87] ppc queue Cédric Le Goater
` (33 preceding siblings ...)
2022-03-02 11:07 ` [PULL 34/87] target/ppc: Move vsel and vperm/vpermr to decodetree Cédric Le Goater
@ 2022-03-02 11:07 ` Cédric Le Goater
2022-03-02 11:07 ` [PULL 36/87] target/ppc: move xxperm/xxpermr " Cédric Le Goater
` (52 subsequent siblings)
87 siblings, 0 replies; 89+ messages in thread
From: Cédric Le Goater @ 2022-03-02 11:07 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Richard Henderson, Matheus Ferst,
Cédric Le Goater
From: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20220225210936.1749575-30-matheus.ferst@eldorado.org.br>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/insn32.decode | 6 ++++
target/ppc/insn64.decode | 24 ++++++++--------
target/ppc/translate/vsx-impl.c.inc | 20 ++++++--------
target/ppc/translate/vsx-ops.c.inc | 43 -----------------------------
4 files changed, 26 insertions(+), 67 deletions(-)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 0a3ada2b663a..66cb9184cdab 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -148,12 +148,16 @@
%xx_xt 0:1 21:5
%xx_xb 1:1 11:5
%xx_xa 2:1 16:5
+%xx_xc 3:1 6:5
&XX2 xt xb uim:uint8_t
@XX2 ...... ..... ... uim:2 ..... ......... .. &XX2 xt=%xx_xt xb=%xx_xb
&XX3 xt xa xb
@XX3 ...... ..... ..... ..... ........ ... &XX3 xt=%xx_xt xa=%xx_xa xb=%xx_xb
+&XX4 xt xa xb xc
+@XX4 ...... ..... ..... ..... ..... .. .... &XX4 xt=%xx_xt xa=%xx_xa xb=%xx_xb xc=%xx_xc
+
&Z22_bf_fra bf fra dm
@Z22_bf_fra ...... bf:3 .. fra:5 dm:6 ......... . &Z22_bf_fra
@@ -600,6 +604,8 @@ STXVPX 011111 ..... ..... ..... 0111001101 - @X_TSXP
XXSPLTIB 111100 ..... 00 ........ 0101101000 . @X_imm8
XXSPLTW 111100 ..... ---.. ..... 010100100 . . @XX2
+XXSEL 111100 ..... ..... ..... ..... 11 .... @XX4
+
## VSX Vector Load Special Value Instruction
LXVKQ 111100 ..... 11111 ..... 0101101000 . @X_uim5
diff --git a/target/ppc/insn64.decode b/target/ppc/insn64.decode
index 39e610913dfd..9e4f531fb98b 100644
--- a/target/ppc/insn64.decode
+++ b/target/ppc/insn64.decode
@@ -44,15 +44,15 @@
...... ..... .... . ................ \
&8RR_D si=%8rr_si xt=%8rr_xt
-# Format XX4
-&XX4 xt xa xb xc
-%xx4_xt 0:1 21:5
-%xx4_xa 2:1 16:5
-%xx4_xb 1:1 11:5
-%xx4_xc 3:1 6:5
-@XX4 ........ ........ ........ ........ \
+# Format 8RR:XX4
+%8rr_xx_xt 0:1 21:5
+%8rr_xx_xa 2:1 16:5
+%8rr_xx_xb 1:1 11:5
+%8rr_xx_xc 3:1 6:5
+&8RR_XX4 xt xa xb xc
+@8RR_XX4 ........ ........ ........ ........ \
...... ..... ..... ..... ..... .. .... \
- &XX4 xt=%xx4_xt xa=%xx4_xa xb=%xx4_xb xc=%xx4_xc
+ &8RR_XX4 xt=%8rr_xx_xt xa=%8rr_xx_xa xb=%8rr_xx_xb xc=%8rr_xx_xc
### Fixed-Point Load Instructions
@@ -187,10 +187,10 @@ XXSPLTI32DX 000001 01 0000 -- -- ................ \
100000 ..... 000 .. ................ @8RR_D_IX
XXBLENDVD 000001 01 0000 -- ------------------ \
- 100001 ..... ..... ..... ..... 11 .... @XX4
+ 100001 ..... ..... ..... ..... 11 .... @8RR_XX4
XXBLENDVW 000001 01 0000 -- ------------------ \
- 100001 ..... ..... ..... ..... 10 .... @XX4
+ 100001 ..... ..... ..... ..... 10 .... @8RR_XX4
XXBLENDVH 000001 01 0000 -- ------------------ \
- 100001 ..... ..... ..... ..... 01 .... @XX4
+ 100001 ..... ..... ..... ..... 01 .... @8RR_XX4
XXBLENDVB 000001 01 0000 -- ------------------ \
- 100001 ..... ..... ..... ..... 00 .... @XX4
+ 100001 ..... ..... ..... ..... 00 .... @8RR_XX4
diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx-impl.c.inc
index e8a4ba0cfa60..48e4a2e26645 100644
--- a/target/ppc/translate/vsx-impl.c.inc
+++ b/target/ppc/translate/vsx-impl.c.inc
@@ -1422,19 +1422,15 @@ static void glue(gen_, name)(DisasContext *ctx) \
VSX_XXMRG(xxmrghw, 1)
VSX_XXMRG(xxmrglw, 0)
-static void gen_xxsel(DisasContext *ctx)
+static bool trans_XXSEL(DisasContext *ctx, arg_XX4 *a)
{
- int rt = xT(ctx->opcode);
- int ra = xA(ctx->opcode);
- int rb = xB(ctx->opcode);
- int rc = xC(ctx->opcode);
+ REQUIRE_INSNS_FLAGS2(ctx, VSX);
+ REQUIRE_VSX(ctx);
- if (unlikely(!ctx->vsx_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_VSXU);
- return;
- }
- tcg_gen_gvec_bitsel(MO_64, vsr_full_offset(rt), vsr_full_offset(rc),
- vsr_full_offset(rb), vsr_full_offset(ra), 16, 16);
+ tcg_gen_gvec_bitsel(MO_64, vsr_full_offset(a->xt), vsr_full_offset(a->xc),
+ vsr_full_offset(a->xb), vsr_full_offset(a->xa), 16, 16);
+
+ return true;
}
static bool trans_XXSPLTW(DisasContext *ctx, arg_XX2 *a)
@@ -2127,7 +2123,7 @@ static void gen_xxblendv_vec(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b,
tcg_temp_free_vec(tmp);
}
-static bool do_xxblendv(DisasContext *ctx, arg_XX4 *a, unsigned vece)
+static bool do_xxblendv(DisasContext *ctx, arg_8RR_XX4 *a, unsigned vece)
{
static const TCGOpcode vecop_list[] = {
INDEX_op_sari_vec, 0
diff --git a/target/ppc/translate/vsx-ops.c.inc b/target/ppc/translate/vsx-ops.c.inc
index c974324c4c82..b0dbb38c80f6 100644
--- a/target/ppc/translate/vsx-ops.c.inc
+++ b/target/ppc/translate/vsx-ops.c.inc
@@ -347,47 +347,4 @@ GEN_XX3FORM_DM(xxsldwi, 0x08, 0x00),
GEN_XX2FORM_EXT(xxextractuw, 0x0A, 0x0A, PPC2_ISA300),
GEN_XX2FORM_EXT(xxinsertw, 0x0A, 0x0B, PPC2_ISA300),
-#define GEN_XXSEL_ROW(opc3) \
-GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x18, opc3, 0, PPC_NONE, PPC2_VSX), \
-GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x19, opc3, 0, PPC_NONE, PPC2_VSX), \
-GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1A, opc3, 0, PPC_NONE, PPC2_VSX), \
-GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1B, opc3, 0, PPC_NONE, PPC2_VSX), \
-GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1C, opc3, 0, PPC_NONE, PPC2_VSX), \
-GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1D, opc3, 0, PPC_NONE, PPC2_VSX), \
-GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1E, opc3, 0, PPC_NONE, PPC2_VSX), \
-GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1F, opc3, 0, PPC_NONE, PPC2_VSX), \
-
-GEN_XXSEL_ROW(0x00)
-GEN_XXSEL_ROW(0x01)
-GEN_XXSEL_ROW(0x02)
-GEN_XXSEL_ROW(0x03)
-GEN_XXSEL_ROW(0x04)
-GEN_XXSEL_ROW(0x05)
-GEN_XXSEL_ROW(0x06)
-GEN_XXSEL_ROW(0x07)
-GEN_XXSEL_ROW(0x08)
-GEN_XXSEL_ROW(0x09)
-GEN_XXSEL_ROW(0x0A)
-GEN_XXSEL_ROW(0x0B)
-GEN_XXSEL_ROW(0x0C)
-GEN_XXSEL_ROW(0x0D)
-GEN_XXSEL_ROW(0x0E)
-GEN_XXSEL_ROW(0x0F)
-GEN_XXSEL_ROW(0x10)
-GEN_XXSEL_ROW(0x11)
-GEN_XXSEL_ROW(0x12)
-GEN_XXSEL_ROW(0x13)
-GEN_XXSEL_ROW(0x14)
-GEN_XXSEL_ROW(0x15)
-GEN_XXSEL_ROW(0x16)
-GEN_XXSEL_ROW(0x17)
-GEN_XXSEL_ROW(0x18)
-GEN_XXSEL_ROW(0x19)
-GEN_XXSEL_ROW(0x1A)
-GEN_XXSEL_ROW(0x1B)
-GEN_XXSEL_ROW(0x1C)
-GEN_XXSEL_ROW(0x1D)
-GEN_XXSEL_ROW(0x1E)
-GEN_XXSEL_ROW(0x1F)
-
GEN_XX3FORM_DM(xxpermdi, 0x08, 0x01),
--
2.34.1
^ permalink raw reply related [flat|nested] 89+ messages in thread* [PULL 36/87] target/ppc: move xxperm/xxpermr to decodetree
2022-03-02 11:06 [PULL 00/87] ppc queue Cédric Le Goater
` (34 preceding siblings ...)
2022-03-02 11:07 ` [PULL 35/87] target/ppc: Move xxsel " Cédric Le Goater
@ 2022-03-02 11:07 ` Cédric Le Goater
2022-03-02 11:07 ` [PULL 37/87] target/ppc: Move xxpermdi " Cédric Le Goater
` (51 subsequent siblings)
87 siblings, 0 replies; 89+ messages in thread
From: Cédric Le Goater @ 2022-03-02 11:07 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Richard Henderson, Matheus Ferst,
Cédric Le Goater
From: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20220225210936.1749575-31-matheus.ferst@eldorado.org.br>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/helper.h | 2 --
target/ppc/insn32.decode | 5 ++++
target/ppc/fpu_helper.c | 21 ---------------
target/ppc/translate/vsx-impl.c.inc | 42 +++++++++++++++++++++++++++--
target/ppc/translate/vsx-ops.c.inc | 2 --
5 files changed, 45 insertions(+), 27 deletions(-)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 430e75b31f25..233800213658 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -494,8 +494,6 @@ DEF_HELPER_3(xvrspic, void, env, vsr, vsr)
DEF_HELPER_3(xvrspim, void, env, vsr, vsr)
DEF_HELPER_3(xvrspip, void, env, vsr, vsr)
DEF_HELPER_3(xvrspiz, void, env, vsr, vsr)
-DEF_HELPER_4(xxperm, void, env, vsr, vsr, vsr)
-DEF_HELPER_4(xxpermr, void, env, vsr, vsr, vsr)
DEF_HELPER_4(xxextractuw, void, env, vsr, vsr, i32)
DEF_HELPER_4(xxinsertw, void, env, vsr, vsr, i32)
DEF_HELPER_3(xvxsigsp, void, env, vsr, vsr)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 66cb9184cdab..3de4a32e3866 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -604,6 +604,11 @@ STXVPX 011111 ..... ..... ..... 0111001101 - @X_TSXP
XXSPLTIB 111100 ..... 00 ........ 0101101000 . @X_imm8
XXSPLTW 111100 ..... ---.. ..... 010100100 . . @XX2
+## VSX Permute Instructions
+
+XXPERM 111100 ..... ..... ..... 00011010 ... @XX3
+XXPERMR 111100 ..... ..... ..... 00111010 ... @XX3
+
XXSEL 111100 ..... ..... ..... ..... 11 .... @XX4
## VSX Vector Load Special Value Instruction
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
index bd76bee7f1e7..0fd285defc7c 100644
--- a/target/ppc/fpu_helper.c
+++ b/target/ppc/fpu_helper.c
@@ -3055,27 +3055,6 @@ uint64_t helper_xsrsp(CPUPPCState *env, uint64_t xb)
return xt;
}
-#define VSX_XXPERM(op, indexed) \
-void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, \
- ppc_vsr_t *xa, ppc_vsr_t *pcv) \
-{ \
- ppc_vsr_t t = *xt; \
- int i, idx; \
- \
- for (i = 0; i < 16; i++) { \
- idx = pcv->VsrB(i) & 0x1F; \
- if (indexed) { \
- idx = 31 - idx; \
- } \
- t.VsrB(i) = (idx <= 15) ? xa->VsrB(idx) \
- : xt->VsrB(idx - 16); \
- } \
- *xt = t; \
-}
-
-VSX_XXPERM(xxperm, 0)
-VSX_XXPERM(xxpermr, 1)
-
void helper_xvxsigsp(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb)
{
ppc_vsr_t t = { };
diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx-impl.c.inc
index 48e4a2e26645..7ce90f18a502 100644
--- a/target/ppc/translate/vsx-impl.c.inc
+++ b/target/ppc/translate/vsx-impl.c.inc
@@ -1200,8 +1200,46 @@ GEN_VSX_HELPER_X2(xvrspip, 0x12, 0x0A, 0, PPC2_VSX)
GEN_VSX_HELPER_X2(xvrspiz, 0x12, 0x09, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xvtstdcsp, 0x14, 0x1A, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xvtstdcdp, 0x14, 0x1E, 0, PPC2_VSX)
-GEN_VSX_HELPER_X3(xxperm, 0x08, 0x03, 0, PPC2_ISA300)
-GEN_VSX_HELPER_X3(xxpermr, 0x08, 0x07, 0, PPC2_ISA300)
+
+static bool trans_XXPERM(DisasContext *ctx, arg_XX3 *a)
+{
+ TCGv_ptr xt, xa, xb;
+
+ REQUIRE_INSNS_FLAGS2(ctx, ISA300);
+ REQUIRE_VSX(ctx);
+
+ xt = gen_vsr_ptr(a->xt);
+ xa = gen_vsr_ptr(a->xa);
+ xb = gen_vsr_ptr(a->xb);
+
+ gen_helper_VPERM(xt, xa, xt, xb);
+
+ tcg_temp_free_ptr(xt);
+ tcg_temp_free_ptr(xa);
+ tcg_temp_free_ptr(xb);
+
+ return true;
+}
+
+static bool trans_XXPERMR(DisasContext *ctx, arg_XX3 *a)
+{
+ TCGv_ptr xt, xa, xb;
+
+ REQUIRE_INSNS_FLAGS2(ctx, ISA300);
+ REQUIRE_VSX(ctx);
+
+ xt = gen_vsr_ptr(a->xt);
+ xa = gen_vsr_ptr(a->xa);
+ xb = gen_vsr_ptr(a->xb);
+
+ gen_helper_VPERMR(xt, xa, xt, xb);
+
+ tcg_temp_free_ptr(xt);
+ tcg_temp_free_ptr(xa);
+ tcg_temp_free_ptr(xb);
+
+ return true;
+}
#define GEN_VSX_HELPER_VSX_MADD(name, op1, aop, mop, inval, type) \
static void gen_##name(DisasContext *ctx) \
diff --git a/target/ppc/translate/vsx-ops.c.inc b/target/ppc/translate/vsx-ops.c.inc
index b0dbb38c80f6..86ed1a996a53 100644
--- a/target/ppc/translate/vsx-ops.c.inc
+++ b/target/ppc/translate/vsx-ops.c.inc
@@ -341,8 +341,6 @@ VSX_LOGICAL(xxlnand, 0x8, 0x16, PPC2_VSX207),
VSX_LOGICAL(xxlorc, 0x8, 0x15, PPC2_VSX207),
GEN_XX3FORM(xxmrghw, 0x08, 0x02, PPC2_VSX),
GEN_XX3FORM(xxmrglw, 0x08, 0x06, PPC2_VSX),
-GEN_XX3FORM(xxperm, 0x08, 0x03, PPC2_ISA300),
-GEN_XX3FORM(xxpermr, 0x08, 0x07, PPC2_ISA300),
GEN_XX3FORM_DM(xxsldwi, 0x08, 0x00),
GEN_XX2FORM_EXT(xxextractuw, 0x0A, 0x0A, PPC2_ISA300),
GEN_XX2FORM_EXT(xxinsertw, 0x0A, 0x0B, PPC2_ISA300),
--
2.34.1
^ permalink raw reply related [flat|nested] 89+ messages in thread* [PULL 37/87] target/ppc: Move xxpermdi to decodetree
2022-03-02 11:06 [PULL 00/87] ppc queue Cédric Le Goater
` (35 preceding siblings ...)
2022-03-02 11:07 ` [PULL 36/87] target/ppc: move xxperm/xxpermr " Cédric Le Goater
@ 2022-03-02 11:07 ` Cédric Le Goater
2022-03-02 11:07 ` [PULL 38/87] target/ppc: Implement xxpermx instruction Cédric Le Goater
` (50 subsequent siblings)
87 siblings, 0 replies; 89+ messages in thread
From: Cédric Le Goater @ 2022-03-02 11:07 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Richard Henderson, Matheus Ferst,
Cédric Le Goater
From: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20220225210936.1749575-32-matheus.ferst@eldorado.org.br>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/insn32.decode | 4 ++
target/ppc/translate/vsx-impl.c.inc | 71 +++++++++++++----------------
target/ppc/translate/vsx-ops.c.inc | 2 -
3 files changed, 36 insertions(+), 41 deletions(-)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 3de4a32e3866..b8dbac553e33 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -155,6 +155,9 @@
&XX3 xt xa xb
@XX3 ...... ..... ..... ..... ........ ... &XX3 xt=%xx_xt xa=%xx_xa xb=%xx_xb
+&XX3_dm xt xa xb dm
+@XX3_dm ...... ..... ..... ..... . dm:2 ..... ... &XX3_dm xt=%xx_xt xa=%xx_xa xb=%xx_xb
+
&XX4 xt xa xb xc
@XX4 ...... ..... ..... ..... ..... .. .... &XX4 xt=%xx_xt xa=%xx_xa xb=%xx_xb xc=%xx_xc
@@ -608,6 +611,7 @@ XXSPLTW 111100 ..... ---.. ..... 010100100 . . @XX2
XXPERM 111100 ..... ..... ..... 00011010 ... @XX3
XXPERMR 111100 ..... ..... ..... 00111010 ... @XX3
+XXPERMDI 111100 ..... ..... ..... 0 .. 01010 ... @XX3_dm
XXSEL 111100 ..... ..... ..... ..... 11 .... @XX4
diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx-impl.c.inc
index 7ce90f18a502..cdefa1359065 100644
--- a/target/ppc/translate/vsx-impl.c.inc
+++ b/target/ppc/translate/vsx-impl.c.inc
@@ -665,45 +665,6 @@ static void gen_mtvsrws(DisasContext *ctx)
#endif
-static void gen_xxpermdi(DisasContext *ctx)
-{
- TCGv_i64 xh, xl;
-
- if (unlikely(!ctx->vsx_enabled)) {
- gen_exception(ctx, POWERPC_EXCP_VSXU);
- return;
- }
-
- xh = tcg_temp_new_i64();
- xl = tcg_temp_new_i64();
-
- if (unlikely((xT(ctx->opcode) == xA(ctx->opcode)) ||
- (xT(ctx->opcode) == xB(ctx->opcode)))) {
- get_cpu_vsr(xh, xA(ctx->opcode), (DM(ctx->opcode) & 2) == 0);
- get_cpu_vsr(xl, xB(ctx->opcode), (DM(ctx->opcode) & 1) == 0);
-
- set_cpu_vsr(xT(ctx->opcode), xh, true);
- set_cpu_vsr(xT(ctx->opcode), xl, false);
- } else {
- if ((DM(ctx->opcode) & 2) == 0) {
- get_cpu_vsr(xh, xA(ctx->opcode), true);
- set_cpu_vsr(xT(ctx->opcode), xh, true);
- } else {
- get_cpu_vsr(xh, xA(ctx->opcode), false);
- set_cpu_vsr(xT(ctx->opcode), xh, true);
- }
- if ((DM(ctx->opcode) & 1) == 0) {
- get_cpu_vsr(xl, xB(ctx->opcode), true);
- set_cpu_vsr(xT(ctx->opcode), xl, false);
- } else {
- get_cpu_vsr(xl, xB(ctx->opcode), false);
- set_cpu_vsr(xT(ctx->opcode), xl, false);
- }
- }
- tcg_temp_free_i64(xh);
- tcg_temp_free_i64(xl);
-}
-
#define OP_ABS 1
#define OP_NABS 2
#define OP_NEG 3
@@ -1241,6 +1202,38 @@ static bool trans_XXPERMR(DisasContext *ctx, arg_XX3 *a)
return true;
}
+static bool trans_XXPERMDI(DisasContext *ctx, arg_XX3_dm *a)
+{
+ TCGv_i64 t0, t1;
+
+ REQUIRE_INSNS_FLAGS2(ctx, VSX);
+ REQUIRE_VSX(ctx);
+
+ t0 = tcg_temp_new_i64();
+
+ if (unlikely(a->xt == a->xa || a->xt == a->xb)) {
+ t1 = tcg_temp_new_i64();
+
+ get_cpu_vsr(t0, a->xa, (a->dm & 2) == 0);
+ get_cpu_vsr(t1, a->xb, (a->dm & 1) == 0);
+
+ set_cpu_vsr(a->xt, t0, true);
+ set_cpu_vsr(a->xt, t1, false);
+
+ tcg_temp_free_i64(t1);
+ } else {
+ get_cpu_vsr(t0, a->xa, (a->dm & 2) == 0);
+ set_cpu_vsr(a->xt, t0, true);
+
+ get_cpu_vsr(t0, a->xb, (a->dm & 1) == 0);
+ set_cpu_vsr(a->xt, t0, false);
+ }
+
+ tcg_temp_free_i64(t0);
+
+ return true;
+}
+
#define GEN_VSX_HELPER_VSX_MADD(name, op1, aop, mop, inval, type) \
static void gen_##name(DisasContext *ctx) \
{ \
diff --git a/target/ppc/translate/vsx-ops.c.inc b/target/ppc/translate/vsx-ops.c.inc
index 86ed1a996a53..0a6b2b31ac84 100644
--- a/target/ppc/translate/vsx-ops.c.inc
+++ b/target/ppc/translate/vsx-ops.c.inc
@@ -344,5 +344,3 @@ GEN_XX3FORM(xxmrglw, 0x08, 0x06, PPC2_VSX),
GEN_XX3FORM_DM(xxsldwi, 0x08, 0x00),
GEN_XX2FORM_EXT(xxextractuw, 0x0A, 0x0A, PPC2_ISA300),
GEN_XX2FORM_EXT(xxinsertw, 0x0A, 0x0B, PPC2_ISA300),
-
-GEN_XX3FORM_DM(xxpermdi, 0x08, 0x01),
--
2.34.1
^ permalink raw reply related [flat|nested] 89+ messages in thread* [PULL 38/87] target/ppc: Implement xxpermx instruction
2022-03-02 11:06 [PULL 00/87] ppc queue Cédric Le Goater
` (36 preceding siblings ...)
2022-03-02 11:07 ` [PULL 37/87] target/ppc: Move xxpermdi " Cédric Le Goater
@ 2022-03-02 11:07 ` Cédric Le Goater
2022-03-02 11:07 ` [PULL 39/87] tcg/tcg-op-gvec.c: Introduce tcg_gen_gvec_4i Cédric Le Goater
` (49 subsequent siblings)
87 siblings, 0 replies; 89+ messages in thread
From: Cédric Le Goater @ 2022-03-02 11:07 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Richard Henderson, Matheus Ferst,
Cédric Le Goater
From: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20220225210936.1749575-33-matheus.ferst@eldorado.org.br>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/helper.h | 1 +
target/ppc/insn64.decode | 8 ++++++++
target/ppc/int_helper.c | 20 ++++++++++++++++++++
target/ppc/translate/vsx-impl.c.inc | 22 ++++++++++++++++++++++
4 files changed, 51 insertions(+)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 233800213658..7eda74211e66 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -495,6 +495,7 @@ DEF_HELPER_3(xvrspim, void, env, vsr, vsr)
DEF_HELPER_3(xvrspip, void, env, vsr, vsr)
DEF_HELPER_3(xvrspiz, void, env, vsr, vsr)
DEF_HELPER_4(xxextractuw, void, env, vsr, vsr, i32)
+DEF_HELPER_FLAGS_5(XXPERMX, TCG_CALL_NO_RWG, void, vsr, vsr, vsr, vsr, tl)
DEF_HELPER_4(xxinsertw, void, env, vsr, vsr, i32)
DEF_HELPER_3(xvxsigsp, void, env, vsr, vsr)
DEF_HELPER_5(XXBLENDVB, void, vsr, vsr, vsr, vsr, i32)
diff --git a/target/ppc/insn64.decode b/target/ppc/insn64.decode
index 9e4f531fb98b..0963e064b189 100644
--- a/target/ppc/insn64.decode
+++ b/target/ppc/insn64.decode
@@ -54,6 +54,11 @@
...... ..... ..... ..... ..... .. .... \
&8RR_XX4 xt=%8rr_xx_xt xa=%8rr_xx_xa xb=%8rr_xx_xb xc=%8rr_xx_xc
+&8RR_XX4_uim3 xt xa xb xc uim3
+@8RR_XX4_uim3 ...... .. .... .. ............... uim3:3 \
+ ...... ..... ..... ..... ..... .. .... \
+ &8RR_XX4_uim3 xt=%8rr_xx_xt xa=%8rr_xx_xa xb=%8rr_xx_xb xc=%8rr_xx_xc
+
### Fixed-Point Load Instructions
PLBZ 000001 10 0--.-- .................. \
@@ -194,3 +199,6 @@ XXBLENDVH 000001 01 0000 -- ------------------ \
100001 ..... ..... ..... ..... 01 .... @8RR_XX4
XXBLENDVB 000001 01 0000 -- ------------------ \
100001 ..... ..... ..... ..... 00 .... @8RR_XX4
+
+XXPERMX 000001 01 0000 -- --------------- ... \
+ 100010 ..... ..... ..... ..... 00 .... @8RR_XX4_uim3
diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
index 6c63c7b2278c..d9bfdc290fbf 100644
--- a/target/ppc/int_helper.c
+++ b/target/ppc/int_helper.c
@@ -1015,6 +1015,26 @@ VMUL(UW, u32, VsrW, VsrD, uint64_t)
#undef VMUL_DO_ODD
#undef VMUL
+void helper_XXPERMX(ppc_vsr_t *t, ppc_vsr_t *s0, ppc_vsr_t *s1, ppc_vsr_t *pcv,
+ target_ulong uim)
+{
+ int i, idx;
+ ppc_vsr_t tmp = { .u64 = {0, 0} };
+
+ for (i = 0; i < ARRAY_SIZE(t->u8); i++) {
+ if ((pcv->VsrB(i) >> 5) == uim) {
+ idx = pcv->VsrB(i) & 0x1f;
+ if (idx < ARRAY_SIZE(t->u8)) {
+ tmp.VsrB(i) = s0->VsrB(idx);
+ } else {
+ tmp.VsrB(i) = s1->VsrB(idx - ARRAY_SIZE(t->u8));
+ }
+ }
+ }
+
+ *t = tmp;
+}
+
void helper_VPERM(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c)
{
ppc_avr_t result;
diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx-impl.c.inc
index cdefa1359065..92851b8926d8 100644
--- a/target/ppc/translate/vsx-impl.c.inc
+++ b/target/ppc/translate/vsx-impl.c.inc
@@ -1234,6 +1234,28 @@ static bool trans_XXPERMDI(DisasContext *ctx, arg_XX3_dm *a)
return true;
}
+static bool trans_XXPERMX(DisasContext *ctx, arg_8RR_XX4_uim3 *a)
+{
+ TCGv_ptr xt, xa, xb, xc;
+
+ REQUIRE_INSNS_FLAGS2(ctx, ISA310);
+ REQUIRE_VSX(ctx);
+
+ xt = gen_vsr_ptr(a->xt);
+ xa = gen_vsr_ptr(a->xa);
+ xb = gen_vsr_ptr(a->xb);
+ xc = gen_vsr_ptr(a->xc);
+
+ gen_helper_XXPERMX(xt, xa, xb, xc, tcg_constant_tl(a->uim3));
+
+ tcg_temp_free_ptr(xt);
+ tcg_temp_free_ptr(xa);
+ tcg_temp_free_ptr(xb);
+ tcg_temp_free_ptr(xc);
+
+ return true;
+}
+
#define GEN_VSX_HELPER_VSX_MADD(name, op1, aop, mop, inval, type) \
static void gen_##name(DisasContext *ctx) \
{ \
--
2.34.1
^ permalink raw reply related [flat|nested] 89+ messages in thread* [PULL 39/87] tcg/tcg-op-gvec.c: Introduce tcg_gen_gvec_4i
2022-03-02 11:06 [PULL 00/87] ppc queue Cédric Le Goater
` (37 preceding siblings ...)
2022-03-02 11:07 ` [PULL 38/87] target/ppc: Implement xxpermx instruction Cédric Le Goater
@ 2022-03-02 11:07 ` Cédric Le Goater
2022-03-02 11:07 ` [PULL 40/87] target/ppc: Implement xxeval Cédric Le Goater
` (48 subsequent siblings)
87 siblings, 0 replies; 89+ messages in thread
From: Cédric Le Goater @ 2022-03-02 11:07 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Richard Henderson, Matheus Ferst,
Cédric Le Goater
From: Matheus Ferst <matheus.ferst@eldorado.org.br>
Following the implementation of tcg_gen_gvec_3i, add a four-vector and
immediate operand expansion method.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20220225210936.1749575-34-matheus.ferst@eldorado.org.br>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
include/tcg/tcg-op-gvec.h | 22 ++++++
tcg/tcg-op-gvec.c | 146 ++++++++++++++++++++++++++++++++++++++
2 files changed, 168 insertions(+)
diff --git a/include/tcg/tcg-op-gvec.h b/include/tcg/tcg-op-gvec.h
index da55fed8704a..28cafbcc5ce0 100644
--- a/include/tcg/tcg-op-gvec.h
+++ b/include/tcg/tcg-op-gvec.h
@@ -218,6 +218,25 @@ typedef struct {
bool write_aofs;
} GVecGen4;
+typedef struct {
+ /*
+ * Expand inline as a 64-bit or 32-bit integer. Only one of these will be
+ * non-NULL.
+ */
+ void (*fni8)(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_i64, int64_t);
+ void (*fni4)(TCGv_i32, TCGv_i32, TCGv_i32, TCGv_i32, int32_t);
+ /* Expand inline with a host vector type. */
+ void (*fniv)(unsigned, TCGv_vec, TCGv_vec, TCGv_vec, TCGv_vec, int64_t);
+ /* Expand out-of-line helper w/descriptor, data in descriptor. */
+ gen_helper_gvec_4 *fno;
+ /* The optional opcodes, if any, utilized by .fniv. */
+ const TCGOpcode *opt_opc;
+ /* The vector element size, if applicable. */
+ uint8_t vece;
+ /* Prefer i64 to v64. */
+ bool prefer_i64;
+} GVecGen4i;
+
void tcg_gen_gvec_2(uint32_t dofs, uint32_t aofs,
uint32_t oprsz, uint32_t maxsz, const GVecGen2 *);
void tcg_gen_gvec_2i(uint32_t dofs, uint32_t aofs, uint32_t oprsz,
@@ -231,6 +250,9 @@ void tcg_gen_gvec_3i(uint32_t dofs, uint32_t aofs, uint32_t bofs,
const GVecGen3i *);
void tcg_gen_gvec_4(uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t cofs,
uint32_t oprsz, uint32_t maxsz, const GVecGen4 *);
+void tcg_gen_gvec_4i(uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t cofs,
+ uint32_t oprsz, uint32_t maxsz, int64_t c,
+ const GVecGen4i *);
/* Expand a specific vector operation. */
diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c
index ffe55e908f8a..079a761b0402 100644
--- a/tcg/tcg-op-gvec.c
+++ b/tcg/tcg-op-gvec.c
@@ -836,6 +836,30 @@ static void expand_4_i32(uint32_t dofs, uint32_t aofs, uint32_t bofs,
tcg_temp_free_i32(t0);
}
+static void expand_4i_i32(uint32_t dofs, uint32_t aofs, uint32_t bofs,
+ uint32_t cofs, uint32_t oprsz, int32_t c,
+ void (*fni)(TCGv_i32, TCGv_i32, TCGv_i32, TCGv_i32,
+ int32_t))
+{
+ TCGv_i32 t0 = tcg_temp_new_i32();
+ TCGv_i32 t1 = tcg_temp_new_i32();
+ TCGv_i32 t2 = tcg_temp_new_i32();
+ TCGv_i32 t3 = tcg_temp_new_i32();
+ uint32_t i;
+
+ for (i = 0; i < oprsz; i += 4) {
+ tcg_gen_ld_i32(t1, cpu_env, aofs + i);
+ tcg_gen_ld_i32(t2, cpu_env, bofs + i);
+ tcg_gen_ld_i32(t3, cpu_env, cofs + i);
+ fni(t0, t1, t2, t3, c);
+ tcg_gen_st_i32(t0, cpu_env, dofs + i);
+ }
+ tcg_temp_free_i32(t3);
+ tcg_temp_free_i32(t2);
+ tcg_temp_free_i32(t1);
+ tcg_temp_free_i32(t0);
+}
+
/* Expand OPSZ bytes worth of two-operand operations using i64 elements. */
static void expand_2_i64(uint32_t dofs, uint32_t aofs, uint32_t oprsz,
bool load_dest, void (*fni)(TCGv_i64, TCGv_i64))
@@ -971,6 +995,30 @@ static void expand_4_i64(uint32_t dofs, uint32_t aofs, uint32_t bofs,
tcg_temp_free_i64(t0);
}
+static void expand_4i_i64(uint32_t dofs, uint32_t aofs, uint32_t bofs,
+ uint32_t cofs, uint32_t oprsz, int64_t c,
+ void (*fni)(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_i64,
+ int64_t))
+{
+ TCGv_i64 t0 = tcg_temp_new_i64();
+ TCGv_i64 t1 = tcg_temp_new_i64();
+ TCGv_i64 t2 = tcg_temp_new_i64();
+ TCGv_i64 t3 = tcg_temp_new_i64();
+ uint32_t i;
+
+ for (i = 0; i < oprsz; i += 8) {
+ tcg_gen_ld_i64(t1, cpu_env, aofs + i);
+ tcg_gen_ld_i64(t2, cpu_env, bofs + i);
+ tcg_gen_ld_i64(t3, cpu_env, cofs + i);
+ fni(t0, t1, t2, t3, c);
+ tcg_gen_st_i64(t0, cpu_env, dofs + i);
+ }
+ tcg_temp_free_i64(t3);
+ tcg_temp_free_i64(t2);
+ tcg_temp_free_i64(t1);
+ tcg_temp_free_i64(t0);
+}
+
/* Expand OPSZ bytes worth of two-operand operations using host vectors. */
static void expand_2_vec(unsigned vece, uint32_t dofs, uint32_t aofs,
uint32_t oprsz, uint32_t tysz, TCGType type,
@@ -1121,6 +1169,35 @@ static void expand_4_vec(unsigned vece, uint32_t dofs, uint32_t aofs,
tcg_temp_free_vec(t0);
}
+/*
+ * Expand OPSZ bytes worth of four-vector operands and an immediate operand
+ * using host vectors.
+ */
+static void expand_4i_vec(unsigned vece, uint32_t dofs, uint32_t aofs,
+ uint32_t bofs, uint32_t cofs, uint32_t oprsz,
+ uint32_t tysz, TCGType type, int64_t c,
+ void (*fni)(unsigned, TCGv_vec, TCGv_vec,
+ TCGv_vec, TCGv_vec, int64_t))
+{
+ TCGv_vec t0 = tcg_temp_new_vec(type);
+ TCGv_vec t1 = tcg_temp_new_vec(type);
+ TCGv_vec t2 = tcg_temp_new_vec(type);
+ TCGv_vec t3 = tcg_temp_new_vec(type);
+ uint32_t i;
+
+ for (i = 0; i < oprsz; i += tysz) {
+ tcg_gen_ld_vec(t1, cpu_env, aofs + i);
+ tcg_gen_ld_vec(t2, cpu_env, bofs + i);
+ tcg_gen_ld_vec(t3, cpu_env, cofs + i);
+ fni(vece, t0, t1, t2, t3, c);
+ tcg_gen_st_vec(t0, cpu_env, dofs + i);
+ }
+ tcg_temp_free_vec(t3);
+ tcg_temp_free_vec(t2);
+ tcg_temp_free_vec(t1);
+ tcg_temp_free_vec(t0);
+}
+
/* Expand a vector two-operand operation. */
void tcg_gen_gvec_2(uint32_t dofs, uint32_t aofs,
uint32_t oprsz, uint32_t maxsz, const GVecGen2 *g)
@@ -1533,6 +1610,75 @@ void tcg_gen_gvec_4(uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t cofs,
}
}
+/* Expand a vector four-operand operation. */
+void tcg_gen_gvec_4i(uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t cofs,
+ uint32_t oprsz, uint32_t maxsz, int64_t c,
+ const GVecGen4i *g)
+{
+ const TCGOpcode *this_list = g->opt_opc ? : vecop_list_empty;
+ const TCGOpcode *hold_list = tcg_swap_vecop_list(this_list);
+ TCGType type;
+ uint32_t some;
+
+ check_size_align(oprsz, maxsz, dofs | aofs | bofs | cofs);
+ check_overlap_4(dofs, aofs, bofs, cofs, maxsz);
+
+ type = 0;
+ if (g->fniv) {
+ type = choose_vector_type(g->opt_opc, g->vece, oprsz, g->prefer_i64);
+ }
+ switch (type) {
+ case TCG_TYPE_V256:
+ /*
+ * Recall that ARM SVE allows vector sizes that are not a
+ * power of 2, but always a multiple of 16. The intent is
+ * that e.g. size == 80 would be expanded with 2x32 + 1x16.
+ */
+ some = QEMU_ALIGN_DOWN(oprsz, 32);
+ expand_4i_vec(g->vece, dofs, aofs, bofs, cofs, some,
+ 32, TCG_TYPE_V256, c, g->fniv);
+ if (some == oprsz) {
+ break;
+ }
+ dofs += some;
+ aofs += some;
+ bofs += some;
+ cofs += some;
+ oprsz -= some;
+ maxsz -= some;
+ /* fallthru */
+ case TCG_TYPE_V128:
+ expand_4i_vec(g->vece, dofs, aofs, bofs, cofs, oprsz,
+ 16, TCG_TYPE_V128, c, g->fniv);
+ break;
+ case TCG_TYPE_V64:
+ expand_4i_vec(g->vece, dofs, aofs, bofs, cofs, oprsz,
+ 8, TCG_TYPE_V64, c, g->fniv);
+ break;
+
+ case 0:
+ if (g->fni8 && check_size_impl(oprsz, 8)) {
+ expand_4i_i64(dofs, aofs, bofs, cofs, oprsz, c, g->fni8);
+ } else if (g->fni4 && check_size_impl(oprsz, 4)) {
+ expand_4i_i32(dofs, aofs, bofs, cofs, oprsz, c, g->fni4);
+ } else {
+ assert(g->fno != NULL);
+ tcg_gen_gvec_4_ool(dofs, aofs, bofs, cofs,
+ oprsz, maxsz, c, g->fno);
+ oprsz = maxsz;
+ }
+ break;
+
+ default:
+ g_assert_not_reached();
+ }
+ tcg_swap_vecop_list(hold_list);
+
+ if (oprsz < maxsz) {
+ expand_clr(dofs + oprsz, maxsz - oprsz);
+ }
+}
+
/*
* Expand specific vector operations.
*/
--
2.34.1
^ permalink raw reply related [flat|nested] 89+ messages in thread* [PULL 40/87] target/ppc: Implement xxeval
2022-03-02 11:06 [PULL 00/87] ppc queue Cédric Le Goater
` (38 preceding siblings ...)
2022-03-02 11:07 ` [PULL 39/87] tcg/tcg-op-gvec.c: Introduce tcg_gen_gvec_4i Cédric Le Goater
@ 2022-03-02 11:07 ` Cédric Le Goater
2022-03-02 11:07 ` [PULL 41/87] target/ppc: Implement xxgenpcv[bhwd]m instruction Cédric Le Goater
` (47 subsequent siblings)
87 siblings, 0 replies; 89+ messages in thread
From: Cédric Le Goater @ 2022-03-02 11:07 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Richard Henderson, Matheus Ferst,
Cédric Le Goater
From: Matheus Ferst <matheus.ferst@eldorado.org.br>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220225210936.1749575-35-matheus.ferst@eldorado.org.br>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/helper.h | 1 +
target/ppc/insn64.decode | 8 +
target/ppc/int_helper.c | 42 ++++++
target/ppc/translate/vsx-impl.c.inc | 220 ++++++++++++++++++++++++++++
4 files changed, 271 insertions(+)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 7eda74211e66..13034bca58c7 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -498,6 +498,7 @@ DEF_HELPER_4(xxextractuw, void, env, vsr, vsr, i32)
DEF_HELPER_FLAGS_5(XXPERMX, TCG_CALL_NO_RWG, void, vsr, vsr, vsr, vsr, tl)
DEF_HELPER_4(xxinsertw, void, env, vsr, vsr, i32)
DEF_HELPER_3(xvxsigsp, void, env, vsr, vsr)
+DEF_HELPER_FLAGS_5(XXEVAL, TCG_CALL_NO_RWG, void, vsr, vsr, vsr, vsr, i32)
DEF_HELPER_5(XXBLENDVB, void, vsr, vsr, vsr, vsr, i32)
DEF_HELPER_5(XXBLENDVH, void, vsr, vsr, vsr, vsr, i32)
DEF_HELPER_5(XXBLENDVW, void, vsr, vsr, vsr, vsr, i32)
diff --git a/target/ppc/insn64.decode b/target/ppc/insn64.decode
index 0963e064b189..fdb859f62dd8 100644
--- a/target/ppc/insn64.decode
+++ b/target/ppc/insn64.decode
@@ -54,6 +54,11 @@
...... ..... ..... ..... ..... .. .... \
&8RR_XX4 xt=%8rr_xx_xt xa=%8rr_xx_xa xb=%8rr_xx_xb xc=%8rr_xx_xc
+&8RR_XX4_imm xt xa xb xc imm
+@8RR_XX4_imm ........ ........ ........ imm:8 \
+ ...... ..... ..... ..... ..... .. .... \
+ &8RR_XX4_imm xt=%8rr_xx_xt xa=%8rr_xx_xa xb=%8rr_xx_xb xc=%8rr_xx_xc
+
&8RR_XX4_uim3 xt xa xb xc uim3
@8RR_XX4_uim3 ...... .. .... .. ............... uim3:3 \
...... ..... ..... ..... ..... .. .... \
@@ -184,6 +189,9 @@ PLXVP 000001 00 0--.-- .................. \
PSTXVP 000001 00 0--.-- .................. \
111110 ..... ..... ................ @8LS_D_TSXP
+XXEVAL 000001 01 0000 -- ---------- ........ \
+ 100010 ..... ..... ..... ..... 01 .... @8RR_XX4_imm
+
XXSPLTIDP 000001 01 0000 -- -- ................ \
100000 ..... 0010 . ................ @8RR_D
XXSPLTIW 000001 01 0000 -- -- ................ \
diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
index d9bfdc290fbf..ca59cd3d79ec 100644
--- a/target/ppc/int_helper.c
+++ b/target/ppc/int_helper.c
@@ -28,6 +28,7 @@
#include "fpu/softfloat.h"
#include "qapi/error.h"
#include "qemu/guest-random.h"
+#include "tcg/tcg-gvec-desc.h"
#include "helper_regs.h"
/*****************************************************************************/
@@ -1572,6 +1573,47 @@ void helper_xxinsertw(CPUPPCState *env, ppc_vsr_t *xt,
*xt = t;
}
+void helper_XXEVAL(ppc_avr_t *t, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c,
+ uint32_t desc)
+{
+ /*
+ * Instead of processing imm bit-by-bit, we'll skip the computation of
+ * conjunctions whose corresponding bit is unset.
+ */
+ int bit, imm = simd_data(desc);
+ Int128 conj, disj = int128_zero();
+
+ /* Iterate over set bits from the least to the most significant bit */
+ while (imm) {
+ /*
+ * Get the next bit to be processed with ctz64. Invert the result of
+ * ctz64 to match the indexing used by PowerISA.
+ */
+ bit = 7 - ctzl(imm);
+ if (bit & 0x4) {
+ conj = a->s128;
+ } else {
+ conj = int128_not(a->s128);
+ }
+ if (bit & 0x2) {
+ conj = int128_and(conj, b->s128);
+ } else {
+ conj = int128_and(conj, int128_not(b->s128));
+ }
+ if (bit & 0x1) {
+ conj = int128_and(conj, c->s128);
+ } else {
+ conj = int128_and(conj, int128_not(c->s128));
+ }
+ disj = int128_or(disj, conj);
+
+ /* Unset the least significant bit that is set */
+ imm &= imm - 1;
+ }
+
+ t->s128 = disj;
+}
+
#define XXBLEND(name, sz) \
void glue(helper_XXBLENDV, name)(ppc_avr_t *t, ppc_avr_t *a, ppc_avr_t *b, \
ppc_avr_t *c, uint32_t desc) \
diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx-impl.c.inc
index 92851b8926d8..b5e07cf3df32 100644
--- a/target/ppc/translate/vsx-impl.c.inc
+++ b/target/ppc/translate/vsx-impl.c.inc
@@ -2167,6 +2167,226 @@ TRANS64_FLAGS2(ISA310, PLXV, do_lstxv_PLS_D, false, false)
TRANS64_FLAGS2(ISA310, PSTXVP, do_lstxv_PLS_D, true, true)
TRANS64_FLAGS2(ISA310, PLXVP, do_lstxv_PLS_D, false, true)
+static void gen_xxeval_i64(TCGv_i64 t, TCGv_i64 a, TCGv_i64 b, TCGv_i64 c,
+ int64_t imm)
+{
+ /*
+ * Instead of processing imm bit-by-bit, we'll skip the computation of
+ * conjunctions whose corresponding bit is unset.
+ */
+ int bit;
+ TCGv_i64 conj, disj;
+
+ conj = tcg_temp_new_i64();
+ disj = tcg_const_i64(0);
+
+ /* Iterate over set bits from the least to the most significant bit */
+ while (imm) {
+ /*
+ * Get the next bit to be processed with ctz64. Invert the result of
+ * ctz64 to match the indexing used by PowerISA.
+ */
+ bit = 7 - ctz64(imm);
+ if (bit & 0x4) {
+ tcg_gen_mov_i64(conj, a);
+ } else {
+ tcg_gen_not_i64(conj, a);
+ }
+ if (bit & 0x2) {
+ tcg_gen_and_i64(conj, conj, b);
+ } else {
+ tcg_gen_andc_i64(conj, conj, b);
+ }
+ if (bit & 0x1) {
+ tcg_gen_and_i64(conj, conj, c);
+ } else {
+ tcg_gen_andc_i64(conj, conj, c);
+ }
+ tcg_gen_or_i64(disj, disj, conj);
+
+ /* Unset the least significant bit that is set */
+ imm &= imm - 1;
+ }
+
+ tcg_gen_mov_i64(t, disj);
+
+ tcg_temp_free_i64(conj);
+ tcg_temp_free_i64(disj);
+}
+
+static void gen_xxeval_vec(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b,
+ TCGv_vec c, int64_t imm)
+{
+ /*
+ * Instead of processing imm bit-by-bit, we'll skip the computation of
+ * conjunctions whose corresponding bit is unset.
+ */
+ int bit;
+ TCGv_vec disj, conj;
+
+ disj = tcg_const_zeros_vec_matching(t);
+ conj = tcg_temp_new_vec_matching(t);
+
+ /* Iterate over set bits from the least to the most significant bit */
+ while (imm) {
+ /*
+ * Get the next bit to be processed with ctz64. Invert the result of
+ * ctz64 to match the indexing used by PowerISA.
+ */
+ bit = 7 - ctz64(imm);
+ if (bit & 0x4) {
+ tcg_gen_mov_vec(conj, a);
+ } else {
+ tcg_gen_not_vec(vece, conj, a);
+ }
+ if (bit & 0x2) {
+ tcg_gen_and_vec(vece, conj, conj, b);
+ } else {
+ tcg_gen_andc_vec(vece, conj, conj, b);
+ }
+ if (bit & 0x1) {
+ tcg_gen_and_vec(vece, conj, conj, c);
+ } else {
+ tcg_gen_andc_vec(vece, conj, conj, c);
+ }
+ tcg_gen_or_vec(vece, disj, disj, conj);
+
+ /* Unset the least significant bit that is set */
+ imm &= imm - 1;
+ }
+
+ tcg_gen_mov_vec(t, disj);
+
+ tcg_temp_free_vec(disj);
+ tcg_temp_free_vec(conj);
+}
+
+static bool trans_XXEVAL(DisasContext *ctx, arg_8RR_XX4_imm *a)
+{
+ static const TCGOpcode vecop_list[] = {
+ INDEX_op_andc_vec, 0
+ };
+ static const GVecGen4i op = {
+ .fniv = gen_xxeval_vec,
+ .fno = gen_helper_XXEVAL,
+ .fni8 = gen_xxeval_i64,
+ .opt_opc = vecop_list,
+ .vece = MO_64
+ };
+ int xt = vsr_full_offset(a->xt), xa = vsr_full_offset(a->xa),
+ xb = vsr_full_offset(a->xb), xc = vsr_full_offset(a->xc);
+
+ REQUIRE_INSNS_FLAGS2(ctx, ISA310);
+ REQUIRE_VSX(ctx);
+
+ /* Equivalent functions that can be implemented with a single gen_gvec */
+ switch (a->imm) {
+ case 0b00000000: /* true */
+ set_cpu_vsr(a->xt, tcg_constant_i64(0), true);
+ set_cpu_vsr(a->xt, tcg_constant_i64(0), false);
+ break;
+ case 0b00000011: /* and(B,A) */
+ tcg_gen_gvec_and(MO_64, xt, xb, xa, 16, 16);
+ break;
+ case 0b00000101: /* and(C,A) */
+ tcg_gen_gvec_and(MO_64, xt, xc, xa, 16, 16);
+ break;
+ case 0b00001111: /* A */
+ tcg_gen_gvec_mov(MO_64, xt, xa, 16, 16);
+ break;
+ case 0b00010001: /* and(C,B) */
+ tcg_gen_gvec_and(MO_64, xt, xc, xb, 16, 16);
+ break;
+ case 0b00011011: /* C?B:A */
+ tcg_gen_gvec_bitsel(MO_64, xt, xc, xb, xa, 16, 16);
+ break;
+ case 0b00011101: /* B?C:A */
+ tcg_gen_gvec_bitsel(MO_64, xt, xb, xc, xa, 16, 16);
+ break;
+ case 0b00100111: /* C?A:B */
+ tcg_gen_gvec_bitsel(MO_64, xt, xc, xa, xb, 16, 16);
+ break;
+ case 0b00110011: /* B */
+ tcg_gen_gvec_mov(MO_64, xt, xb, 16, 16);
+ break;
+ case 0b00110101: /* A?C:B */
+ tcg_gen_gvec_bitsel(MO_64, xt, xa, xc, xb, 16, 16);
+ break;
+ case 0b00111100: /* xor(B,A) */
+ tcg_gen_gvec_xor(MO_64, xt, xb, xa, 16, 16);
+ break;
+ case 0b00111111: /* or(B,A) */
+ tcg_gen_gvec_or(MO_64, xt, xb, xa, 16, 16);
+ break;
+ case 0b01000111: /* B?A:C */
+ tcg_gen_gvec_bitsel(MO_64, xt, xb, xa, xc, 16, 16);
+ break;
+ case 0b01010011: /* A?B:C */
+ tcg_gen_gvec_bitsel(MO_64, xt, xa, xb, xc, 16, 16);
+ break;
+ case 0b01010101: /* C */
+ tcg_gen_gvec_mov(MO_64, xt, xc, 16, 16);
+ break;
+ case 0b01011010: /* xor(C,A) */
+ tcg_gen_gvec_xor(MO_64, xt, xc, xa, 16, 16);
+ break;
+ case 0b01011111: /* or(C,A) */
+ tcg_gen_gvec_or(MO_64, xt, xc, xa, 16, 16);
+ break;
+ case 0b01100110: /* xor(C,B) */
+ tcg_gen_gvec_xor(MO_64, xt, xc, xb, 16, 16);
+ break;
+ case 0b01110111: /* or(C,B) */
+ tcg_gen_gvec_or(MO_64, xt, xc, xb, 16, 16);
+ break;
+ case 0b10001000: /* nor(C,B) */
+ tcg_gen_gvec_nor(MO_64, xt, xc, xb, 16, 16);
+ break;
+ case 0b10011001: /* eqv(C,B) */
+ tcg_gen_gvec_eqv(MO_64, xt, xc, xb, 16, 16);
+ break;
+ case 0b10100000: /* nor(C,A) */
+ tcg_gen_gvec_nor(MO_64, xt, xc, xa, 16, 16);
+ break;
+ case 0b10100101: /* eqv(C,A) */
+ tcg_gen_gvec_eqv(MO_64, xt, xc, xa, 16, 16);
+ break;
+ case 0b10101010: /* not(C) */
+ tcg_gen_gvec_not(MO_64, xt, xc, 16, 16);
+ break;
+ case 0b11000000: /* nor(B,A) */
+ tcg_gen_gvec_nor(MO_64, xt, xb, xa, 16, 16);
+ break;
+ case 0b11000011: /* eqv(B,A) */
+ tcg_gen_gvec_eqv(MO_64, xt, xb, xa, 16, 16);
+ break;
+ case 0b11001100: /* not(B) */
+ tcg_gen_gvec_not(MO_64, xt, xb, 16, 16);
+ break;
+ case 0b11101110: /* nand(C,B) */
+ tcg_gen_gvec_nand(MO_64, xt, xc, xb, 16, 16);
+ break;
+ case 0b11110000: /* not(A) */
+ tcg_gen_gvec_not(MO_64, xt, xa, 16, 16);
+ break;
+ case 0b11111010: /* nand(C,A) */
+ tcg_gen_gvec_nand(MO_64, xt, xc, xa, 16, 16);
+ break;
+ case 0b11111100: /* nand(B,A) */
+ tcg_gen_gvec_nand(MO_64, xt, xb, xa, 16, 16);
+ break;
+ case 0b11111111: /* true */
+ set_cpu_vsr(a->xt, tcg_constant_i64(-1), true);
+ set_cpu_vsr(a->xt, tcg_constant_i64(-1), false);
+ break;
+ default:
+ /* Fallback to compute all conjunctions/disjunctions */
+ tcg_gen_gvec_4i(xt, xa, xb, xc, 16, 16, a->imm, &op);
+ }
+
+ return true;
+}
+
static void gen_xxblendv_vec(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b,
TCGv_vec c)
{
--
2.34.1
^ permalink raw reply related [flat|nested] 89+ messages in thread* [PULL 41/87] target/ppc: Implement xxgenpcv[bhwd]m instruction
2022-03-02 11:06 [PULL 00/87] ppc queue Cédric Le Goater
` (39 preceding siblings ...)
2022-03-02 11:07 ` [PULL 40/87] target/ppc: Implement xxeval Cédric Le Goater
@ 2022-03-02 11:07 ` Cédric Le Goater
2022-03-02 11:07 ` [PULL 42/87] target/ppc: move xs[n]madd[am][ds]p/xs[n]msub[am][ds]p to decodetree Cédric Le Goater
` (46 subsequent siblings)
87 siblings, 0 replies; 89+ messages in thread
From: Cédric Le Goater @ 2022-03-02 11:07 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Richard Henderson, Matheus Ferst,
Cédric Le Goater
From: Matheus Ferst <matheus.ferst@eldorado.org.br>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220225210936.1749575-36-matheus.ferst@eldorado.org.br>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/helper.h | 16 +++++
target/ppc/insn32.decode | 10 ++++
target/ppc/int_helper.c | 91 +++++++++++++++++++++++++++++
target/ppc/translate/vsx-impl.c.inc | 43 ++++++++++++++
4 files changed, 160 insertions(+)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 13034bca58c7..008cd6405d0f 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -494,6 +494,22 @@ DEF_HELPER_3(xvrspic, void, env, vsr, vsr)
DEF_HELPER_3(xvrspim, void, env, vsr, vsr)
DEF_HELPER_3(xvrspip, void, env, vsr, vsr)
DEF_HELPER_3(xvrspiz, void, env, vsr, vsr)
+DEF_HELPER_FLAGS_2(XXGENPCVBM_be_exp, TCG_CALL_NO_RWG, void, vsr, avr)
+DEF_HELPER_FLAGS_2(XXGENPCVBM_be_comp, TCG_CALL_NO_RWG, void, vsr, avr)
+DEF_HELPER_FLAGS_2(XXGENPCVBM_le_exp, TCG_CALL_NO_RWG, void, vsr, avr)
+DEF_HELPER_FLAGS_2(XXGENPCVBM_le_comp, TCG_CALL_NO_RWG, void, vsr, avr)
+DEF_HELPER_FLAGS_2(XXGENPCVHM_be_exp, TCG_CALL_NO_RWG, void, vsr, avr)
+DEF_HELPER_FLAGS_2(XXGENPCVHM_be_comp, TCG_CALL_NO_RWG, void, vsr, avr)
+DEF_HELPER_FLAGS_2(XXGENPCVHM_le_exp, TCG_CALL_NO_RWG, void, vsr, avr)
+DEF_HELPER_FLAGS_2(XXGENPCVHM_le_comp, TCG_CALL_NO_RWG, void, vsr, avr)
+DEF_HELPER_FLAGS_2(XXGENPCVWM_be_exp, TCG_CALL_NO_RWG, void, vsr, avr)
+DEF_HELPER_FLAGS_2(XXGENPCVWM_be_comp, TCG_CALL_NO_RWG, void, vsr, avr)
+DEF_HELPER_FLAGS_2(XXGENPCVWM_le_exp, TCG_CALL_NO_RWG, void, vsr, avr)
+DEF_HELPER_FLAGS_2(XXGENPCVWM_le_comp, TCG_CALL_NO_RWG, void, vsr, avr)
+DEF_HELPER_FLAGS_2(XXGENPCVDM_be_exp, TCG_CALL_NO_RWG, void, vsr, avr)
+DEF_HELPER_FLAGS_2(XXGENPCVDM_be_comp, TCG_CALL_NO_RWG, void, vsr, avr)
+DEF_HELPER_FLAGS_2(XXGENPCVDM_le_exp, TCG_CALL_NO_RWG, void, vsr, avr)
+DEF_HELPER_FLAGS_2(XXGENPCVDM_le_comp, TCG_CALL_NO_RWG, void, vsr, avr)
DEF_HELPER_4(xxextractuw, void, env, vsr, vsr, i32)
DEF_HELPER_FLAGS_5(XXPERMX, TCG_CALL_NO_RWG, void, vsr, vsr, vsr, vsr, tl)
DEF_HELPER_4(xxinsertw, void, env, vsr, vsr, i32)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index b8dbac553e33..22b245607b0f 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -119,6 +119,9 @@
@X_bfl ...... bf:3 - l:1 ra:5 rb:5 ..........- &X_bfl
%x_xt 0:1 21:5
+&X_imm5 xt imm:uint8_t vrb
+@X_imm5 ...... ..... imm:5 vrb:5 .......... . &X_imm5 xt=%x_xt
+
&X_imm8 xt imm:uint8_t
@X_imm8 ...... ..... .. imm:8 .......... . &X_imm8 xt=%x_xt
@@ -615,6 +618,13 @@ XXPERMDI 111100 ..... ..... ..... 0 .. 01010 ... @XX3_dm
XXSEL 111100 ..... ..... ..... ..... 11 .... @XX4
+## VSX Vector Generate PCV
+
+XXGENPCVBM 111100 ..... ..... ..... 1110010100 . @X_imm5
+XXGENPCVHM 111100 ..... ..... ..... 1110010101 . @X_imm5
+XXGENPCVWM 111100 ..... ..... ..... 1110110100 . @X_imm5
+XXGENPCVDM 111100 ..... ..... ..... 1110110101 . @X_imm5
+
## VSX Vector Load Special Value Instruction
LXVKQ 111100 ..... 11111 ..... 0101101000 . @X_uim5
diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
index ca59cd3d79ec..b2b17bb1ca5e 100644
--- a/target/ppc/int_helper.c
+++ b/target/ppc/int_helper.c
@@ -1072,6 +1072,97 @@ void helper_VPERMR(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c)
*r = result;
}
+#define XXGENPCV(NAME, SZ) \
+void glue(helper_, glue(NAME, _be_exp))(ppc_vsr_t *t, ppc_vsr_t *b) \
+{ \
+ ppc_vsr_t tmp; \
+ \
+ /* Initialize tmp with the result of an all-zeros mask */ \
+ tmp.VsrD(0) = 0x1011121314151617; \
+ tmp.VsrD(1) = 0x18191A1B1C1D1E1F; \
+ \
+ /* Iterate over the most significant byte of each element */ \
+ for (int i = 0, j = 0; i < ARRAY_SIZE(b->u8); i += SZ) { \
+ if (b->VsrB(i) & 0x80) { \
+ /* Update each byte of the element */ \
+ for (int k = 0; k < SZ; k++) { \
+ tmp.VsrB(i + k) = j + k; \
+ } \
+ j += SZ; \
+ } \
+ } \
+ \
+ *t = tmp; \
+} \
+ \
+void glue(helper_, glue(NAME, _be_comp))(ppc_vsr_t *t, ppc_vsr_t *b)\
+{ \
+ ppc_vsr_t tmp = { .u64 = { 0, 0 } }; \
+ \
+ /* Iterate over the most significant byte of each element */ \
+ for (int i = 0, j = 0; i < ARRAY_SIZE(b->u8); i += SZ) { \
+ if (b->VsrB(i) & 0x80) { \
+ /* Update each byte of the element */ \
+ for (int k = 0; k < SZ; k++) { \
+ tmp.VsrB(j + k) = i + k; \
+ } \
+ j += SZ; \
+ } \
+ } \
+ \
+ *t = tmp; \
+} \
+ \
+void glue(helper_, glue(NAME, _le_exp))(ppc_vsr_t *t, ppc_vsr_t *b) \
+{ \
+ ppc_vsr_t tmp; \
+ \
+ /* Initialize tmp with the result of an all-zeros mask */ \
+ tmp.VsrD(0) = 0x1F1E1D1C1B1A1918; \
+ tmp.VsrD(1) = 0x1716151413121110; \
+ \
+ /* Iterate over the most significant byte of each element */ \
+ for (int i = 0, j = 0; i < ARRAY_SIZE(b->u8); i += SZ) { \
+ /* Reverse indexing of "i" */ \
+ const int idx = ARRAY_SIZE(b->u8) - i - SZ; \
+ if (b->VsrB(idx) & 0x80) { \
+ /* Update each byte of the element */ \
+ for (int k = 0, rk = SZ - 1; k < SZ; k++, rk--) { \
+ tmp.VsrB(idx + rk) = j + k; \
+ } \
+ j += SZ; \
+ } \
+ } \
+ \
+ *t = tmp; \
+} \
+ \
+void glue(helper_, glue(NAME, _le_comp))(ppc_vsr_t *t, ppc_vsr_t *b)\
+{ \
+ ppc_vsr_t tmp = { .u64 = { 0, 0 } }; \
+ \
+ /* Iterate over the most significant byte of each element */ \
+ for (int i = 0, j = 0; i < ARRAY_SIZE(b->u8); i += SZ) { \
+ if (b->VsrB(ARRAY_SIZE(b->u8) - i - SZ) & 0x80) { \
+ /* Update each byte of the element */ \
+ for (int k = 0, rk = SZ - 1; k < SZ; k++, rk--) { \
+ /* Reverse indexing of "j" */ \
+ const int idx = ARRAY_SIZE(b->u8) - j - SZ; \
+ tmp.VsrB(idx + rk) = i + k; \
+ } \
+ j += SZ; \
+ } \
+ } \
+ \
+ *t = tmp; \
+}
+
+XXGENPCV(XXGENPCVBM, 1)
+XXGENPCV(XXGENPCVHM, 2)
+XXGENPCV(XXGENPCVWM, 4)
+XXGENPCV(XXGENPCVDM, 8)
+#undef XXGENPCV
+
#if defined(HOST_WORDS_BIGENDIAN)
#define VBPERMQ_INDEX(avr, i) ((avr)->u8[(i)])
#define VBPERMD_INDEX(i) (i)
diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx-impl.c.inc
index b5e07cf3df32..6528e1ae31e0 100644
--- a/target/ppc/translate/vsx-impl.c.inc
+++ b/target/ppc/translate/vsx-impl.c.inc
@@ -1256,6 +1256,49 @@ static bool trans_XXPERMX(DisasContext *ctx, arg_8RR_XX4_uim3 *a)
return true;
}
+#define XXGENPCV(NAME) \
+static bool trans_##NAME(DisasContext *ctx, arg_X_imm5 *a) \
+{ \
+ TCGv_ptr xt, vrb; \
+ \
+ REQUIRE_INSNS_FLAGS2(ctx, ISA310); \
+ REQUIRE_VSX(ctx); \
+ \
+ if (a->imm & ~0x3) { \
+ gen_invalid(ctx); \
+ return true; \
+ } \
+ \
+ xt = gen_vsr_ptr(a->xt); \
+ vrb = gen_avr_ptr(a->vrb); \
+ \
+ switch (a->imm) { \
+ case 0b00000: /* Big-Endian expansion */ \
+ glue(gen_helper_, glue(NAME, _be_exp))(xt, vrb); \
+ break; \
+ case 0b00001: /* Big-Endian compression */ \
+ glue(gen_helper_, glue(NAME, _be_comp))(xt, vrb); \
+ break; \
+ case 0b00010: /* Little-Endian expansion */ \
+ glue(gen_helper_, glue(NAME, _le_exp))(xt, vrb); \
+ break; \
+ case 0b00011: /* Little-Endian compression */ \
+ glue(gen_helper_, glue(NAME, _le_comp))(xt, vrb); \
+ break; \
+ } \
+ \
+ tcg_temp_free_ptr(xt); \
+ tcg_temp_free_ptr(vrb); \
+ \
+ return true; \
+}
+
+XXGENPCV(XXGENPCVBM)
+XXGENPCV(XXGENPCVHM)
+XXGENPCV(XXGENPCVWM)
+XXGENPCV(XXGENPCVDM)
+#undef XXGENPCV
+
#define GEN_VSX_HELPER_VSX_MADD(name, op1, aop, mop, inval, type) \
static void gen_##name(DisasContext *ctx) \
{ \
--
2.34.1
^ permalink raw reply related [flat|nested] 89+ messages in thread* [PULL 42/87] target/ppc: move xs[n]madd[am][ds]p/xs[n]msub[am][ds]p to decodetree
2022-03-02 11:06 [PULL 00/87] ppc queue Cédric Le Goater
` (40 preceding siblings ...)
2022-03-02 11:07 ` [PULL 41/87] target/ppc: Implement xxgenpcv[bhwd]m instruction Cédric Le Goater
@ 2022-03-02 11:07 ` Cédric Le Goater
2022-03-02 11:07 ` [PULL 43/87] target/ppc: implement xs[n]maddqp[o]/xs[n]msubqp[o] Cédric Le Goater
` (45 subsequent siblings)
87 siblings, 0 replies; 89+ messages in thread
From: Cédric Le Goater @ 2022-03-02 11:07 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Richard Henderson, Matheus Ferst,
Cédric Le Goater
From: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20220225210936.1749575-37-matheus.ferst@eldorado.org.br>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/helper.h | 16 ++++-----
target/ppc/insn32.decode | 22 ++++++++++++
target/ppc/fpu_helper.c | 23 ++++++------
target/ppc/translate/vsx-impl.c.inc | 56 ++++++++++++++++++++++++-----
target/ppc/translate/vsx-ops.c.inc | 16 ---------
5 files changed, 90 insertions(+), 43 deletions(-)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 008cd6405d0f..e376ad19b3d1 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -355,10 +355,10 @@ DEF_HELPER_3(xssqrtdp, void, env, vsr, vsr)
DEF_HELPER_3(xsrsqrtedp, void, env, vsr, vsr)
DEF_HELPER_4(xstdivdp, void, env, i32, vsr, vsr)
DEF_HELPER_3(xstsqrtdp, void, env, i32, vsr)
-DEF_HELPER_5(xsmadddp, void, env, vsr, vsr, vsr, vsr)
-DEF_HELPER_5(xsmsubdp, void, env, vsr, vsr, vsr, vsr)
-DEF_HELPER_5(xsnmadddp, void, env, vsr, vsr, vsr, vsr)
-DEF_HELPER_5(xsnmsubdp, void, env, vsr, vsr, vsr, vsr)
+DEF_HELPER_5(XSMADDDP, void, env, vsr, vsr, vsr, vsr)
+DEF_HELPER_5(XSMSUBDP, void, env, vsr, vsr, vsr, vsr)
+DEF_HELPER_5(XSNMADDDP, void, env, vsr, vsr, vsr, vsr)
+DEF_HELPER_5(XSNMSUBDP, void, env, vsr, vsr, vsr, vsr)
DEF_HELPER_4(xscmpeqdp, void, env, vsr, vsr, vsr)
DEF_HELPER_4(xscmpgtdp, void, env, vsr, vsr, vsr)
DEF_HELPER_4(xscmpgedp, void, env, vsr, vsr, vsr)
@@ -418,10 +418,10 @@ DEF_HELPER_3(xsresp, void, env, vsr, vsr)
DEF_HELPER_2(xsrsp, i64, env, i64)
DEF_HELPER_3(xssqrtsp, void, env, vsr, vsr)
DEF_HELPER_3(xsrsqrtesp, void, env, vsr, vsr)
-DEF_HELPER_5(xsmaddsp, void, env, vsr, vsr, vsr, vsr)
-DEF_HELPER_5(xsmsubsp, void, env, vsr, vsr, vsr, vsr)
-DEF_HELPER_5(xsnmaddsp, void, env, vsr, vsr, vsr, vsr)
-DEF_HELPER_5(xsnmsubsp, void, env, vsr, vsr, vsr, vsr)
+DEF_HELPER_5(XSMADDSP, void, env, vsr, vsr, vsr, vsr)
+DEF_HELPER_5(XSMSUBSP, void, env, vsr, vsr, vsr, vsr)
+DEF_HELPER_5(XSNMADDSP, void, env, vsr, vsr, vsr, vsr)
+DEF_HELPER_5(XSNMSUBSP, void, env, vsr, vsr, vsr, vsr)
DEF_HELPER_4(xvadddp, void, env, vsr, vsr, vsr)
DEF_HELPER_4(xvsubdp, void, env, vsr, vsr, vsr)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 22b245607b0f..ed24b39e5a89 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -605,6 +605,28 @@ STXVX 011111 ..... ..... ..... 0110001100 . @X_TSX
LXVPX 011111 ..... ..... ..... 0101001101 - @X_TSXP
STXVPX 011111 ..... ..... ..... 0111001101 - @X_TSXP
+## VSX Scalar Multiply-Add Instructions
+
+XSMADDADP 111100 ..... ..... ..... 00100001 . . . @XX3
+XSMADDMDP 111100 ..... ..... ..... 00101001 . . . @XX3
+XSMADDASP 111100 ..... ..... ..... 00000001 . . . @XX3
+XSMADDMSP 111100 ..... ..... ..... 00001001 . . . @XX3
+
+XSMSUBADP 111100 ..... ..... ..... 00110001 . . . @XX3
+XSMSUBMDP 111100 ..... ..... ..... 00111001 . . . @XX3
+XSMSUBASP 111100 ..... ..... ..... 00010001 . . . @XX3
+XSMSUBMSP 111100 ..... ..... ..... 00011001 . . . @XX3
+
+XSNMADDASP 111100 ..... ..... ..... 10000001 . . . @XX3
+XSNMADDMSP 111100 ..... ..... ..... 10001001 . . . @XX3
+XSNMADDADP 111100 ..... ..... ..... 10100001 . . . @XX3
+XSNMADDMDP 111100 ..... ..... ..... 10101001 . . . @XX3
+
+XSNMSUBASP 111100 ..... ..... ..... 10010001 . . . @XX3
+XSNMSUBMSP 111100 ..... ..... ..... 10011001 . . . @XX3
+XSNMSUBADP 111100 ..... ..... ..... 10110001 . . . @XX3
+XSNMSUBMDP 111100 ..... ..... ..... 10111001 . . . @XX3
+
## VSX splat instruction
XXSPLTIB 111100 ..... 00 ........ 0101101000 . @X_imm8
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
index 0fd285defc7c..c8797d805323 100644
--- a/target/ppc/fpu_helper.c
+++ b/target/ppc/fpu_helper.c
@@ -2156,10 +2156,11 @@ VSX_TSQRT(xvtsqrtsp, 4, float32, VsrW(i), -126, 23)
* maddflgs - flags for the float*muladd routine that control the
* various forms (madd, msub, nmadd, nmsub)
* sfprf - set FPRF
+ * r2sp - round intermediate double precision result to single precision
*/
#define VSX_MADD(op, nels, tp, fld, maddflgs, sfprf, r2sp) \
void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, \
- ppc_vsr_t *xa, ppc_vsr_t *b, ppc_vsr_t *c) \
+ ppc_vsr_t *s1, ppc_vsr_t *s2, ppc_vsr_t *s3) \
{ \
ppc_vsr_t t = *xt; \
int i; \
@@ -2175,12 +2176,12 @@ void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, \
* result to odd. \
*/ \
set_float_rounding_mode(float_round_to_zero, &tstat); \
- t.fld = tp##_muladd(xa->fld, b->fld, c->fld, \
+ t.fld = tp##_muladd(s1->fld, s3->fld, s2->fld, \
maddflgs, &tstat); \
t.fld |= (get_float_exception_flags(&tstat) & \
float_flag_inexact) != 0; \
} else { \
- t.fld = tp##_muladd(xa->fld, b->fld, c->fld, \
+ t.fld = tp##_muladd(s1->fld, s3->fld, s2->fld, \
maddflgs, &tstat); \
} \
env->fp_status.float_exception_flags |= tstat.float_exception_flags; \
@@ -2202,14 +2203,14 @@ void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, \
do_float_check_status(env, GETPC()); \
}
-VSX_MADD(xsmadddp, 1, float64, VsrD(0), MADD_FLGS, 1, 0)
-VSX_MADD(xsmsubdp, 1, float64, VsrD(0), MSUB_FLGS, 1, 0)
-VSX_MADD(xsnmadddp, 1, float64, VsrD(0), NMADD_FLGS, 1, 0)
-VSX_MADD(xsnmsubdp, 1, float64, VsrD(0), NMSUB_FLGS, 1, 0)
-VSX_MADD(xsmaddsp, 1, float64, VsrD(0), MADD_FLGS, 1, 1)
-VSX_MADD(xsmsubsp, 1, float64, VsrD(0), MSUB_FLGS, 1, 1)
-VSX_MADD(xsnmaddsp, 1, float64, VsrD(0), NMADD_FLGS, 1, 1)
-VSX_MADD(xsnmsubsp, 1, float64, VsrD(0), NMSUB_FLGS, 1, 1)
+VSX_MADD(XSMADDDP, 1, float64, VsrD(0), MADD_FLGS, 1, 0)
+VSX_MADD(XSMSUBDP, 1, float64, VsrD(0), MSUB_FLGS, 1, 0)
+VSX_MADD(XSNMADDDP, 1, float64, VsrD(0), NMADD_FLGS, 1, 0)
+VSX_MADD(XSNMSUBDP, 1, float64, VsrD(0), NMSUB_FLGS, 1, 0)
+VSX_MADD(XSMADDSP, 1, float64, VsrD(0), MADD_FLGS, 1, 1)
+VSX_MADD(XSMSUBSP, 1, float64, VsrD(0), MSUB_FLGS, 1, 1)
+VSX_MADD(XSNMADDSP, 1, float64, VsrD(0), NMADD_FLGS, 1, 1)
+VSX_MADD(XSNMSUBSP, 1, float64, VsrD(0), NMSUB_FLGS, 1, 1)
VSX_MADD(xvmadddp, 2, float64, VsrD(i), MADD_FLGS, 0, 0)
VSX_MADD(xvmsubdp, 2, float64, VsrD(i), MSUB_FLGS, 0, 0)
diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx-impl.c.inc
index 6528e1ae31e0..c6313b8f56e3 100644
--- a/target/ppc/translate/vsx-impl.c.inc
+++ b/target/ppc/translate/vsx-impl.c.inc
@@ -1299,6 +1299,54 @@ XXGENPCV(XXGENPCVWM)
XXGENPCV(XXGENPCVDM)
#undef XXGENPCV
+static bool do_xsmadd(DisasContext *ctx, int tgt, int src1, int src2, int src3,
+ void (*gen_helper)(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr))
+{
+ TCGv_ptr t, s1, s2, s3;
+
+ t = gen_vsr_ptr(tgt);
+ s1 = gen_vsr_ptr(src1);
+ s2 = gen_vsr_ptr(src2);
+ s3 = gen_vsr_ptr(src3);
+
+ gen_helper(cpu_env, t, s1, s2, s3);
+
+ tcg_temp_free_ptr(t);
+ tcg_temp_free_ptr(s1);
+ tcg_temp_free_ptr(s2);
+ tcg_temp_free_ptr(s3);
+
+ return true;
+}
+
+static bool do_xsmadd_XX3(DisasContext *ctx, arg_XX3 *a, bool type_a,
+ void (*gen_helper)(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr))
+{
+ REQUIRE_VSX(ctx);
+
+ if (type_a) {
+ return do_xsmadd(ctx, a->xt, a->xa, a->xt, a->xb, gen_helper);
+ }
+ return do_xsmadd(ctx, a->xt, a->xa, a->xb, a->xt, gen_helper);
+}
+
+TRANS_FLAGS2(VSX, XSMADDADP, do_xsmadd_XX3, true, gen_helper_XSMADDDP)
+TRANS_FLAGS2(VSX, XSMADDMDP, do_xsmadd_XX3, false, gen_helper_XSMADDDP)
+TRANS_FLAGS2(VSX, XSMSUBADP, do_xsmadd_XX3, true, gen_helper_XSMSUBDP)
+TRANS_FLAGS2(VSX, XSMSUBMDP, do_xsmadd_XX3, false, gen_helper_XSMSUBDP)
+TRANS_FLAGS2(VSX, XSNMADDADP, do_xsmadd_XX3, true, gen_helper_XSNMADDDP)
+TRANS_FLAGS2(VSX, XSNMADDMDP, do_xsmadd_XX3, false, gen_helper_XSNMADDDP)
+TRANS_FLAGS2(VSX, XSNMSUBADP, do_xsmadd_XX3, true, gen_helper_XSNMSUBDP)
+TRANS_FLAGS2(VSX, XSNMSUBMDP, do_xsmadd_XX3, false, gen_helper_XSNMSUBDP)
+TRANS_FLAGS2(VSX207, XSMADDASP, do_xsmadd_XX3, true, gen_helper_XSMADDSP)
+TRANS_FLAGS2(VSX207, XSMADDMSP, do_xsmadd_XX3, false, gen_helper_XSMADDSP)
+TRANS_FLAGS2(VSX207, XSMSUBASP, do_xsmadd_XX3, true, gen_helper_XSMSUBSP)
+TRANS_FLAGS2(VSX207, XSMSUBMSP, do_xsmadd_XX3, false, gen_helper_XSMSUBSP)
+TRANS_FLAGS2(VSX207, XSNMADDASP, do_xsmadd_XX3, true, gen_helper_XSNMADDSP)
+TRANS_FLAGS2(VSX207, XSNMADDMSP, do_xsmadd_XX3, false, gen_helper_XSNMADDSP)
+TRANS_FLAGS2(VSX207, XSNMSUBASP, do_xsmadd_XX3, true, gen_helper_XSNMSUBSP)
+TRANS_FLAGS2(VSX207, XSNMSUBMSP, do_xsmadd_XX3, false, gen_helper_XSNMSUBSP)
+
#define GEN_VSX_HELPER_VSX_MADD(name, op1, aop, mop, inval, type) \
static void gen_##name(DisasContext *ctx) \
{ \
@@ -1329,14 +1377,6 @@ static void gen_##name(DisasContext *ctx) \
tcg_temp_free_ptr(c); \
}
-GEN_VSX_HELPER_VSX_MADD(xsmadddp, 0x04, 0x04, 0x05, 0, PPC2_VSX)
-GEN_VSX_HELPER_VSX_MADD(xsmsubdp, 0x04, 0x06, 0x07, 0, PPC2_VSX)
-GEN_VSX_HELPER_VSX_MADD(xsnmadddp, 0x04, 0x14, 0x15, 0, PPC2_VSX)
-GEN_VSX_HELPER_VSX_MADD(xsnmsubdp, 0x04, 0x16, 0x17, 0, PPC2_VSX)
-GEN_VSX_HELPER_VSX_MADD(xsmaddsp, 0x04, 0x00, 0x01, 0, PPC2_VSX207)
-GEN_VSX_HELPER_VSX_MADD(xsmsubsp, 0x04, 0x02, 0x03, 0, PPC2_VSX207)
-GEN_VSX_HELPER_VSX_MADD(xsnmaddsp, 0x04, 0x10, 0x11, 0, PPC2_VSX207)
-GEN_VSX_HELPER_VSX_MADD(xsnmsubsp, 0x04, 0x12, 0x13, 0, PPC2_VSX207)
GEN_VSX_HELPER_VSX_MADD(xvmadddp, 0x04, 0x0C, 0x0D, 0, PPC2_VSX)
GEN_VSX_HELPER_VSX_MADD(xvmsubdp, 0x04, 0x0E, 0x0F, 0, PPC2_VSX)
GEN_VSX_HELPER_VSX_MADD(xvnmadddp, 0x04, 0x1C, 0x1D, 0, PPC2_VSX)
diff --git a/target/ppc/translate/vsx-ops.c.inc b/target/ppc/translate/vsx-ops.c.inc
index 0a6b2b31ac84..9cfec53df0be 100644
--- a/target/ppc/translate/vsx-ops.c.inc
+++ b/target/ppc/translate/vsx-ops.c.inc
@@ -186,14 +186,6 @@ GEN_XX2FORM(xssqrtdp, 0x16, 0x04, PPC2_VSX),
GEN_XX2FORM(xsrsqrtedp, 0x14, 0x04, PPC2_VSX),
GEN_XX3FORM(xstdivdp, 0x14, 0x07, PPC2_VSX),
GEN_XX2FORM(xstsqrtdp, 0x14, 0x06, PPC2_VSX),
-GEN_XX3FORM_NAME(xsmadddp, "xsmaddadp", 0x04, 0x04, PPC2_VSX),
-GEN_XX3FORM_NAME(xsmadddp, "xsmaddmdp", 0x04, 0x05, PPC2_VSX),
-GEN_XX3FORM_NAME(xsmsubdp, "xsmsubadp", 0x04, 0x06, PPC2_VSX),
-GEN_XX3FORM_NAME(xsmsubdp, "xsmsubmdp", 0x04, 0x07, PPC2_VSX),
-GEN_XX3FORM_NAME(xsnmadddp, "xsnmaddadp", 0x04, 0x14, PPC2_VSX),
-GEN_XX3FORM_NAME(xsnmadddp, "xsnmaddmdp", 0x04, 0x15, PPC2_VSX),
-GEN_XX3FORM_NAME(xsnmsubdp, "xsnmsubadp", 0x04, 0x16, PPC2_VSX),
-GEN_XX3FORM_NAME(xsnmsubdp, "xsnmsubmdp", 0x04, 0x17, PPC2_VSX),
GEN_XX3FORM(xscmpeqdp, 0x0C, 0x00, PPC2_ISA300),
GEN_XX3FORM(xscmpgtdp, 0x0C, 0x01, PPC2_ISA300),
GEN_XX3FORM(xscmpgedp, 0x0C, 0x02, PPC2_ISA300),
@@ -235,14 +227,6 @@ GEN_XX2FORM(xsresp, 0x14, 0x01, PPC2_VSX207),
GEN_XX2FORM(xsrsp, 0x12, 0x11, PPC2_VSX207),
GEN_XX2FORM(xssqrtsp, 0x16, 0x00, PPC2_VSX207),
GEN_XX2FORM(xsrsqrtesp, 0x14, 0x00, PPC2_VSX207),
-GEN_XX3FORM_NAME(xsmaddsp, "xsmaddasp", 0x04, 0x00, PPC2_VSX207),
-GEN_XX3FORM_NAME(xsmaddsp, "xsmaddmsp", 0x04, 0x01, PPC2_VSX207),
-GEN_XX3FORM_NAME(xsmsubsp, "xsmsubasp", 0x04, 0x02, PPC2_VSX207),
-GEN_XX3FORM_NAME(xsmsubsp, "xsmsubmsp", 0x04, 0x03, PPC2_VSX207),
-GEN_XX3FORM_NAME(xsnmaddsp, "xsnmaddasp", 0x04, 0x10, PPC2_VSX207),
-GEN_XX3FORM_NAME(xsnmaddsp, "xsnmaddmsp", 0x04, 0x11, PPC2_VSX207),
-GEN_XX3FORM_NAME(xsnmsubsp, "xsnmsubasp", 0x04, 0x12, PPC2_VSX207),
-GEN_XX3FORM_NAME(xsnmsubsp, "xsnmsubmsp", 0x04, 0x13, PPC2_VSX207),
GEN_XX2FORM(xscvsxdsp, 0x10, 0x13, PPC2_VSX207),
GEN_XX2FORM(xscvuxdsp, 0x10, 0x12, PPC2_VSX207),
--
2.34.1
^ permalink raw reply related [flat|nested] 89+ messages in thread* [PULL 43/87] target/ppc: implement xs[n]maddqp[o]/xs[n]msubqp[o]
2022-03-02 11:06 [PULL 00/87] ppc queue Cédric Le Goater
` (41 preceding siblings ...)
2022-03-02 11:07 ` [PULL 42/87] target/ppc: move xs[n]madd[am][ds]p/xs[n]msub[am][ds]p to decodetree Cédric Le Goater
@ 2022-03-02 11:07 ` Cédric Le Goater
2022-03-02 11:07 ` [PULL 44/87] target/ppc: Implement xvtlsbb instruction Cédric Le Goater
` (44 subsequent siblings)
87 siblings, 0 replies; 89+ messages in thread
From: Cédric Le Goater @ 2022-03-02 11:07 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Richard Henderson, Matheus Ferst,
Cédric Le Goater
From: Matheus Ferst <matheus.ferst@eldorado.org.br>
Implement the following PowerISA v3.0 instuctions:
xsmaddqp[o]: VSX Scalar Multiply-Add Quad-Precision [using round to Odd]
xsmsubqp[o]: VSX Scalar Multiply-Subtract Quad-Precision [using round
to Odd]
xsnmaddqp[o]: VSX Scalar Negative Multiply-Add Quad-Precision [using
round to Odd]
xsnmsubqp[o]: VSX Scalar Negative Multiply-Subtract Quad-Precision
[using round to Odd]
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20220225210936.1749575-38-matheus.ferst@eldorado.org.br>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/helper.h | 9 +++++++
target/ppc/insn32.decode | 4 +++
target/ppc/fpu_helper.c | 42 +++++++++++++++++++++++++++++
target/ppc/translate/vsx-impl.c.inc | 25 +++++++++++++++++
4 files changed, 80 insertions(+)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index e376ad19b3d1..378a348c8a83 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -423,6 +423,15 @@ DEF_HELPER_5(XSMSUBSP, void, env, vsr, vsr, vsr, vsr)
DEF_HELPER_5(XSNMADDSP, void, env, vsr, vsr, vsr, vsr)
DEF_HELPER_5(XSNMSUBSP, void, env, vsr, vsr, vsr, vsr)
+DEF_HELPER_5(XSMADDQP, void, env, vsr, vsr, vsr, vsr)
+DEF_HELPER_5(XSMADDQPO, void, env, vsr, vsr, vsr, vsr)
+DEF_HELPER_5(XSMSUBQP, void, env, vsr, vsr, vsr, vsr)
+DEF_HELPER_5(XSMSUBQPO, void, env, vsr, vsr, vsr, vsr)
+DEF_HELPER_5(XSNMADDQP, void, env, vsr, vsr, vsr, vsr)
+DEF_HELPER_5(XSNMADDQPO, void, env, vsr, vsr, vsr, vsr)
+DEF_HELPER_5(XSNMSUBQP, void, env, vsr, vsr, vsr, vsr)
+DEF_HELPER_5(XSNMSUBQPO, void, env, vsr, vsr, vsr, vsr)
+
DEF_HELPER_4(xvadddp, void, env, vsr, vsr, vsr)
DEF_HELPER_4(xvsubdp, void, env, vsr, vsr, vsr)
DEF_HELPER_4(xvmuldp, void, env, vsr, vsr, vsr)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index ed24b39e5a89..c28cc13325fe 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -611,21 +611,25 @@ XSMADDADP 111100 ..... ..... ..... 00100001 . . . @XX3
XSMADDMDP 111100 ..... ..... ..... 00101001 . . . @XX3
XSMADDASP 111100 ..... ..... ..... 00000001 . . . @XX3
XSMADDMSP 111100 ..... ..... ..... 00001001 . . . @XX3
+XSMADDQP 111111 ..... ..... ..... 0110000100 . @X_rc
XSMSUBADP 111100 ..... ..... ..... 00110001 . . . @XX3
XSMSUBMDP 111100 ..... ..... ..... 00111001 . . . @XX3
XSMSUBASP 111100 ..... ..... ..... 00010001 . . . @XX3
XSMSUBMSP 111100 ..... ..... ..... 00011001 . . . @XX3
+XSMSUBQP 111111 ..... ..... ..... 0110100100 . @X_rc
XSNMADDASP 111100 ..... ..... ..... 10000001 . . . @XX3
XSNMADDMSP 111100 ..... ..... ..... 10001001 . . . @XX3
XSNMADDADP 111100 ..... ..... ..... 10100001 . . . @XX3
XSNMADDMDP 111100 ..... ..... ..... 10101001 . . . @XX3
+XSNMADDQP 111111 ..... ..... ..... 0111000100 . @X_rc
XSNMSUBASP 111100 ..... ..... ..... 10010001 . . . @XX3
XSNMSUBMSP 111100 ..... ..... ..... 10011001 . . . @XX3
XSNMSUBADP 111100 ..... ..... ..... 10110001 . . . @XX3
XSNMSUBMDP 111100 ..... ..... ..... 10111001 . . . @XX3
+XSNMSUBQP 111111 ..... ..... ..... 0111100100 . @X_rc
## VSX splat instruction
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
index c8797d805323..98e9576608f6 100644
--- a/target/ppc/fpu_helper.c
+++ b/target/ppc/fpu_helper.c
@@ -2222,6 +2222,48 @@ VSX_MADD(xvmsubsp, 4, float32, VsrW(i), MSUB_FLGS, 0, 0)
VSX_MADD(xvnmaddsp, 4, float32, VsrW(i), NMADD_FLGS, 0, 0)
VSX_MADD(xvnmsubsp, 4, float32, VsrW(i), NMSUB_FLGS, 0, 0)
+/*
+ * VSX_MADDQ - VSX floating point quad-precision muliply/add
+ * op - instruction mnemonic
+ * maddflgs - flags for the float*muladd routine that control the
+ * various forms (madd, msub, nmadd, nmsub)
+ * ro - round to odd
+ */
+#define VSX_MADDQ(op, maddflgs, ro) \
+void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *s1, ppc_vsr_t *s2,\
+ ppc_vsr_t *s3) \
+{ \
+ ppc_vsr_t t = *xt; \
+ \
+ helper_reset_fpstatus(env); \
+ \
+ float_status tstat = env->fp_status; \
+ set_float_exception_flags(0, &tstat); \
+ if (ro) { \
+ tstat.float_rounding_mode = float_round_to_odd; \
+ } \
+ t.f128 = float128_muladd(s1->f128, s3->f128, s2->f128, maddflgs, &tstat); \
+ env->fp_status.float_exception_flags |= tstat.float_exception_flags; \
+ \
+ if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { \
+ float_invalid_op_madd(env, tstat.float_exception_flags, \
+ false, GETPC()); \
+ } \
+ \
+ helper_compute_fprf_float128(env, t.f128); \
+ *xt = t; \
+ do_float_check_status(env, GETPC()); \
+}
+
+VSX_MADDQ(XSMADDQP, MADD_FLGS, 0)
+VSX_MADDQ(XSMADDQPO, MADD_FLGS, 1)
+VSX_MADDQ(XSMSUBQP, MSUB_FLGS, 0)
+VSX_MADDQ(XSMSUBQPO, MSUB_FLGS, 1)
+VSX_MADDQ(XSNMADDQP, NMADD_FLGS, 0)
+VSX_MADDQ(XSNMADDQPO, NMADD_FLGS, 1)
+VSX_MADDQ(XSNMSUBQP, NMSUB_FLGS, 0)
+VSX_MADDQ(XSNMSUBQPO, NMSUB_FLGS, 0)
+
/*
* VSX_SCALAR_CMP_DP - VSX scalar floating point compare double precision
* op - instruction mnemonic
diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx-impl.c.inc
index c6313b8f56e3..292a14f5aa98 100644
--- a/target/ppc/translate/vsx-impl.c.inc
+++ b/target/ppc/translate/vsx-impl.c.inc
@@ -1347,6 +1347,31 @@ TRANS_FLAGS2(VSX207, XSNMADDMSP, do_xsmadd_XX3, false, gen_helper_XSNMADDSP)
TRANS_FLAGS2(VSX207, XSNMSUBASP, do_xsmadd_XX3, true, gen_helper_XSNMSUBSP)
TRANS_FLAGS2(VSX207, XSNMSUBMSP, do_xsmadd_XX3, false, gen_helper_XSNMSUBSP)
+static bool do_xsmadd_X(DisasContext *ctx, arg_X_rc *a,
+ void (*gen_helper)(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr),
+ void (*gen_helper_ro)(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr))
+{
+ int vrt, vra, vrb;
+
+ REQUIRE_INSNS_FLAGS2(ctx, ISA300);
+ REQUIRE_VSX(ctx);
+
+ vrt = a->rt + 32;
+ vra = a->ra + 32;
+ vrb = a->rb + 32;
+
+ if (a->rc) {
+ return do_xsmadd(ctx, vrt, vra, vrt, vrb, gen_helper_ro);
+ }
+
+ return do_xsmadd(ctx, vrt, vra, vrt, vrb, gen_helper);
+}
+
+TRANS(XSMADDQP, do_xsmadd_X, gen_helper_XSMADDQP, gen_helper_XSMADDQPO)
+TRANS(XSMSUBQP, do_xsmadd_X, gen_helper_XSMSUBQP, gen_helper_XSMSUBQPO)
+TRANS(XSNMADDQP, do_xsmadd_X, gen_helper_XSNMADDQP, gen_helper_XSNMADDQPO)
+TRANS(XSNMSUBQP, do_xsmadd_X, gen_helper_XSNMSUBQP, gen_helper_XSNMSUBQPO)
+
#define GEN_VSX_HELPER_VSX_MADD(name, op1, aop, mop, inval, type) \
static void gen_##name(DisasContext *ctx) \
{ \
--
2.34.1
^ permalink raw reply related [flat|nested] 89+ messages in thread* [PULL 44/87] target/ppc: Implement xvtlsbb instruction
2022-03-02 11:06 [PULL 00/87] ppc queue Cédric Le Goater
` (42 preceding siblings ...)
2022-03-02 11:07 ` [PULL 43/87] target/ppc: implement xs[n]maddqp[o]/xs[n]msubqp[o] Cédric Le Goater
@ 2022-03-02 11:07 ` Cédric Le Goater
2022-03-02 11:07 ` [PULL 45/87] target/ppc: Remove xscmpnedp instruction Cédric Le Goater
` (43 subsequent siblings)
87 siblings, 0 replies; 89+ messages in thread
From: Cédric Le Goater @ 2022-03-02 11:07 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Víctor Colombo, Peter Maydell, Matheus Ferst,
Cédric Le Goater
From: Víctor Colombo <victor.colombo@eldorado.org.br>
Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20220225210936.1749575-39-matheus.ferst@eldorado.org.br>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/insn32.decode | 7 +++++
target/ppc/translate/vsx-impl.c.inc | 40 +++++++++++++++++++++++++++++
2 files changed, 47 insertions(+)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index c28cc13325fe..973cda113166 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -155,6 +155,9 @@
&XX2 xt xb uim:uint8_t
@XX2 ...... ..... ... uim:2 ..... ......... .. &XX2 xt=%xx_xt xb=%xx_xb
+&XX2_bf_xb bf xb
+@XX2_bf_xb ...... bf:3 .. ..... ..... ......... . . &XX2_bf_xb xb=%xx_xb
+
&XX3 xt xa xb
@XX3 ...... ..... ..... ..... ........ ... &XX3 xt=%xx_xt xa=%xx_xa xb=%xx_xb
@@ -666,6 +669,10 @@ XSMINJDP 111100 ..... ..... ..... 10011000 ... @XX3
XSCVQPDP 111111 ..... 10100 ..... 1101000100 . @X_tb_rc
+## VSX Vector Test Least-Significant Bit by Byte Instruction
+
+XVTLSBB 111100 ... -- 00010 ..... 111011011 . - @XX2_bf_xb
+
### rfebb
&XL_s s:uint8_t
@XL_s ......-------------- s:1 .......... - &XL_s
diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx-impl.c.inc
index 292a14f5aa98..4da889531bd7 100644
--- a/target/ppc/translate/vsx-impl.c.inc
+++ b/target/ppc/translate/vsx-impl.c.inc
@@ -1704,6 +1704,46 @@ static bool trans_LXVKQ(DisasContext *ctx, arg_X_uim5 *a)
return true;
}
+static bool trans_XVTLSBB(DisasContext *ctx, arg_XX2_bf_xb *a)
+{
+ TCGv_i64 xb, t0, t1, all_true, all_false, mask, zero;
+
+ REQUIRE_INSNS_FLAGS2(ctx, ISA310);
+ REQUIRE_VSX(ctx);
+
+ xb = tcg_temp_new_i64();
+ t0 = tcg_temp_new_i64();
+ t1 = tcg_temp_new_i64();
+ all_true = tcg_temp_new_i64();
+ all_false = tcg_temp_new_i64();
+ mask = tcg_constant_i64(dup_const(MO_8, 1));
+ zero = tcg_constant_i64(0);
+
+ get_cpu_vsr(xb, a->xb, true);
+ tcg_gen_and_i64(t0, mask, xb);
+ get_cpu_vsr(xb, a->xb, false);
+ tcg_gen_and_i64(t1, mask, xb);
+
+ tcg_gen_or_i64(all_false, t0, t1);
+ tcg_gen_and_i64(all_true, t0, t1);
+
+ tcg_gen_setcond_i64(TCG_COND_EQ, all_false, all_false, zero);
+ tcg_gen_shli_i64(all_false, all_false, 1);
+ tcg_gen_setcond_i64(TCG_COND_EQ, all_true, all_true, mask);
+ tcg_gen_shli_i64(all_true, all_true, 3);
+
+ tcg_gen_or_i64(t0, all_false, all_true);
+ tcg_gen_extrl_i64_i32(cpu_crf[a->bf], t0);
+
+ tcg_temp_free_i64(xb);
+ tcg_temp_free_i64(t0);
+ tcg_temp_free_i64(t1);
+ tcg_temp_free_i64(all_true);
+ tcg_temp_free_i64(all_false);
+
+ return true;
+}
+
static void gen_xxsldwi(DisasContext *ctx)
{
TCGv_i64 xth, xtl;
--
2.34.1
^ permalink raw reply related [flat|nested] 89+ messages in thread* [PULL 45/87] target/ppc: Remove xscmpnedp instruction
2022-03-02 11:06 [PULL 00/87] ppc queue Cédric Le Goater
` (43 preceding siblings ...)
2022-03-02 11:07 ` [PULL 44/87] target/ppc: Implement xvtlsbb instruction Cédric Le Goater
@ 2022-03-02 11:07 ` Cédric Le Goater
2022-03-02 11:07 ` [PULL 46/87] target/ppc: Refactor VSX_SCALAR_CMP_DP Cédric Le Goater
` (42 subsequent siblings)
87 siblings, 0 replies; 89+ messages in thread
From: Cédric Le Goater @ 2022-03-02 11:07 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Richard Henderson, Greg Kurz, Víctor Colombo,
Cédric Le Goater, Matheus Ferst
From: Víctor Colombo <victor.colombo@eldorado.org.br>
xscmpnedp was added in ISA v3.0 but removed in v3.0B. This patch
removes this instruction as it was not in the final version of v3.0.
Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br>
Acked-by: Greg Kurz <groug@kaod.org>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20220225210936.1749575-40-matheus.ferst@eldorado.org.br>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/helper.h | 1 -
target/ppc/fpu_helper.c | 1 -
target/ppc/translate/vsx-impl.c.inc | 1 -
target/ppc/translate/vsx-ops.c.inc | 1 -
4 files changed, 4 deletions(-)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 378a348c8a83..4a12d4390527 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -362,7 +362,6 @@ DEF_HELPER_5(XSNMSUBDP, void, env, vsr, vsr, vsr, vsr)
DEF_HELPER_4(xscmpeqdp, void, env, vsr, vsr, vsr)
DEF_HELPER_4(xscmpgtdp, void, env, vsr, vsr, vsr)
DEF_HELPER_4(xscmpgedp, void, env, vsr, vsr, vsr)
-DEF_HELPER_4(xscmpnedp, void, env, vsr, vsr, vsr)
DEF_HELPER_4(xscmpexpdp, void, env, i32, vsr, vsr)
DEF_HELPER_4(xscmpexpqp, void, env, i32, vsr, vsr)
DEF_HELPER_4(xscmpodp, void, env, i32, vsr, vsr)
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
index 98e9576608f6..9b034d1fe47c 100644
--- a/target/ppc/fpu_helper.c
+++ b/target/ppc/fpu_helper.c
@@ -2313,7 +2313,6 @@ void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, \
VSX_SCALAR_CMP_DP(xscmpeqdp, eq, 1, 0)
VSX_SCALAR_CMP_DP(xscmpgedp, le, 1, 1)
VSX_SCALAR_CMP_DP(xscmpgtdp, lt, 1, 1)
-VSX_SCALAR_CMP_DP(xscmpnedp, eq, 0, 0)
void helper_xscmpexpdp(CPUPPCState *env, uint32_t opcode,
ppc_vsr_t *xa, ppc_vsr_t *xb)
diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx-impl.c.inc
index 4da889531bd7..3baaac1abd22 100644
--- a/target/ppc/translate/vsx-impl.c.inc
+++ b/target/ppc/translate/vsx-impl.c.inc
@@ -1055,7 +1055,6 @@ GEN_VSX_HELPER_X1(xstsqrtdp, 0x14, 0x06, 0, PPC2_VSX)
GEN_VSX_HELPER_X3(xscmpeqdp, 0x0C, 0x00, 0, PPC2_ISA300)
GEN_VSX_HELPER_X3(xscmpgtdp, 0x0C, 0x01, 0, PPC2_ISA300)
GEN_VSX_HELPER_X3(xscmpgedp, 0x0C, 0x02, 0, PPC2_ISA300)
-GEN_VSX_HELPER_X3(xscmpnedp, 0x0C, 0x03, 0, PPC2_ISA300)
GEN_VSX_HELPER_X2_AB(xscmpexpdp, 0x0C, 0x07, 0, PPC2_ISA300)
GEN_VSX_HELPER_R2_AB(xscmpexpqp, 0x04, 0x05, 0, PPC2_ISA300)
GEN_VSX_HELPER_X2_AB(xscmpodp, 0x0C, 0x05, 0, PPC2_VSX)
diff --git a/target/ppc/translate/vsx-ops.c.inc b/target/ppc/translate/vsx-ops.c.inc
index 9cfec53df0be..34310c1fb53d 100644
--- a/target/ppc/translate/vsx-ops.c.inc
+++ b/target/ppc/translate/vsx-ops.c.inc
@@ -189,7 +189,6 @@ GEN_XX2FORM(xstsqrtdp, 0x14, 0x06, PPC2_VSX),
GEN_XX3FORM(xscmpeqdp, 0x0C, 0x00, PPC2_ISA300),
GEN_XX3FORM(xscmpgtdp, 0x0C, 0x01, PPC2_ISA300),
GEN_XX3FORM(xscmpgedp, 0x0C, 0x02, PPC2_ISA300),
-GEN_XX3FORM(xscmpnedp, 0x0C, 0x03, PPC2_ISA300),
GEN_XX3FORM(xscmpexpdp, 0x0C, 0x07, PPC2_ISA300),
GEN_VSX_XFORM_300(xscmpexpqp, 0x04, 0x05, 0x00600001),
GEN_XX2IFORM(xscmpodp, 0x0C, 0x05, PPC2_VSX),
--
2.34.1
^ permalink raw reply related [flat|nested] 89+ messages in thread* [PULL 46/87] target/ppc: Refactor VSX_SCALAR_CMP_DP
2022-03-02 11:06 [PULL 00/87] ppc queue Cédric Le Goater
` (44 preceding siblings ...)
2022-03-02 11:07 ` [PULL 45/87] target/ppc: Remove xscmpnedp instruction Cédric Le Goater
@ 2022-03-02 11:07 ` Cédric Le Goater
2022-03-02 11:07 ` [PULL 47/87] target/ppc: Implement xscmp{eq,ge,gt}qp Cédric Le Goater
` (41 subsequent siblings)
87 siblings, 0 replies; 89+ messages in thread
From: Cédric Le Goater @ 2022-03-02 11:07 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Víctor Colombo, Peter Maydell, Richard Henderson,
Matheus Ferst, Cédric Le Goater
From: Víctor Colombo <victor.colombo@eldorado.org.br>
Refactor VSX_SCALAR_CMP_DP, changing its name to VSX_SCALAR_CMP and
prepare the helper to be used for quadword comparisons.
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220225210936.1749575-41-matheus.ferst@eldorado.org.br>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/fpu_helper.c | 64 +++++++++++++++++++----------------------
1 file changed, 29 insertions(+), 35 deletions(-)
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
index 9b034d1fe47c..bbd54b2d9c16 100644
--- a/target/ppc/fpu_helper.c
+++ b/target/ppc/fpu_helper.c
@@ -2265,54 +2265,48 @@ VSX_MADDQ(XSNMSUBQP, NMSUB_FLGS, 0)
VSX_MADDQ(XSNMSUBQPO, NMSUB_FLGS, 0)
/*
- * VSX_SCALAR_CMP_DP - VSX scalar floating point compare double precision
+ * VSX_SCALAR_CMP - VSX scalar floating point compare
* op - instruction mnemonic
+ * tp - type
* cmp - comparison operation
- * exp - expected result of comparison
+ * fld - vsr_t field
* svxvc - set VXVC bit
*/
-#define VSX_SCALAR_CMP_DP(op, cmp, exp, svxvc) \
-void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, \
- ppc_vsr_t *xa, ppc_vsr_t *xb) \
+#define VSX_SCALAR_CMP(op, tp, cmp, fld, svxvc) \
+ void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, \
+ ppc_vsr_t *xa, ppc_vsr_t *xb) \
{ \
- ppc_vsr_t t = *xt; \
- bool vxsnan_flag = false, vxvc_flag = false, vex_flag = false; \
+ int flags; \
+ bool r, vxvc; \
\
- if (float64_is_signaling_nan(xa->VsrD(0), &env->fp_status) || \
- float64_is_signaling_nan(xb->VsrD(0), &env->fp_status)) { \
- vxsnan_flag = true; \
- if (fpscr_ve == 0 && svxvc) { \
- vxvc_flag = true; \
- } \
- } else if (svxvc) { \
- vxvc_flag = float64_is_quiet_nan(xa->VsrD(0), &env->fp_status) || \
- float64_is_quiet_nan(xb->VsrD(0), &env->fp_status); \
- } \
- if (vxsnan_flag) { \
- float_invalid_op_vxsnan(env, GETPC()); \
- } \
- if (vxvc_flag) { \
- float_invalid_op_vxvc(env, 0, GETPC()); \
+ helper_reset_fpstatus(env); \
+ \
+ if (svxvc) { \
+ r = tp##_##cmp(xb->fld, xa->fld, &env->fp_status); \
+ } else { \
+ r = tp##_##cmp##_quiet(xb->fld, xa->fld, &env->fp_status); \
} \
- vex_flag = fpscr_ve && (vxvc_flag || vxsnan_flag); \
\
- if (!vex_flag) { \
- if (float64_##cmp(xb->VsrD(0), xa->VsrD(0), \
- &env->fp_status) == exp) { \
- t.VsrD(0) = -1; \
- t.VsrD(1) = 0; \
- } else { \
- t.VsrD(0) = 0; \
- t.VsrD(1) = 0; \
+ flags = get_float_exception_flags(&env->fp_status); \
+ if (unlikely(flags & float_flag_invalid)) { \
+ vxvc = svxvc; \
+ if (flags & float_flag_invalid_snan) { \
+ float_invalid_op_vxsnan(env, GETPC()); \
+ vxvc &= fpscr_ve == 0; \
+ } \
+ if (vxvc) { \
+ float_invalid_op_vxvc(env, 0, GETPC()); \
} \
} \
- *xt = t; \
+ \
+ memset(xt, 0, sizeof(*xt)); \
+ memset(&xt->fld, -r, sizeof(xt->fld)); \
do_float_check_status(env, GETPC()); \
}
-VSX_SCALAR_CMP_DP(xscmpeqdp, eq, 1, 0)
-VSX_SCALAR_CMP_DP(xscmpgedp, le, 1, 1)
-VSX_SCALAR_CMP_DP(xscmpgtdp, lt, 1, 1)
+VSX_SCALAR_CMP(xscmpeqdp, float64, eq, VsrD(0), 0)
+VSX_SCALAR_CMP(xscmpgedp, float64, le, VsrD(0), 1)
+VSX_SCALAR_CMP(xscmpgtdp, float64, lt, VsrD(0), 1)
void helper_xscmpexpdp(CPUPPCState *env, uint32_t opcode,
ppc_vsr_t *xa, ppc_vsr_t *xb)
--
2.34.1
^ permalink raw reply related [flat|nested] 89+ messages in thread* [PULL 47/87] target/ppc: Implement xscmp{eq,ge,gt}qp
2022-03-02 11:06 [PULL 00/87] ppc queue Cédric Le Goater
` (45 preceding siblings ...)
2022-03-02 11:07 ` [PULL 46/87] target/ppc: Refactor VSX_SCALAR_CMP_DP Cédric Le Goater
@ 2022-03-02 11:07 ` Cédric Le Goater
2022-03-02 11:07 ` [PULL 48/87] target/ppc: Move xscmp{eq,ge,gt}dp to decodetree Cédric Le Goater
` (40 subsequent siblings)
87 siblings, 0 replies; 89+ messages in thread
From: Cédric Le Goater @ 2022-03-02 11:07 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Víctor Colombo, Peter Maydell, Richard Henderson,
Matheus Ferst, Cédric Le Goater
From: Víctor Colombo <victor.colombo@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20220225210936.1749575-42-matheus.ferst@eldorado.org.br>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/helper.h | 3 +++
target/ppc/insn32.decode | 3 +++
target/ppc/fpu_helper.c | 3 +++
target/ppc/translate/vsx-impl.c.inc | 31 +++++++++++++++++++++++++++++
4 files changed, 40 insertions(+)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 4a12d4390527..c646b983e329 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -362,6 +362,9 @@ DEF_HELPER_5(XSNMSUBDP, void, env, vsr, vsr, vsr, vsr)
DEF_HELPER_4(xscmpeqdp, void, env, vsr, vsr, vsr)
DEF_HELPER_4(xscmpgtdp, void, env, vsr, vsr, vsr)
DEF_HELPER_4(xscmpgedp, void, env, vsr, vsr, vsr)
+DEF_HELPER_4(XSCMPEQQP, void, env, vsr, vsr, vsr)
+DEF_HELPER_4(XSCMPGTQP, void, env, vsr, vsr, vsr)
+DEF_HELPER_4(XSCMPGEQP, void, env, vsr, vsr, vsr)
DEF_HELPER_4(xscmpexpdp, void, env, i32, vsr, vsr)
DEF_HELPER_4(xscmpexpqp, void, env, i32, vsr, vsr)
DEF_HELPER_4(xscmpodp, void, env, i32, vsr, vsr)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 973cda113166..92327a0a718f 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -664,6 +664,9 @@ XSMAXCDP 111100 ..... ..... ..... 10000000 ... @XX3
XSMINCDP 111100 ..... ..... ..... 10001000 ... @XX3
XSMAXJDP 111100 ..... ..... ..... 10010000 ... @XX3
XSMINJDP 111100 ..... ..... ..... 10011000 ... @XX3
+XSCMPEQQP 111111 ..... ..... ..... 0001000100 - @X
+XSCMPGEQP 111111 ..... ..... ..... 0011000100 - @X
+XSCMPGTQP 111111 ..... ..... ..... 0011100100 - @X
## VSX Binary Floating-Point Convert Instructions
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
index bbd54b2d9c16..a589e6b7a54f 100644
--- a/target/ppc/fpu_helper.c
+++ b/target/ppc/fpu_helper.c
@@ -2307,6 +2307,9 @@ VSX_MADDQ(XSNMSUBQPO, NMSUB_FLGS, 0)
VSX_SCALAR_CMP(xscmpeqdp, float64, eq, VsrD(0), 0)
VSX_SCALAR_CMP(xscmpgedp, float64, le, VsrD(0), 1)
VSX_SCALAR_CMP(xscmpgtdp, float64, lt, VsrD(0), 1)
+VSX_SCALAR_CMP(XSCMPEQQP, float128, eq, f128, 0)
+VSX_SCALAR_CMP(XSCMPGEQP, float128, le, f128, 1)
+VSX_SCALAR_CMP(XSCMPGTQP, float128, lt, f128, 1)
void helper_xscmpexpdp(CPUPPCState *env, uint32_t opcode,
ppc_vsr_t *xa, ppc_vsr_t *xb)
diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx-impl.c.inc
index 3baaac1abd22..6dd20b030976 100644
--- a/target/ppc/translate/vsx-impl.c.inc
+++ b/target/ppc/translate/vsx-impl.c.inc
@@ -2615,6 +2615,37 @@ TRANS(XSMINCDP, do_xsmaxmincjdp, gen_helper_xsmincdp)
TRANS(XSMAXJDP, do_xsmaxmincjdp, gen_helper_xsmaxjdp)
TRANS(XSMINJDP, do_xsmaxmincjdp, gen_helper_xsminjdp)
+static bool do_helper_X(arg_X *a,
+ void (*helper)(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr))
+{
+ TCGv_ptr rt, ra, rb;
+
+ rt = gen_avr_ptr(a->rt);
+ ra = gen_avr_ptr(a->ra);
+ rb = gen_avr_ptr(a->rb);
+
+ helper(cpu_env, rt, ra, rb);
+
+ tcg_temp_free_ptr(rt);
+ tcg_temp_free_ptr(ra);
+ tcg_temp_free_ptr(rb);
+
+ return true;
+}
+
+static bool do_xscmpqp(DisasContext *ctx, arg_X *a,
+ void (*helper)(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr))
+{
+ REQUIRE_INSNS_FLAGS2(ctx, ISA310);
+ REQUIRE_VSX(ctx);
+
+ return do_helper_X(a, helper);
+}
+
+TRANS(XSCMPEQQP, do_xscmpqp, gen_helper_XSCMPEQQP)
+TRANS(XSCMPGEQP, do_xscmpqp, gen_helper_XSCMPGEQP)
+TRANS(XSCMPGTQP, do_xscmpqp, gen_helper_XSCMPGTQP)
+
#undef GEN_XX2FORM
#undef GEN_XX3FORM
#undef GEN_XX2IFORM
--
2.34.1
^ permalink raw reply related [flat|nested] 89+ messages in thread* [PULL 48/87] target/ppc: Move xscmp{eq,ge,gt}dp to decodetree
2022-03-02 11:06 [PULL 00/87] ppc queue Cédric Le Goater
` (46 preceding siblings ...)
2022-03-02 11:07 ` [PULL 47/87] target/ppc: Implement xscmp{eq,ge,gt}qp Cédric Le Goater
@ 2022-03-02 11:07 ` Cédric Le Goater
2022-03-02 11:07 ` [PULL 49/87] target/ppc: Move xs{max, min}[cj]dp to use do_helper_XX3 Cédric Le Goater
` (39 subsequent siblings)
87 siblings, 0 replies; 89+ messages in thread
From: Cédric Le Goater @ 2022-03-02 11:07 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Víctor Colombo, Peter Maydell, Richard Henderson,
Matheus Ferst, Cédric Le Goater
From: Víctor Colombo <victor.colombo@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20220225210936.1749575-43-matheus.ferst@eldorado.org.br>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/helper.h | 6 +++---
target/ppc/insn32.decode | 3 +++
target/ppc/fpu_helper.c | 6 +++---
target/ppc/translate/vsx-impl.c.inc | 28 +++++++++++++++++++++++++---
target/ppc/translate/vsx-ops.c.inc | 3 ---
5 files changed, 34 insertions(+), 12 deletions(-)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index c646b983e329..567488b28091 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -359,9 +359,9 @@ DEF_HELPER_5(XSMADDDP, void, env, vsr, vsr, vsr, vsr)
DEF_HELPER_5(XSMSUBDP, void, env, vsr, vsr, vsr, vsr)
DEF_HELPER_5(XSNMADDDP, void, env, vsr, vsr, vsr, vsr)
DEF_HELPER_5(XSNMSUBDP, void, env, vsr, vsr, vsr, vsr)
-DEF_HELPER_4(xscmpeqdp, void, env, vsr, vsr, vsr)
-DEF_HELPER_4(xscmpgtdp, void, env, vsr, vsr, vsr)
-DEF_HELPER_4(xscmpgedp, void, env, vsr, vsr, vsr)
+DEF_HELPER_4(XSCMPEQDP, void, env, vsr, vsr, vsr)
+DEF_HELPER_4(XSCMPGTDP, void, env, vsr, vsr, vsr)
+DEF_HELPER_4(XSCMPGEDP, void, env, vsr, vsr, vsr)
DEF_HELPER_4(XSCMPEQQP, void, env, vsr, vsr, vsr)
DEF_HELPER_4(XSCMPGTQP, void, env, vsr, vsr, vsr)
DEF_HELPER_4(XSCMPGEQP, void, env, vsr, vsr, vsr)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 92327a0a718f..6fbb2d188f51 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -664,6 +664,9 @@ XSMAXCDP 111100 ..... ..... ..... 10000000 ... @XX3
XSMINCDP 111100 ..... ..... ..... 10001000 ... @XX3
XSMAXJDP 111100 ..... ..... ..... 10010000 ... @XX3
XSMINJDP 111100 ..... ..... ..... 10011000 ... @XX3
+XSCMPEQDP 111100 ..... ..... ..... 00000011 ... @XX3
+XSCMPGEDP 111100 ..... ..... ..... 00010011 ... @XX3
+XSCMPGTDP 111100 ..... ..... ..... 00001011 ... @XX3
XSCMPEQQP 111111 ..... ..... ..... 0001000100 - @X
XSCMPGEQP 111111 ..... ..... ..... 0011000100 - @X
XSCMPGTQP 111111 ..... ..... ..... 0011100100 - @X
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
index a589e6b7a54f..4d67180bec74 100644
--- a/target/ppc/fpu_helper.c
+++ b/target/ppc/fpu_helper.c
@@ -2304,9 +2304,9 @@ VSX_MADDQ(XSNMSUBQPO, NMSUB_FLGS, 0)
do_float_check_status(env, GETPC()); \
}
-VSX_SCALAR_CMP(xscmpeqdp, float64, eq, VsrD(0), 0)
-VSX_SCALAR_CMP(xscmpgedp, float64, le, VsrD(0), 1)
-VSX_SCALAR_CMP(xscmpgtdp, float64, lt, VsrD(0), 1)
+VSX_SCALAR_CMP(XSCMPEQDP, float64, eq, VsrD(0), 0)
+VSX_SCALAR_CMP(XSCMPGEDP, float64, le, VsrD(0), 1)
+VSX_SCALAR_CMP(XSCMPGTDP, float64, lt, VsrD(0), 1)
VSX_SCALAR_CMP(XSCMPEQQP, float128, eq, f128, 0)
VSX_SCALAR_CMP(XSCMPGEQP, float128, le, f128, 1)
VSX_SCALAR_CMP(XSCMPGTQP, float128, lt, f128, 1)
diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx-impl.c.inc
index 6dd20b030976..fca25c267b97 100644
--- a/target/ppc/translate/vsx-impl.c.inc
+++ b/target/ppc/translate/vsx-impl.c.inc
@@ -1052,9 +1052,6 @@ GEN_VSX_HELPER_X2(xssqrtdp, 0x16, 0x04, 0, PPC2_VSX)
GEN_VSX_HELPER_X2(xsrsqrtedp, 0x14, 0x04, 0, PPC2_VSX)
GEN_VSX_HELPER_X2_AB(xstdivdp, 0x14, 0x07, 0, PPC2_VSX)
GEN_VSX_HELPER_X1(xstsqrtdp, 0x14, 0x06, 0, PPC2_VSX)
-GEN_VSX_HELPER_X3(xscmpeqdp, 0x0C, 0x00, 0, PPC2_ISA300)
-GEN_VSX_HELPER_X3(xscmpgtdp, 0x0C, 0x01, 0, PPC2_ISA300)
-GEN_VSX_HELPER_X3(xscmpgedp, 0x0C, 0x02, 0, PPC2_ISA300)
GEN_VSX_HELPER_X2_AB(xscmpexpdp, 0x0C, 0x07, 0, PPC2_ISA300)
GEN_VSX_HELPER_R2_AB(xscmpexpqp, 0x04, 0x05, 0, PPC2_ISA300)
GEN_VSX_HELPER_X2_AB(xscmpodp, 0x0C, 0x05, 0, PPC2_VSX)
@@ -2589,6 +2586,31 @@ TRANS(XXBLENDVH, do_xxblendv, MO_16)
TRANS(XXBLENDVW, do_xxblendv, MO_32)
TRANS(XXBLENDVD, do_xxblendv, MO_64)
+static bool do_helper_XX3(DisasContext *ctx, arg_XX3 *a,
+ void (*helper)(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr))
+{
+ TCGv_ptr xt, xa, xb;
+
+ REQUIRE_INSNS_FLAGS2(ctx, ISA300);
+ REQUIRE_VSX(ctx);
+
+ xt = gen_vsr_ptr(a->xt);
+ xa = gen_vsr_ptr(a->xa);
+ xb = gen_vsr_ptr(a->xb);
+
+ helper(cpu_env, xt, xa, xb);
+
+ tcg_temp_free_ptr(xt);
+ tcg_temp_free_ptr(xa);
+ tcg_temp_free_ptr(xb);
+
+ return true;
+}
+
+TRANS(XSCMPEQDP, do_helper_XX3, gen_helper_XSCMPEQDP)
+TRANS(XSCMPGEDP, do_helper_XX3, gen_helper_XSCMPGEDP)
+TRANS(XSCMPGTDP, do_helper_XX3, gen_helper_XSCMPGTDP)
+
static bool do_xsmaxmincjdp(DisasContext *ctx, arg_XX3 *a,
void (*helper)(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr))
{
diff --git a/target/ppc/translate/vsx-ops.c.inc b/target/ppc/translate/vsx-ops.c.inc
index 34310c1fb53d..b8fd116728bd 100644
--- a/target/ppc/translate/vsx-ops.c.inc
+++ b/target/ppc/translate/vsx-ops.c.inc
@@ -186,9 +186,6 @@ GEN_XX2FORM(xssqrtdp, 0x16, 0x04, PPC2_VSX),
GEN_XX2FORM(xsrsqrtedp, 0x14, 0x04, PPC2_VSX),
GEN_XX3FORM(xstdivdp, 0x14, 0x07, PPC2_VSX),
GEN_XX2FORM(xstsqrtdp, 0x14, 0x06, PPC2_VSX),
-GEN_XX3FORM(xscmpeqdp, 0x0C, 0x00, PPC2_ISA300),
-GEN_XX3FORM(xscmpgtdp, 0x0C, 0x01, PPC2_ISA300),
-GEN_XX3FORM(xscmpgedp, 0x0C, 0x02, PPC2_ISA300),
GEN_XX3FORM(xscmpexpdp, 0x0C, 0x07, PPC2_ISA300),
GEN_VSX_XFORM_300(xscmpexpqp, 0x04, 0x05, 0x00600001),
GEN_XX2IFORM(xscmpodp, 0x0C, 0x05, PPC2_VSX),
--
2.34.1
^ permalink raw reply related [flat|nested] 89+ messages in thread* [PULL 49/87] target/ppc: Move xs{max, min}[cj]dp to use do_helper_XX3
2022-03-02 11:06 [PULL 00/87] ppc queue Cédric Le Goater
` (47 preceding siblings ...)
2022-03-02 11:07 ` [PULL 48/87] target/ppc: Move xscmp{eq,ge,gt}dp to decodetree Cédric Le Goater
@ 2022-03-02 11:07 ` Cédric Le Goater
2022-03-02 11:07 ` [PULL 50/87] target/ppc: Refactor VSX_MAX_MINC helper Cédric Le Goater
` (38 subsequent siblings)
87 siblings, 0 replies; 89+ messages in thread
From: Cédric Le Goater @ 2022-03-02 11:07 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Víctor Colombo, Peter Maydell, Richard Henderson,
Matheus Ferst, Cédric Le Goater
From: Víctor Colombo <victor.colombo@eldorado.org.br>
Also, fixes these instructions not being capitalized.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20220225210936.1749575-44-matheus.ferst@eldorado.org.br>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/helper.h | 8 ++++----
target/ppc/fpu_helper.c | 8 ++++----
target/ppc/translate/vsx-impl.c.inc | 30 ++++-------------------------
3 files changed, 12 insertions(+), 34 deletions(-)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 567488b28091..e37614f45b63 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -373,10 +373,10 @@ DEF_HELPER_4(xscmpoqp, void, env, i32, vsr, vsr)
DEF_HELPER_4(xscmpuqp, void, env, i32, vsr, vsr)
DEF_HELPER_4(xsmaxdp, void, env, vsr, vsr, vsr)
DEF_HELPER_4(xsmindp, void, env, vsr, vsr, vsr)
-DEF_HELPER_4(xsmaxcdp, void, env, vsr, vsr, vsr)
-DEF_HELPER_4(xsmincdp, void, env, vsr, vsr, vsr)
-DEF_HELPER_4(xsmaxjdp, void, env, vsr, vsr, vsr)
-DEF_HELPER_4(xsminjdp, void, env, vsr, vsr, vsr)
+DEF_HELPER_4(XSMAXCDP, void, env, vsr, vsr, vsr)
+DEF_HELPER_4(XSMINCDP, void, env, vsr, vsr, vsr)
+DEF_HELPER_4(XSMAXJDP, void, env, vsr, vsr, vsr)
+DEF_HELPER_4(XSMINJDP, void, env, vsr, vsr, vsr)
DEF_HELPER_3(xscvdphp, void, env, vsr, vsr)
DEF_HELPER_4(xscvdpqp, void, env, i32, vsr, vsr)
DEF_HELPER_3(xscvdpsp, void, env, vsr, vsr)
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
index 4d67180bec74..4bfa1c428311 100644
--- a/target/ppc/fpu_helper.c
+++ b/target/ppc/fpu_helper.c
@@ -2565,8 +2565,8 @@ void helper_##name(CPUPPCState *env, \
} \
} \
-VSX_MAX_MINC(xsmaxcdp, 1);
-VSX_MAX_MINC(xsmincdp, 0);
+VSX_MAX_MINC(XSMAXCDP, 1);
+VSX_MAX_MINC(XSMINCDP, 0);
#define VSX_MAX_MINJ(name, max) \
void helper_##name(CPUPPCState *env, \
@@ -2620,8 +2620,8 @@ void helper_##name(CPUPPCState *env, \
} \
} \
-VSX_MAX_MINJ(xsmaxjdp, 1);
-VSX_MAX_MINJ(xsminjdp, 0);
+VSX_MAX_MINJ(XSMAXJDP, 1);
+VSX_MAX_MINJ(XSMINJDP, 0);
/*
* VSX_CMP - VSX floating point compare
diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx-impl.c.inc
index fca25c267b97..5273452d1370 100644
--- a/target/ppc/translate/vsx-impl.c.inc
+++ b/target/ppc/translate/vsx-impl.c.inc
@@ -2610,32 +2610,10 @@ static bool do_helper_XX3(DisasContext *ctx, arg_XX3 *a,
TRANS(XSCMPEQDP, do_helper_XX3, gen_helper_XSCMPEQDP)
TRANS(XSCMPGEDP, do_helper_XX3, gen_helper_XSCMPGEDP)
TRANS(XSCMPGTDP, do_helper_XX3, gen_helper_XSCMPGTDP)
-
-static bool do_xsmaxmincjdp(DisasContext *ctx, arg_XX3 *a,
- void (*helper)(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr))
-{
- TCGv_ptr xt, xa, xb;
-
- REQUIRE_INSNS_FLAGS2(ctx, ISA300);
- REQUIRE_VSX(ctx);
-
- xt = gen_vsr_ptr(a->xt);
- xa = gen_vsr_ptr(a->xa);
- xb = gen_vsr_ptr(a->xb);
-
- helper(cpu_env, xt, xa, xb);
-
- tcg_temp_free_ptr(xt);
- tcg_temp_free_ptr(xa);
- tcg_temp_free_ptr(xb);
-
- return true;
-}
-
-TRANS(XSMAXCDP, do_xsmaxmincjdp, gen_helper_xsmaxcdp)
-TRANS(XSMINCDP, do_xsmaxmincjdp, gen_helper_xsmincdp)
-TRANS(XSMAXJDP, do_xsmaxmincjdp, gen_helper_xsmaxjdp)
-TRANS(XSMINJDP, do_xsmaxmincjdp, gen_helper_xsminjdp)
+TRANS(XSMAXCDP, do_helper_XX3, gen_helper_XSMAXCDP)
+TRANS(XSMINCDP, do_helper_XX3, gen_helper_XSMINCDP)
+TRANS(XSMAXJDP, do_helper_XX3, gen_helper_XSMAXJDP)
+TRANS(XSMINJDP, do_helper_XX3, gen_helper_XSMINJDP)
static bool do_helper_X(arg_X *a,
void (*helper)(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr))
--
2.34.1
^ permalink raw reply related [flat|nested] 89+ messages in thread* [PULL 50/87] target/ppc: Refactor VSX_MAX_MINC helper
2022-03-02 11:06 [PULL 00/87] ppc queue Cédric Le Goater
` (48 preceding siblings ...)
2022-03-02 11:07 ` [PULL 49/87] target/ppc: Move xs{max, min}[cj]dp to use do_helper_XX3 Cédric Le Goater
@ 2022-03-02 11:07 ` Cédric Le Goater
2022-03-02 11:07 ` [PULL 51/87] target/ppc: Implement xs{max,min}cqp Cédric Le Goater
` (37 subsequent siblings)
87 siblings, 0 replies; 89+ messages in thread
From: Cédric Le Goater @ 2022-03-02 11:07 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Víctor Colombo, Peter Maydell, Matheus Ferst,
Cédric Le Goater
From: Víctor Colombo <victor.colombo@eldorado.org.br>
Refactor xs{max,min}cdp VSX_MAX_MINC helper to prepare for
xs{max,min}cqp implementation.
Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20220225210936.1749575-45-matheus.ferst@eldorado.org.br>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/fpu_helper.c | 41 +++++++++++++++++------------------------
1 file changed, 17 insertions(+), 24 deletions(-)
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
index 4bfa1c428311..0aaf529ac8d0 100644
--- a/target/ppc/fpu_helper.c
+++ b/target/ppc/fpu_helper.c
@@ -2533,40 +2533,33 @@ VSX_MAX_MIN(xsmindp, minnum, 1, float64, VsrD(0))
VSX_MAX_MIN(xvmindp, minnum, 2, float64, VsrD(i))
VSX_MAX_MIN(xvminsp, minnum, 4, float32, VsrW(i))
-#define VSX_MAX_MINC(name, max) \
+#define VSX_MAX_MINC(name, max, tp, fld) \
void helper_##name(CPUPPCState *env, \
ppc_vsr_t *xt, ppc_vsr_t *xa, ppc_vsr_t *xb) \
{ \
ppc_vsr_t t = { }; \
- bool vxsnan_flag = false, vex_flag = false; \
+ bool first; \
\
- if (unlikely(float64_is_any_nan(xa->VsrD(0)) || \
- float64_is_any_nan(xb->VsrD(0)))) { \
- if (float64_is_signaling_nan(xa->VsrD(0), &env->fp_status) || \
- float64_is_signaling_nan(xb->VsrD(0), &env->fp_status)) { \
- vxsnan_flag = true; \
- } \
- t.VsrD(0) = xb->VsrD(0); \
- } else if ((max && \
- !float64_lt(xa->VsrD(0), xb->VsrD(0), &env->fp_status)) || \
- (!max && \
- float64_lt(xa->VsrD(0), xb->VsrD(0), &env->fp_status))) { \
- t.VsrD(0) = xa->VsrD(0); \
+ if (max) { \
+ first = tp##_le_quiet(xb->fld, xa->fld, &env->fp_status); \
} else { \
- t.VsrD(0) = xb->VsrD(0); \
+ first = tp##_lt_quiet(xa->fld, xb->fld, &env->fp_status); \
} \
\
- vex_flag = fpscr_ve & vxsnan_flag; \
- if (vxsnan_flag) { \
- float_invalid_op_vxsnan(env, GETPC()); \
- } \
- if (!vex_flag) { \
- *xt = t; \
+ if (first) { \
+ t.fld = xa->fld; \
+ } else { \
+ t.fld = xb->fld; \
+ if (env->fp_status.float_exception_flags & float_flag_invalid_snan) { \
+ float_invalid_op_vxsnan(env, GETPC()); \
+ } \
} \
-} \
+ \
+ *xt = t; \
+}
-VSX_MAX_MINC(XSMAXCDP, 1);
-VSX_MAX_MINC(XSMINCDP, 0);
+VSX_MAX_MINC(XSMAXCDP, true, float64, VsrD(0));
+VSX_MAX_MINC(XSMINCDP, false, float64, VsrD(0));
#define VSX_MAX_MINJ(name, max) \
void helper_##name(CPUPPCState *env, \
--
2.34.1
^ permalink raw reply related [flat|nested] 89+ messages in thread* [PULL 51/87] target/ppc: Implement xs{max,min}cqp
2022-03-02 11:06 [PULL 00/87] ppc queue Cédric Le Goater
` (49 preceding siblings ...)
2022-03-02 11:07 ` [PULL 50/87] target/ppc: Refactor VSX_MAX_MINC helper Cédric Le Goater
@ 2022-03-02 11:07 ` Cédric Le Goater
2022-03-02 11:07 ` [PULL 52/87] target/ppc: Implement xvcvbf16spn and xvcvspbf16 instructions Cédric Le Goater
` (36 subsequent siblings)
87 siblings, 0 replies; 89+ messages in thread
From: Cédric Le Goater @ 2022-03-02 11:07 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Víctor Colombo, Peter Maydell, Matheus Ferst,
Cédric Le Goater
From: Víctor Colombo <victor.colombo@eldorado.org.br>
Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20220225210936.1749575-46-matheus.ferst@eldorado.org.br>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/helper.h | 2 ++
target/ppc/insn32.decode | 3 +++
target/ppc/fpu_helper.c | 2 ++
target/ppc/translate/vsx-impl.c.inc | 2 ++
4 files changed, 9 insertions(+)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index e37614f45b63..0ca28555f2d9 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -377,6 +377,8 @@ DEF_HELPER_4(XSMAXCDP, void, env, vsr, vsr, vsr)
DEF_HELPER_4(XSMINCDP, void, env, vsr, vsr, vsr)
DEF_HELPER_4(XSMAXJDP, void, env, vsr, vsr, vsr)
DEF_HELPER_4(XSMINJDP, void, env, vsr, vsr, vsr)
+DEF_HELPER_4(XSMAXCQP, void, env, vsr, vsr, vsr)
+DEF_HELPER_4(XSMINCQP, void, env, vsr, vsr, vsr)
DEF_HELPER_3(xscvdphp, void, env, vsr, vsr)
DEF_HELPER_4(xscvdpqp, void, env, i32, vsr, vsr)
DEF_HELPER_3(xscvdpsp, void, env, vsr, vsr)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 6fbb2d188f51..126cadadb8b0 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -664,6 +664,9 @@ XSMAXCDP 111100 ..... ..... ..... 10000000 ... @XX3
XSMINCDP 111100 ..... ..... ..... 10001000 ... @XX3
XSMAXJDP 111100 ..... ..... ..... 10010000 ... @XX3
XSMINJDP 111100 ..... ..... ..... 10011000 ... @XX3
+XSMAXCQP 111111 ..... ..... ..... 1010100100 - @X
+XSMINCQP 111111 ..... ..... ..... 1011100100 - @X
+
XSCMPEQDP 111100 ..... ..... ..... 00000011 ... @XX3
XSCMPGEDP 111100 ..... ..... ..... 00010011 ... @XX3
XSCMPGTDP 111100 ..... ..... ..... 00001011 ... @XX3
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
index 0aaf529ac8d0..714400731611 100644
--- a/target/ppc/fpu_helper.c
+++ b/target/ppc/fpu_helper.c
@@ -2560,6 +2560,8 @@ void helper_##name(CPUPPCState *env, \
VSX_MAX_MINC(XSMAXCDP, true, float64, VsrD(0));
VSX_MAX_MINC(XSMINCDP, false, float64, VsrD(0));
+VSX_MAX_MINC(XSMAXCQP, true, float128, f128);
+VSX_MAX_MINC(XSMINCQP, false, float128, f128);
#define VSX_MAX_MINJ(name, max) \
void helper_##name(CPUPPCState *env, \
diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx-impl.c.inc
index 5273452d1370..3b0c8bf3ca07 100644
--- a/target/ppc/translate/vsx-impl.c.inc
+++ b/target/ppc/translate/vsx-impl.c.inc
@@ -2645,6 +2645,8 @@ static bool do_xscmpqp(DisasContext *ctx, arg_X *a,
TRANS(XSCMPEQQP, do_xscmpqp, gen_helper_XSCMPEQQP)
TRANS(XSCMPGEQP, do_xscmpqp, gen_helper_XSCMPGEQP)
TRANS(XSCMPGTQP, do_xscmpqp, gen_helper_XSCMPGTQP)
+TRANS(XSMAXCQP, do_xscmpqp, gen_helper_XSMAXCQP)
+TRANS(XSMINCQP, do_xscmpqp, gen_helper_XSMINCQP)
#undef GEN_XX2FORM
#undef GEN_XX3FORM
--
2.34.1
^ permalink raw reply related [flat|nested] 89+ messages in thread* [PULL 52/87] target/ppc: Implement xvcvbf16spn and xvcvspbf16 instructions
2022-03-02 11:06 [PULL 00/87] ppc queue Cédric Le Goater
` (50 preceding siblings ...)
2022-03-02 11:07 ` [PULL 51/87] target/ppc: Implement xs{max,min}cqp Cédric Le Goater
@ 2022-03-02 11:07 ` Cédric Le Goater
2022-03-02 11:07 ` [PULL 53/87] target/ppc: implement plxsd/pstxsd Cédric Le Goater
` (35 subsequent siblings)
87 siblings, 0 replies; 89+ messages in thread
From: Cédric Le Goater @ 2022-03-02 11:07 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Víctor Colombo, Peter Maydell, Richard Henderson,
Matheus Ferst, Cédric Le Goater
From: Víctor Colombo <victor.colombo@eldorado.org.br>
Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220225210936.1749575-47-matheus.ferst@eldorado.org.br>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/helper.h | 1 +
target/ppc/insn32.decode | 11 +++++++---
target/ppc/fpu_helper.c | 18 +++++++++++++++++
target/ppc/translate/vsx-impl.c.inc | 31 ++++++++++++++++++++++++++++-
4 files changed, 57 insertions(+), 4 deletions(-)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 0ca28555f2d9..57da11c77ec9 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -492,6 +492,7 @@ DEF_HELPER_FLAGS_4(xvcmpnesp, TCG_CALL_NO_RWG, i32, env, vsr, vsr, vsr)
DEF_HELPER_3(xvcvspdp, void, env, vsr, vsr)
DEF_HELPER_3(xvcvsphp, void, env, vsr, vsr)
DEF_HELPER_3(xvcvhpsp, void, env, vsr, vsr)
+DEF_HELPER_3(XVCVSPBF16, void, env, vsr, vsr)
DEF_HELPER_3(xvcvspsxds, void, env, vsr, vsr)
DEF_HELPER_3(xvcvspsxws, void, env, vsr, vsr)
DEF_HELPER_3(xvcvspuxds, void, env, vsr, vsr)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 126cadadb8b0..fede42f5ce33 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -152,8 +152,11 @@
%xx_xb 1:1 11:5
%xx_xa 2:1 16:5
%xx_xc 3:1 6:5
-&XX2 xt xb uim:uint8_t
-@XX2 ...... ..... ... uim:2 ..... ......... .. &XX2 xt=%xx_xt xb=%xx_xb
+&XX2 xt xb
+@XX2 ...... ..... ..... ..... ......... .. &XX2 xt=%xx_xt xb=%xx_xb
+
+&XX2_uim2 xt xb uim:uint8_t
+@XX2_uim2 ...... ..... ... uim:2 ..... ......... .. &XX2_uim2 xt=%xx_xt xb=%xx_xb
&XX2_bf_xb bf xb
@XX2_bf_xb ...... bf:3 .. ..... ..... ......... . . &XX2_bf_xb xb=%xx_xb
@@ -637,7 +640,7 @@ XSNMSUBQP 111111 ..... ..... ..... 0111100100 . @X_rc
## VSX splat instruction
XXSPLTIB 111100 ..... 00 ........ 0101101000 . @X_imm8
-XXSPLTW 111100 ..... ---.. ..... 010100100 . . @XX2
+XXSPLTW 111100 ..... ---.. ..... 010100100 . . @XX2_uim2
## VSX Permute Instructions
@@ -677,6 +680,8 @@ XSCMPGTQP 111111 ..... ..... ..... 0011100100 - @X
## VSX Binary Floating-Point Convert Instructions
XSCVQPDP 111111 ..... 10100 ..... 1101000100 . @X_tb_rc
+XVCVBF16SPN 111100 ..... 10000 ..... 111011011 .. @XX2
+XVCVSPBF16 111100 ..... 10001 ..... 111011011 .. @XX2
## VSX Vector Test Least-Significant Bit by Byte Instruction
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
index 714400731611..8f970288f50e 100644
--- a/target/ppc/fpu_helper.c
+++ b/target/ppc/fpu_helper.c
@@ -2785,6 +2785,24 @@ VSX_CVT_FP_TO_FP_HP(xscvhpdp, 1, float16, float64, VsrH(3), VsrD(0), 1)
VSX_CVT_FP_TO_FP_HP(xvcvsphp, 4, float32, float16, VsrW(i), VsrH(2 * i + 1), 0)
VSX_CVT_FP_TO_FP_HP(xvcvhpsp, 4, float16, float32, VsrH(2 * i + 1), VsrW(i), 0)
+void helper_XVCVSPBF16(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb)
+{
+ ppc_vsr_t t = { };
+ int i, status;
+
+ for (i = 0; i < 4; i++) {
+ t.VsrH(2 * i + 1) = float32_to_bfloat16(xb->VsrW(i), &env->fp_status);
+ }
+
+ status = get_float_exception_flags(&env->fp_status);
+ if (unlikely(status & float_flag_invalid_snan)) {
+ float_invalid_op_vxsnan(env, GETPC());
+ }
+
+ *xt = t;
+ do_float_check_status(env, GETPC());
+}
+
void helper_XSCVQPDP(CPUPPCState *env, uint32_t ro, ppc_vsr_t *xt,
ppc_vsr_t *xb)
{
diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx-impl.c.inc
index 3b0c8bf3ca07..0344c47eed14 100644
--- a/target/ppc/translate/vsx-impl.c.inc
+++ b/target/ppc/translate/vsx-impl.c.inc
@@ -1590,7 +1590,7 @@ static bool trans_XXSEL(DisasContext *ctx, arg_XX4 *a)
return true;
}
-static bool trans_XXSPLTW(DisasContext *ctx, arg_XX2 *a)
+static bool trans_XXSPLTW(DisasContext *ctx, arg_XX2_uim2 *a)
{
int tofs, bofs;
@@ -2648,6 +2648,35 @@ TRANS(XSCMPGTQP, do_xscmpqp, gen_helper_XSCMPGTQP)
TRANS(XSMAXCQP, do_xscmpqp, gen_helper_XSMAXCQP)
TRANS(XSMINCQP, do_xscmpqp, gen_helper_XSMINCQP)
+static bool trans_XVCVSPBF16(DisasContext *ctx, arg_XX2 *a)
+{
+ TCGv_ptr xt, xb;
+
+ REQUIRE_INSNS_FLAGS2(ctx, ISA310);
+ REQUIRE_VSX(ctx);
+
+ xt = gen_vsr_ptr(a->xt);
+ xb = gen_vsr_ptr(a->xb);
+
+ gen_helper_XVCVSPBF16(cpu_env, xt, xb);
+
+ tcg_temp_free_ptr(xt);
+ tcg_temp_free_ptr(xb);
+
+ return true;
+}
+
+static bool trans_XVCVBF16SPN(DisasContext *ctx, arg_XX2 *a)
+{
+ REQUIRE_INSNS_FLAGS2(ctx, ISA310);
+ REQUIRE_VSX(ctx);
+
+ tcg_gen_gvec_shli(MO_32, vsr_full_offset(a->xt), vsr_full_offset(a->xb),
+ 16, 16, 16);
+
+ return true;
+}
+
#undef GEN_XX2FORM
#undef GEN_XX3FORM
#undef GEN_XX2IFORM
--
2.34.1
^ permalink raw reply related [flat|nested] 89+ messages in thread* [PULL 53/87] target/ppc: implement plxsd/pstxsd
2022-03-02 11:06 [PULL 00/87] ppc queue Cédric Le Goater
` (51 preceding siblings ...)
2022-03-02 11:07 ` [PULL 52/87] target/ppc: Implement xvcvbf16spn and xvcvspbf16 instructions Cédric Le Goater
@ 2022-03-02 11:07 ` Cédric Le Goater
2022-03-02 11:07 ` [PULL 54/87] target/ppc: implement plxssp/pstxssp Cédric Le Goater
` (34 subsequent siblings)
87 siblings, 0 replies; 89+ messages in thread
From: Cédric Le Goater @ 2022-03-02 11:07 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Richard Henderson, Leandro Lupori, Matheus Ferst,
Cédric Le Goater
From: Leandro Lupori <leandro.lupori@eldorado.org.br>
Implement instructions plxsd/pstxsd and port lxsd/stxsd to decode
tree.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Leandro Lupori <leandro.lupori@eldorado.org.br>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20220225210936.1749575-48-matheus.ferst@eldorado.org.br>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/insn32.decode | 2 ++
target/ppc/insn64.decode | 10 ++++++
target/ppc/translate.c | 14 ++------
target/ppc/translate/vsx-impl.c.inc | 55 +++++++++++++++++++++++++++--
4 files changed, 67 insertions(+), 14 deletions(-)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index fede42f5ce33..37b64705030a 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -602,6 +602,8 @@ VCLRRB 000100 ..... ..... ..... 00111001101 @VX
# VSX Load/Store Instructions
+LXSD 111001 ..... ..... .............. 10 @DS
+STXSD 111101 ..... ..... .............. 10 @DS
LXV 111101 ..... ..... ............ . 001 @DQ_TSX
STXV 111101 ..... ..... ............ . 101 @DQ_TSX
LXVP 000110 ..... ..... ............ 0000 @DQ_TSXP
diff --git a/target/ppc/insn64.decode b/target/ppc/insn64.decode
index fdb859f62dd8..b7426f5b2481 100644
--- a/target/ppc/insn64.decode
+++ b/target/ppc/insn64.decode
@@ -32,6 +32,10 @@
...... ..... ra:5 ................ \
&PLS_D si=%pls_si rt=%rt_tsxp
+@8LS_D ...... .. . .. r:1 .. .................. \
+ ...... rt:5 ra:5 ................ \
+ &PLS_D si=%pls_si
+
# Format 8RR:D
%8rr_si 32:s16 0:16
%8rr_xt 16:1 21:5
@@ -180,6 +184,12 @@ PSTFD 000001 10 0--.-- .................. \
### VSX instructions
+PLXSD 000001 00 0--.-- .................. \
+ 101010 ..... ..... ................ @8LS_D
+
+PSTXSD 000001 00 0--.-- .................. \
+ 101110 ..... ..... ................ @8LS_D
+
PLXV 000001 00 0--.-- .................. \
11001 ...... ..... ................ @8LS_D_TSX
PSTXV 000001 00 0--.-- .................. \
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index b46a11386eee..1ef2eeeead90 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -6668,7 +6668,7 @@ static bool resolve_PLS_D(DisasContext *ctx, arg_D *d, arg_PLS_D *a)
#include "translate/branch-impl.c.inc"
-/* Handles lfdp, lxsd, lxssp */
+/* Handles lfdp, lxssp */
static void gen_dform39(DisasContext *ctx)
{
switch (ctx->opcode & 0x3) {
@@ -6677,11 +6677,6 @@ static void gen_dform39(DisasContext *ctx)
return gen_lfdp(ctx);
}
break;
- case 2: /* lxsd */
- if (ctx->insns_flags2 & PPC2_ISA300) {
- return gen_lxsd(ctx);
- }
- break;
case 3: /* lxssp */
if (ctx->insns_flags2 & PPC2_ISA300) {
return gen_lxssp(ctx);
@@ -6691,7 +6686,7 @@ static void gen_dform39(DisasContext *ctx)
return gen_invalid(ctx);
}
-/* handles stfdp, lxv, stxsd, stxssp lxvx */
+/* handles stfdp, lxv, stxssp lxvx */
static void gen_dform3D(DisasContext *ctx)
{
if ((ctx->opcode & 3) != 1) { /* DS-FORM */
@@ -6701,11 +6696,6 @@ static void gen_dform3D(DisasContext *ctx)
return gen_stfdp(ctx);
}
break;
- case 2: /* stxsd */
- if (ctx->insns_flags2 & PPC2_ISA300) {
- return gen_stxsd(ctx);
- }
- break;
case 3: /* stxssp */
if (ctx->insns_flags2 & PPC2_ISA300) {
return gen_stxssp(ctx);
diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx-impl.c.inc
index 0344c47eed14..a6e9417f2d5f 100644
--- a/target/ppc/translate/vsx-impl.c.inc
+++ b/target/ppc/translate/vsx-impl.c.inc
@@ -309,7 +309,6 @@ static void gen_##name(DisasContext *ctx) \
tcg_temp_free_i64(xth); \
}
-VSX_LOAD_SCALAR_DS(lxsd, ld64_i64)
VSX_LOAD_SCALAR_DS(lxssp, ld32fs)
#define VSX_STORE_SCALAR(name, operation) \
@@ -482,7 +481,6 @@ static void gen_##name(DisasContext *ctx) \
tcg_temp_free_i64(xth); \
}
-VSX_STORE_SCALAR_DS(stxsd, st64_i64)
VSX_STORE_SCALAR_DS(stxssp, st32fs)
static void gen_mfvsrwz(DisasContext *ctx)
@@ -2298,6 +2296,57 @@ static bool do_lstxv_X(DisasContext *ctx, arg_X *a, bool store, bool paired)
return do_lstxv(ctx, a->ra, cpu_gpr[a->rb], a->rt, store, paired);
}
+static bool do_lstxsd(DisasContext *ctx, int rt, int ra, TCGv displ, bool store)
+{
+ TCGv ea;
+ TCGv_i64 xt;
+ MemOp mop;
+
+ if (store) {
+ REQUIRE_VECTOR(ctx);
+ } else {
+ REQUIRE_VSX(ctx);
+ }
+
+ xt = tcg_temp_new_i64();
+ mop = DEF_MEMOP(MO_UQ);
+
+ gen_set_access_type(ctx, ACCESS_INT);
+ ea = do_ea_calc(ctx, ra, displ);
+
+ if (store) {
+ get_cpu_vsr(xt, rt + 32, true);
+ tcg_gen_qemu_st_i64(xt, ea, ctx->mem_idx, mop);
+ } else {
+ tcg_gen_qemu_ld_i64(xt, ea, ctx->mem_idx, mop);
+ set_cpu_vsr(rt + 32, xt, true);
+ set_cpu_vsr(rt + 32, tcg_constant_i64(0), false);
+ }
+
+ tcg_temp_free(ea);
+ tcg_temp_free_i64(xt);
+
+ return true;
+}
+
+static bool do_lstxsd_DS(DisasContext *ctx, arg_D *a, bool store)
+{
+ return do_lstxsd(ctx, a->rt, a->ra, tcg_constant_tl(a->si), store);
+}
+
+static bool do_plstxsd_PLS_D(DisasContext *ctx, arg_PLS_D *a, bool store)
+{
+ arg_D d;
+
+ if (!resolve_PLS_D(ctx, &d, a)) {
+ return true;
+ }
+
+ return do_lstxsd(ctx, d.rt, d.ra, tcg_constant_tl(d.si), store);
+}
+
+TRANS_FLAGS2(ISA300, LXSD, do_lstxsd_DS, false)
+TRANS_FLAGS2(ISA300, STXSD, do_lstxsd_DS, true)
TRANS_FLAGS2(ISA300, STXV, do_lstxv_D, true, false)
TRANS_FLAGS2(ISA300, LXV, do_lstxv_D, false, false)
TRANS_FLAGS2(ISA310, STXVP, do_lstxv_D, true, true)
@@ -2306,6 +2355,8 @@ TRANS_FLAGS2(ISA300, STXVX, do_lstxv_X, true, false)
TRANS_FLAGS2(ISA300, LXVX, do_lstxv_X, false, false)
TRANS_FLAGS2(ISA310, STXVPX, do_lstxv_X, true, true)
TRANS_FLAGS2(ISA310, LXVPX, do_lstxv_X, false, true)
+TRANS64_FLAGS2(ISA310, PLXSD, do_plstxsd_PLS_D, false)
+TRANS64_FLAGS2(ISA310, PSTXSD, do_plstxsd_PLS_D, true)
TRANS64_FLAGS2(ISA310, PSTXV, do_lstxv_PLS_D, true, false)
TRANS64_FLAGS2(ISA310, PLXV, do_lstxv_PLS_D, false, false)
TRANS64_FLAGS2(ISA310, PSTXVP, do_lstxv_PLS_D, true, true)
--
2.34.1
^ permalink raw reply related [flat|nested] 89+ messages in thread* [PULL 54/87] target/ppc: implement plxssp/pstxssp
2022-03-02 11:06 [PULL 00/87] ppc queue Cédric Le Goater
` (52 preceding siblings ...)
2022-03-02 11:07 ` [PULL 53/87] target/ppc: implement plxsd/pstxsd Cédric Le Goater
@ 2022-03-02 11:07 ` Cédric Le Goater
2022-03-02 11:07 ` [PULL 55/87] target/ppc: implement lxvr[bhwd]/stxvr[bhwd]x Cédric Le Goater
` (33 subsequent siblings)
87 siblings, 0 replies; 89+ messages in thread
From: Cédric Le Goater @ 2022-03-02 11:07 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Richard Henderson, Leandro Lupori, Matheus Ferst,
Cédric Le Goater
From: Leandro Lupori <leandro.lupori@eldorado.org.br>
Implement instructions plxssp/pstxssp and port lxssp/stxssp to
decode tree.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Leandro Lupori <leandro.lupori@eldorado.org.br>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20220225210936.1749575-49-matheus.ferst@eldorado.org.br>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/insn32.decode | 2 +
target/ppc/insn64.decode | 6 ++
target/ppc/translate.c | 29 +++------
target/ppc/translate/vsx-impl.c.inc | 93 +++++++++++++++--------------
4 files changed, 62 insertions(+), 68 deletions(-)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 37b64705030a..1641a3189417 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -604,6 +604,8 @@ VCLRRB 000100 ..... ..... ..... 00111001101 @VX
LXSD 111001 ..... ..... .............. 10 @DS
STXSD 111101 ..... ..... .............. 10 @DS
+LXSSP 111001 ..... ..... .............. 11 @DS
+STXSSP 111101 ..... ..... .............. 11 @DS
LXV 111101 ..... ..... ............ . 001 @DQ_TSX
STXV 111101 ..... ..... ............ . 101 @DQ_TSX
LXVP 000110 ..... ..... ............ 0000 @DQ_TSXP
diff --git a/target/ppc/insn64.decode b/target/ppc/insn64.decode
index b7426f5b2481..691e8fe6c0bb 100644
--- a/target/ppc/insn64.decode
+++ b/target/ppc/insn64.decode
@@ -190,6 +190,12 @@ PLXSD 000001 00 0--.-- .................. \
PSTXSD 000001 00 0--.-- .................. \
101110 ..... ..... ................ @8LS_D
+PLXSSP 000001 00 0--.-- .................. \
+ 101011 ..... ..... ................ @8LS_D
+
+PSTXSSP 000001 00 0--.-- .................. \
+ 101111 ..... ..... ................ @8LS_D
+
PLXV 000001 00 0--.-- .................. \
11001 ...... ..... ................ @8LS_D_TSX
PSTXV 000001 00 0--.-- .................. \
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 1ef2eeeead90..408ae26173de 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -6668,39 +6668,24 @@ static bool resolve_PLS_D(DisasContext *ctx, arg_D *d, arg_PLS_D *a)
#include "translate/branch-impl.c.inc"
-/* Handles lfdp, lxssp */
+/* Handles lfdp */
static void gen_dform39(DisasContext *ctx)
{
- switch (ctx->opcode & 0x3) {
- case 0: /* lfdp */
+ if ((ctx->opcode & 0x3) == 0) {
if (ctx->insns_flags2 & PPC2_ISA205) {
return gen_lfdp(ctx);
}
- break;
- case 3: /* lxssp */
- if (ctx->insns_flags2 & PPC2_ISA300) {
- return gen_lxssp(ctx);
- }
- break;
}
return gen_invalid(ctx);
}
-/* handles stfdp, lxv, stxssp lxvx */
+/* Handles stfdp */
static void gen_dform3D(DisasContext *ctx)
{
- if ((ctx->opcode & 3) != 1) { /* DS-FORM */
- switch (ctx->opcode & 0x3) {
- case 0: /* stfdp */
- if (ctx->insns_flags2 & PPC2_ISA205) {
- return gen_stfdp(ctx);
- }
- break;
- case 3: /* stxssp */
- if (ctx->insns_flags2 & PPC2_ISA300) {
- return gen_stxssp(ctx);
- }
- break;
+ if ((ctx->opcode & 3) == 0) { /* DS-FORM */
+ /* stfdp */
+ if (ctx->insns_flags2 & PPC2_ISA205) {
+ return gen_stfdp(ctx);
}
}
return gen_invalid(ctx);
diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx-impl.c.inc
index a6e9417f2d5f..a980a79b7880 100644
--- a/target/ppc/translate/vsx-impl.c.inc
+++ b/target/ppc/translate/vsx-impl.c.inc
@@ -288,29 +288,6 @@ VSX_VECTOR_LOAD_STORE_LENGTH(stxvl)
VSX_VECTOR_LOAD_STORE_LENGTH(stxvll)
#endif
-#define VSX_LOAD_SCALAR_DS(name, operation) \
-static void gen_##name(DisasContext *ctx) \
-{ \
- TCGv EA; \
- TCGv_i64 xth; \
- \
- if (unlikely(!ctx->altivec_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_VPU); \
- return; \
- } \
- xth = tcg_temp_new_i64(); \
- gen_set_access_type(ctx, ACCESS_INT); \
- EA = tcg_temp_new(); \
- gen_addr_imm_index(ctx, EA, 0x03); \
- gen_qemu_##operation(ctx, xth, EA); \
- set_cpu_vsr(rD(ctx->opcode) + 32, xth, true); \
- /* NOTE: cpu_vsrl is undefined */ \
- tcg_temp_free(EA); \
- tcg_temp_free_i64(xth); \
-}
-
-VSX_LOAD_SCALAR_DS(lxssp, ld32fs)
-
#define VSX_STORE_SCALAR(name, operation) \
static void gen_##name(DisasContext *ctx) \
{ \
@@ -460,29 +437,6 @@ static void gen_stxvb16x(DisasContext *ctx)
tcg_temp_free_i64(xsl);
}
-#define VSX_STORE_SCALAR_DS(name, operation) \
-static void gen_##name(DisasContext *ctx) \
-{ \
- TCGv EA; \
- TCGv_i64 xth; \
- \
- if (unlikely(!ctx->altivec_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_VPU); \
- return; \
- } \
- xth = tcg_temp_new_i64(); \
- get_cpu_vsr(xth, rD(ctx->opcode) + 32, true); \
- gen_set_access_type(ctx, ACCESS_INT); \
- EA = tcg_temp_new(); \
- gen_addr_imm_index(ctx, EA, 0x03); \
- gen_qemu_##operation(ctx, xth, EA); \
- /* NOTE: cpu_vsrl is undefined */ \
- tcg_temp_free(EA); \
- tcg_temp_free_i64(xth); \
-}
-
-VSX_STORE_SCALAR_DS(stxssp, st32fs)
-
static void gen_mfvsrwz(DisasContext *ctx)
{
if (xS(ctx->opcode) < 32) {
@@ -2345,8 +2299,53 @@ static bool do_plstxsd_PLS_D(DisasContext *ctx, arg_PLS_D *a, bool store)
return do_lstxsd(ctx, d.rt, d.ra, tcg_constant_tl(d.si), store);
}
+static bool do_lstxssp(DisasContext *ctx, int rt, int ra, TCGv displ, bool store)
+{
+ TCGv ea;
+ TCGv_i64 xt;
+
+ REQUIRE_VECTOR(ctx);
+
+ xt = tcg_temp_new_i64();
+
+ gen_set_access_type(ctx, ACCESS_INT);
+ ea = do_ea_calc(ctx, ra, displ);
+
+ if (store) {
+ get_cpu_vsr(xt, rt + 32, true);
+ gen_qemu_st32fs(ctx, xt, ea);
+ } else {
+ gen_qemu_ld32fs(ctx, xt, ea);
+ set_cpu_vsr(rt + 32, xt, true);
+ set_cpu_vsr(rt + 32, tcg_constant_i64(0), false);
+ }
+
+ tcg_temp_free(ea);
+ tcg_temp_free_i64(xt);
+
+ return true;
+}
+
+static bool do_lstxssp_DS(DisasContext *ctx, arg_D *a, bool store)
+{
+ return do_lstxssp(ctx, a->rt, a->ra, tcg_constant_tl(a->si), store);
+}
+
+static bool do_plstxssp_PLS_D(DisasContext *ctx, arg_PLS_D *a, bool store)
+{
+ arg_D d;
+
+ if (!resolve_PLS_D(ctx, &d, a)) {
+ return true;
+ }
+
+ return do_lstxssp(ctx, d.rt, d.ra, tcg_constant_tl(d.si), store);
+}
+
TRANS_FLAGS2(ISA300, LXSD, do_lstxsd_DS, false)
TRANS_FLAGS2(ISA300, STXSD, do_lstxsd_DS, true)
+TRANS_FLAGS2(ISA300, LXSSP, do_lstxssp_DS, false)
+TRANS_FLAGS2(ISA300, STXSSP, do_lstxssp_DS, true)
TRANS_FLAGS2(ISA300, STXV, do_lstxv_D, true, false)
TRANS_FLAGS2(ISA300, LXV, do_lstxv_D, false, false)
TRANS_FLAGS2(ISA310, STXVP, do_lstxv_D, true, true)
@@ -2357,6 +2356,8 @@ TRANS_FLAGS2(ISA310, STXVPX, do_lstxv_X, true, true)
TRANS_FLAGS2(ISA310, LXVPX, do_lstxv_X, false, true)
TRANS64_FLAGS2(ISA310, PLXSD, do_plstxsd_PLS_D, false)
TRANS64_FLAGS2(ISA310, PSTXSD, do_plstxsd_PLS_D, true)
+TRANS64_FLAGS2(ISA310, PLXSSP, do_plstxssp_PLS_D, false)
+TRANS64_FLAGS2(ISA310, PSTXSSP, do_plstxssp_PLS_D, true)
TRANS64_FLAGS2(ISA310, PSTXV, do_lstxv_PLS_D, true, false)
TRANS64_FLAGS2(ISA310, PLXV, do_lstxv_PLS_D, false, false)
TRANS64_FLAGS2(ISA310, PSTXVP, do_lstxv_PLS_D, true, true)
--
2.34.1
^ permalink raw reply related [flat|nested] 89+ messages in thread* [PULL 55/87] target/ppc: implement lxvr[bhwd]/stxvr[bhwd]x
2022-03-02 11:06 [PULL 00/87] ppc queue Cédric Le Goater
` (53 preceding siblings ...)
2022-03-02 11:07 ` [PULL 54/87] target/ppc: implement plxssp/pstxssp Cédric Le Goater
@ 2022-03-02 11:07 ` Cédric Le Goater
2022-03-02 11:07 ` [PULL 56/87] ppc/xive2: Introduce a XIVE2 core framework Cédric Le Goater
` (32 subsequent siblings)
87 siblings, 0 replies; 89+ messages in thread
From: Cédric Le Goater @ 2022-03-02 11:07 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Cédric Le Goater, Richard Henderson,
Lucas Coutinho, Matheus Ferst
From: Lucas Coutinho <lucas.coutinho@eldorado.org.br>
Implement the following PowerISA v3.1 instuctions:
lxvrbx: Load VSX Vector Rightmost Byte Indexed X-form
lxvrhx: Load VSX Vector Rightmost Halfword Indexed X-form
lxvrwx: Load VSX Vector Rightmost Word Indexed X-form
lxvrdx: Load VSX Vector Rightmost Doubleword Indexed X-form
stxvrbx: Store VSX Vector Rightmost Byte Indexed X-form
stxvrhx: Store VSX Vector Rightmost Halfword Indexed X-form
stxvrwx: Store VSX Vector Rightmost Word Indexed X-form
stxvrdx: Store VSX Vector Rightmost Doubleword Indexed X-form
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Lucas Coutinho <lucas.coutinho@eldorado.org.br>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20220225210936.1749575-50-matheus.ferst@eldorado.org.br>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/insn32.decode | 8 +++++++
target/ppc/translate/vsx-impl.c.inc | 35 +++++++++++++++++++++++++++++
2 files changed, 43 insertions(+)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 1641a3189417..ac2d3da9a781 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -614,6 +614,14 @@ LXVX 011111 ..... ..... ..... 0100 - 01100 . @X_TSX
STXVX 011111 ..... ..... ..... 0110001100 . @X_TSX
LXVPX 011111 ..... ..... ..... 0101001101 - @X_TSXP
STXVPX 011111 ..... ..... ..... 0111001101 - @X_TSXP
+LXVRBX 011111 ..... ..... ..... 0000001101 . @X_TSX
+LXVRHX 011111 ..... ..... ..... 0000101101 . @X_TSX
+LXVRWX 011111 ..... ..... ..... 0001001101 . @X_TSX
+LXVRDX 011111 ..... ..... ..... 0001101101 . @X_TSX
+STXVRBX 011111 ..... ..... ..... 0010001101 . @X_TSX
+STXVRHX 011111 ..... ..... ..... 0010101101 . @X_TSX
+STXVRWX 011111 ..... ..... ..... 0011001101 . @X_TSX
+STXVRDX 011111 ..... ..... ..... 0011101101 . @X_TSX
## VSX Scalar Multiply-Add Instructions
diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx-impl.c.inc
index a980a79b7880..2ffeab5287e9 100644
--- a/target/ppc/translate/vsx-impl.c.inc
+++ b/target/ppc/translate/vsx-impl.c.inc
@@ -2363,6 +2363,41 @@ TRANS64_FLAGS2(ISA310, PLXV, do_lstxv_PLS_D, false, false)
TRANS64_FLAGS2(ISA310, PSTXVP, do_lstxv_PLS_D, true, true)
TRANS64_FLAGS2(ISA310, PLXVP, do_lstxv_PLS_D, false, true)
+static bool do_lstrm(DisasContext *ctx, arg_X *a, MemOp mop, bool store)
+{
+ TCGv ea;
+ TCGv_i64 xt;
+
+ REQUIRE_VSX(ctx);
+
+ xt = tcg_temp_new_i64();
+
+ gen_set_access_type(ctx, ACCESS_INT);
+ ea = do_ea_calc(ctx, a->ra , cpu_gpr[a->rb]);
+
+ if (store) {
+ get_cpu_vsr(xt, a->rt, false);
+ tcg_gen_qemu_st_i64(xt, ea, ctx->mem_idx, mop);
+ } else {
+ tcg_gen_qemu_ld_i64(xt, ea, ctx->mem_idx, mop);
+ set_cpu_vsr(a->rt, xt, false);
+ set_cpu_vsr(a->rt, tcg_constant_i64(0), true);
+ }
+
+ tcg_temp_free(ea);
+ tcg_temp_free_i64(xt);
+ return true;
+}
+
+TRANS_FLAGS2(ISA310, LXVRBX, do_lstrm, DEF_MEMOP(MO_UB), false)
+TRANS_FLAGS2(ISA310, LXVRHX, do_lstrm, DEF_MEMOP(MO_UW), false)
+TRANS_FLAGS2(ISA310, LXVRWX, do_lstrm, DEF_MEMOP(MO_UL), false)
+TRANS_FLAGS2(ISA310, LXVRDX, do_lstrm, DEF_MEMOP(MO_UQ), false)
+TRANS_FLAGS2(ISA310, STXVRBX, do_lstrm, DEF_MEMOP(MO_UB), true)
+TRANS_FLAGS2(ISA310, STXVRHX, do_lstrm, DEF_MEMOP(MO_UW), true)
+TRANS_FLAGS2(ISA310, STXVRWX, do_lstrm, DEF_MEMOP(MO_UL), true)
+TRANS_FLAGS2(ISA310, STXVRDX, do_lstrm, DEF_MEMOP(MO_UQ), true)
+
static void gen_xxeval_i64(TCGv_i64 t, TCGv_i64 a, TCGv_i64 b, TCGv_i64 c,
int64_t imm)
{
--
2.34.1
^ permalink raw reply related [flat|nested] 89+ messages in thread* [PULL 56/87] ppc/xive2: Introduce a XIVE2 core framework
2022-03-02 11:06 [PULL 00/87] ppc queue Cédric Le Goater
` (54 preceding siblings ...)
2022-03-02 11:07 ` [PULL 55/87] target/ppc: implement lxvr[bhwd]/stxvr[bhwd]x Cédric Le Goater
@ 2022-03-02 11:07 ` Cédric Le Goater
2022-03-02 11:07 ` [PULL 57/87] ppc/xive2: Introduce a presenter matching routine Cédric Le Goater
` (31 subsequent siblings)
87 siblings, 0 replies; 89+ messages in thread
From: Cédric Le Goater @ 2022-03-02 11:07 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Daniel Henrique Barboza, Cédric Le Goater
The XIVE2 interrupt controller of the POWER10 processor as the same
logic as on POWER9 but its SW interface has been largely reworked. The
interrupt controller has a new register interface, different BARs,
extra VSDs. These will be described when we add the device model for
the baremetal machine.
The XIVE internal structures for the EAS, END, NVT have different
layouts which is a problem for the current core XIVE framework. To
avoid adding too much complexity in the XIVE models, a new XIVE2 core
framework is introduced. It duplicates the models which are closely
linked to the XIVE internal structures : Xive2Router and
Xive2ENDSource and reuses the XiveSource, XivePresenter, XiveTCTX
models, as they are more generic.
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
include/hw/ppc/xive2.h | 78 +++++
include/hw/ppc/xive2_regs.h | 198 +++++++++++
hw/intc/xive2.c | 667 ++++++++++++++++++++++++++++++++++++
hw/intc/meson.build | 2 +-
4 files changed, 944 insertions(+), 1 deletion(-)
create mode 100644 include/hw/ppc/xive2.h
create mode 100644 include/hw/ppc/xive2_regs.h
create mode 100644 hw/intc/xive2.c
diff --git a/include/hw/ppc/xive2.h b/include/hw/ppc/xive2.h
new file mode 100644
index 000000000000..69b2117e65bd
--- /dev/null
+++ b/include/hw/ppc/xive2.h
@@ -0,0 +1,78 @@
+/*
+ * QEMU PowerPC XIVE2 interrupt controller model (POWER10)
+ *
+ * Copyright (c) 2019-2022, IBM Corporation.
+ *
+ * This code is licensed under the GPL version 2 or later. See the
+ * COPYING file in the top-level directory.
+ *
+ */
+
+#ifndef PPC_XIVE2_H
+#define PPC_XIVE2_H
+
+#include "hw/ppc/xive2_regs.h"
+
+/*
+ * XIVE2 Router (POWER10)
+ */
+typedef struct Xive2Router {
+ SysBusDevice parent;
+
+ XiveFabric *xfb;
+} Xive2Router;
+
+#define TYPE_XIVE2_ROUTER "xive2-router"
+OBJECT_DECLARE_TYPE(Xive2Router, Xive2RouterClass, XIVE2_ROUTER);
+
+typedef struct Xive2RouterClass {
+ SysBusDeviceClass parent;
+
+ /* XIVE table accessors */
+ int (*get_eas)(Xive2Router *xrtr, uint8_t eas_blk, uint32_t eas_idx,
+ Xive2Eas *eas);
+ int (*get_end)(Xive2Router *xrtr, uint8_t end_blk, uint32_t end_idx,
+ Xive2End *end);
+ int (*write_end)(Xive2Router *xrtr, uint8_t end_blk, uint32_t end_idx,
+ Xive2End *end, uint8_t word_number);
+ int (*get_nvp)(Xive2Router *xrtr, uint8_t nvp_blk, uint32_t nvp_idx,
+ Xive2Nvp *nvp);
+ int (*write_nvp)(Xive2Router *xrtr, uint8_t nvp_blk, uint32_t nvp_idx,
+ Xive2Nvp *nvp, uint8_t word_number);
+ uint8_t (*get_block_id)(Xive2Router *xrtr);
+} Xive2RouterClass;
+
+int xive2_router_get_eas(Xive2Router *xrtr, uint8_t eas_blk, uint32_t eas_idx,
+ Xive2Eas *eas);
+int xive2_router_get_end(Xive2Router *xrtr, uint8_t end_blk, uint32_t end_idx,
+ Xive2End *end);
+int xive2_router_write_end(Xive2Router *xrtr, uint8_t end_blk, uint32_t end_idx,
+ Xive2End *end, uint8_t word_number);
+int xive2_router_get_nvp(Xive2Router *xrtr, uint8_t nvp_blk, uint32_t nvp_idx,
+ Xive2Nvp *nvp);
+int xive2_router_write_nvp(Xive2Router *xrtr, uint8_t nvp_blk, uint32_t nvp_idx,
+ Xive2Nvp *nvp, uint8_t word_number);
+
+void xive2_router_notify(XiveNotifier *xn, uint32_t lisn);
+
+/*
+ * XIVE2 END ESBs (POWER10)
+ */
+
+#define TYPE_XIVE2_END_SOURCE "xive2-end-source"
+OBJECT_DECLARE_SIMPLE_TYPE(Xive2EndSource, XIVE2_END_SOURCE)
+
+typedef struct Xive2EndSource {
+ DeviceState parent;
+
+ uint32_t nr_ends;
+
+ /* ESB memory region */
+ uint32_t esb_shift;
+ MemoryRegion esb_mmio;
+
+ Xive2Router *xrtr;
+} Xive2EndSource;
+
+
+#endif /* PPC_XIVE2_H */
diff --git a/include/hw/ppc/xive2_regs.h b/include/hw/ppc/xive2_regs.h
new file mode 100644
index 000000000000..b6d36204e6b9
--- /dev/null
+++ b/include/hw/ppc/xive2_regs.h
@@ -0,0 +1,198 @@
+/*
+ * QEMU PowerPC XIVE2 internal structure definitions (POWER10)
+ *
+ * Copyright (c) 2019-2022, IBM Corporation.
+ *
+ * This code is licensed under the GPL version 2 or later. See the
+ * COPYING file in the top-level directory.
+ */
+
+#ifndef PPC_XIVE2_REGS_H
+#define PPC_XIVE2_REGS_H
+
+/*
+ * Thread Interrupt Management Area (TIMA)
+ *
+ * In Gen1 mode (P9 compat mode) word 2 is the same. However in Gen2
+ * mode (P10), the CAM line is slightly different as the VP space was
+ * increased.
+ */
+#define TM2_QW0W2_VU PPC_BIT32(0)
+#define TM2_QW0W2_LOGIC_SERV PPC_BITMASK32(4, 31)
+#define TM2_QW1W2_VO PPC_BIT32(0)
+#define TM2_QW1W2_OS_CAM PPC_BITMASK32(4, 31)
+#define TM2_QW2W2_VP PPC_BIT32(0)
+#define TM2_QW2W2_POOL_CAM PPC_BITMASK32(4, 31)
+#define TM2_QW3W2_VT PPC_BIT32(0)
+#define TM2_QW3W2_LP PPC_BIT32(6)
+#define TM2_QW3W2_LE PPC_BIT32(7)
+
+/*
+ * Event Assignment Structure (EAS)
+ */
+
+typedef struct Xive2Eas {
+ uint64_t w;
+#define EAS2_VALID PPC_BIT(0)
+#define EAS2_END_BLOCK PPC_BITMASK(4, 7) /* Destination EQ block# */
+#define EAS2_END_INDEX PPC_BITMASK(8, 31) /* Destination EQ index */
+#define EAS2_MASKED PPC_BIT(32) /* Masked */
+#define EAS2_END_DATA PPC_BITMASK(33, 63) /* written to the EQ */
+} Xive2Eas;
+
+#define xive2_eas_is_valid(eas) (be64_to_cpu((eas)->w) & EAS2_VALID)
+#define xive2_eas_is_masked(eas) (be64_to_cpu((eas)->w) & EAS2_MASKED)
+
+void xive2_eas_pic_print_info(Xive2Eas *eas, uint32_t lisn, Monitor *mon);
+
+/*
+ * Event Notifification Descriptor (END)
+ */
+
+typedef struct Xive2End {
+ uint32_t w0;
+#define END2_W0_VALID PPC_BIT32(0) /* "v" bit */
+#define END2_W0_ENQUEUE PPC_BIT32(5) /* "q" bit */
+#define END2_W0_UCOND_NOTIFY PPC_BIT32(6) /* "n" bit */
+#define END2_W0_SILENT_ESCALATE PPC_BIT32(7) /* "s" bit */
+#define END2_W0_BACKLOG PPC_BIT32(8) /* "b" bit */
+#define END2_W0_PRECL_ESC_CTL PPC_BIT32(9) /* "p" bit */
+#define END2_W0_UNCOND_ESCALATE PPC_BIT32(10) /* "u" bit */
+#define END2_W0_ESCALATE_CTL PPC_BIT32(11) /* "e" bit */
+#define END2_W0_ADAPTIVE_ESC PPC_BIT32(12) /* "a" bit */
+#define END2_W0_ESCALATE_END PPC_BIT32(13) /* "N" bit */
+#define END2_W0_FIRMWARE1 PPC_BIT32(16) /* Owned by FW */
+#define END2_W0_FIRMWARE2 PPC_BIT32(17) /* Owned by FW */
+#define END2_W0_AEC_SIZE PPC_BITMASK32(18, 19)
+#define END2_W0_AEG_SIZE PPC_BITMASK32(20, 23)
+#define END2_W0_EQ_VG_PREDICT PPC_BITMASK32(24, 31) /* Owned by HW */
+ uint32_t w1;
+#define END2_W1_ESn PPC_BITMASK32(0, 1)
+#define END2_W1_ESn_P PPC_BIT32(0)
+#define END2_W1_ESn_Q PPC_BIT32(1)
+#define END2_W1_ESe PPC_BITMASK32(2, 3)
+#define END2_W1_ESe_P PPC_BIT32(2)
+#define END2_W1_ESe_Q PPC_BIT32(3)
+#define END2_W1_GEN_FLIPPED PPC_BIT32(8)
+#define END2_W1_GENERATION PPC_BIT32(9)
+#define END2_W1_PAGE_OFF PPC_BITMASK32(10, 31)
+ uint32_t w2;
+#define END2_W2_RESERVED PPC_BITMASK32(4, 7)
+#define END2_W2_EQ_ADDR_HI PPC_BITMASK32(8, 31)
+ uint32_t w3;
+#define END2_W3_EQ_ADDR_LO PPC_BITMASK32(0, 24)
+#define END2_W3_QSIZE PPC_BITMASK32(28, 31)
+ uint32_t w4;
+#define END2_W4_END_BLOCK PPC_BITMASK32(4, 7)
+#define END2_W4_ESC_END_INDEX PPC_BITMASK32(8, 31)
+#define END2_W4_ESB_BLOCK PPC_BITMASK32(0, 3)
+#define END2_W4_ESC_ESB_INDEX PPC_BITMASK32(4, 31)
+ uint32_t w5;
+#define END2_W5_ESC_END_DATA PPC_BITMASK32(1, 31)
+ uint32_t w6;
+#define END2_W6_FORMAT_BIT PPC_BIT32(0)
+#define END2_W6_IGNORE PPC_BIT32(1)
+#define END2_W6_VP_BLOCK PPC_BITMASK32(4, 7)
+#define END2_W6_VP_OFFSET PPC_BITMASK32(8, 31)
+#define END2_W6_VP_OFFSET_GEN1 PPC_BITMASK32(13, 31)
+ uint32_t w7;
+#define END2_W7_TOPO PPC_BITMASK32(0, 3) /* Owned by HW */
+#define END2_W7_F0_PRIORITY PPC_BITMASK32(8, 15)
+#define END2_W7_F1_LOG_SERVER_ID PPC_BITMASK32(4, 31)
+} Xive2End;
+
+#define xive2_end_is_valid(end) (be32_to_cpu((end)->w0) & END2_W0_VALID)
+#define xive2_end_is_enqueue(end) (be32_to_cpu((end)->w0) & END2_W0_ENQUEUE)
+#define xive2_end_is_notify(end) \
+ (be32_to_cpu((end)->w0) & END2_W0_UCOND_NOTIFY)
+#define xive2_end_is_backlog(end) (be32_to_cpu((end)->w0) & END2_W0_BACKLOG)
+#define xive2_end_is_escalate(end) \
+ (be32_to_cpu((end)->w0) & END2_W0_ESCALATE_CTL)
+#define xive2_end_is_uncond_escalation(end) \
+ (be32_to_cpu((end)->w0) & END2_W0_UNCOND_ESCALATE)
+#define xive2_end_is_silent_escalation(end) \
+ (be32_to_cpu((end)->w0) & END2_W0_SILENT_ESCALATE)
+#define xive2_end_is_escalate_end(end) \
+ (be32_to_cpu((end)->w0) & END2_W0_ESCALATE_END)
+#define xive2_end_is_firmware1(end) \
+ (be32_to_cpu((end)->w0) & END2_W0_FIRMWARE1)
+#define xive2_end_is_firmware2(end) \
+ (be32_to_cpu((end)->w0) & END2_W0_FIRMWARE2)
+
+static inline uint64_t xive2_end_qaddr(Xive2End *end)
+{
+ return ((uint64_t) be32_to_cpu(end->w2) & END2_W2_EQ_ADDR_HI) << 32 |
+ (be32_to_cpu(end->w3) & END2_W3_EQ_ADDR_LO);
+}
+
+void xive2_end_pic_print_info(Xive2End *end, uint32_t end_idx, Monitor *mon);
+void xive2_end_queue_pic_print_info(Xive2End *end, uint32_t width,
+ Monitor *mon);
+void xive2_end_eas_pic_print_info(Xive2End *end, uint32_t end_idx,
+ Monitor *mon);
+
+/*
+ * Notification Virtual Processor (NVP)
+ */
+typedef struct Xive2Nvp {
+ uint32_t w0;
+#define NVP2_W0_VALID PPC_BIT32(0)
+#define NVP2_W0_ESC_END PPC_BIT32(25) /* 'N' bit 0:ESB 1:END */
+ uint32_t w1;
+ uint32_t w2;
+#define NVP2_W2_IPB PPC_BITMASK32(8, 15)
+ uint32_t w3;
+ uint32_t w4;
+#define NVP2_W4_ESC_ESB_BLOCK PPC_BITMASK32(0, 3) /* N:0 */
+#define NVP2_W4_ESC_ESB_INDEX PPC_BITMASK32(4, 31) /* N:0 */
+#define NVP2_W4_ESC_END_BLOCK PPC_BITMASK32(4, 7) /* N:1 */
+#define NVP2_W4_ESC_END_INDEX PPC_BITMASK32(8, 31) /* N:1 */
+ uint32_t w5;
+#define NVP2_W5_PSIZE PPC_BITMASK32(0, 1)
+#define NVP2_W5_VP_END_BLOCK PPC_BITMASK32(4, 7)
+#define NVP2_W5_VP_END_INDEX PPC_BITMASK32(8, 31)
+ uint32_t w6;
+ uint32_t w7;
+} Xive2Nvp;
+
+#define xive2_nvp_is_valid(nvp) (be32_to_cpu((nvp)->w0) & NVP2_W0_VALID)
+
+/*
+ * The VP number space in a block is defined by the END2_W6_VP_OFFSET
+ * field of the XIVE END. When running in Gen1 mode (P9 compat mode),
+ * the VP space is reduced to (1 << 19) VPs per block
+ */
+#define XIVE2_NVP_SHIFT 24
+#define XIVE2_NVP_COUNT (1 << XIVE2_NVP_SHIFT)
+
+static inline uint32_t xive2_nvp_cam_line(uint8_t nvp_blk, uint32_t nvp_idx)
+{
+ return (nvp_blk << XIVE2_NVP_SHIFT) | nvp_idx;
+}
+
+static inline uint32_t xive2_nvp_idx(uint32_t cam_line)
+{
+ return cam_line & ((1 << XIVE2_NVP_SHIFT) - 1);
+}
+
+static inline uint32_t xive2_nvp_blk(uint32_t cam_line)
+{
+ return (cam_line >> XIVE2_NVP_SHIFT) & 0xf;
+}
+
+/*
+ * Notification Virtual Group or Crowd (NVG/NVC)
+ */
+typedef struct Xive2Nvgc {
+ uint32_t w0;
+#define NVGC2_W0_VALID PPC_BIT32(0)
+ uint32_t w1;
+ uint32_t w2;
+ uint32_t w3;
+ uint32_t w4;
+ uint32_t w5;
+ uint32_t w6;
+ uint32_t w7;
+} Xive2Nvgc;
+
+#endif /* PPC_XIVE2_REGS_H */
diff --git a/hw/intc/xive2.c b/hw/intc/xive2.c
new file mode 100644
index 000000000000..0248d43e37e4
--- /dev/null
+++ b/hw/intc/xive2.c
@@ -0,0 +1,667 @@
+/*
+ * QEMU PowerPC XIVE2 interrupt controller model (POWER10)
+ *
+ * Copyright (c) 2019-2022, IBM Corporation..
+ *
+ * This code is licensed under the GPL version 2 or later. See the
+ * COPYING file in the top-level directory.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/log.h"
+#include "qemu/module.h"
+#include "qapi/error.h"
+#include "target/ppc/cpu.h"
+#include "sysemu/cpus.h"
+#include "sysemu/dma.h"
+#include "hw/qdev-properties.h"
+#include "monitor/monitor.h"
+#include "hw/ppc/xive.h"
+#include "hw/ppc/xive2.h"
+#include "hw/ppc/xive2_regs.h"
+
+void xive2_eas_pic_print_info(Xive2Eas *eas, uint32_t lisn, Monitor *mon)
+{
+ if (!xive2_eas_is_valid(eas)) {
+ return;
+ }
+
+ monitor_printf(mon, " %08x %s end:%02x/%04x data:%08x\n",
+ lisn, xive2_eas_is_masked(eas) ? "M" : " ",
+ (uint8_t) xive_get_field64(EAS2_END_BLOCK, eas->w),
+ (uint32_t) xive_get_field64(EAS2_END_INDEX, eas->w),
+ (uint32_t) xive_get_field64(EAS2_END_DATA, eas->w));
+}
+
+void xive2_end_queue_pic_print_info(Xive2End *end, uint32_t width,
+ Monitor *mon)
+{
+ uint64_t qaddr_base = xive2_end_qaddr(end);
+ uint32_t qsize = xive_get_field32(END2_W3_QSIZE, end->w3);
+ uint32_t qindex = xive_get_field32(END2_W1_PAGE_OFF, end->w1);
+ uint32_t qentries = 1 << (qsize + 10);
+ int i;
+
+ /*
+ * print out the [ (qindex - (width - 1)) .. (qindex + 1)] window
+ */
+ monitor_printf(mon, " [ ");
+ qindex = (qindex - (width - 1)) & (qentries - 1);
+ for (i = 0; i < width; i++) {
+ uint64_t qaddr = qaddr_base + (qindex << 2);
+ uint32_t qdata = -1;
+
+ if (dma_memory_read(&address_space_memory, qaddr, &qdata,
+ sizeof(qdata), MEMTXATTRS_UNSPECIFIED)) {
+ qemu_log_mask(LOG_GUEST_ERROR, "XIVE: failed to read EQ @0x%"
+ HWADDR_PRIx "\n", qaddr);
+ return;
+ }
+ monitor_printf(mon, "%s%08x ", i == width - 1 ? "^" : "",
+ be32_to_cpu(qdata));
+ qindex = (qindex + 1) & (qentries - 1);
+ }
+ monitor_printf(mon, "]");
+}
+
+void xive2_end_pic_print_info(Xive2End *end, uint32_t end_idx, Monitor *mon)
+{
+ uint64_t qaddr_base = xive2_end_qaddr(end);
+ uint32_t qindex = xive_get_field32(END2_W1_PAGE_OFF, end->w1);
+ uint32_t qgen = xive_get_field32(END2_W1_GENERATION, end->w1);
+ uint32_t qsize = xive_get_field32(END2_W3_QSIZE, end->w3);
+ uint32_t qentries = 1 << (qsize + 10);
+
+ uint32_t nvp_blk = xive_get_field32(END2_W6_VP_BLOCK, end->w6);
+ uint32_t nvp_idx = xive_get_field32(END2_W6_VP_OFFSET, end->w6);
+ uint8_t priority = xive_get_field32(END2_W7_F0_PRIORITY, end->w7);
+ uint8_t pq;
+
+ if (!xive2_end_is_valid(end)) {
+ return;
+ }
+
+ pq = xive_get_field32(END2_W1_ESn, end->w1);
+
+ monitor_printf(mon,
+ " %08x %c%c %c%c%c%c%c%c%c%c%c%c prio:%d nvp:%02x/%04x",
+ end_idx,
+ pq & XIVE_ESB_VAL_P ? 'P' : '-',
+ pq & XIVE_ESB_VAL_Q ? 'Q' : '-',
+ xive2_end_is_valid(end) ? 'v' : '-',
+ xive2_end_is_enqueue(end) ? 'q' : '-',
+ xive2_end_is_notify(end) ? 'n' : '-',
+ xive2_end_is_backlog(end) ? 'b' : '-',
+ xive2_end_is_escalate(end) ? 'e' : '-',
+ xive2_end_is_escalate_end(end) ? 'N' : '-',
+ xive2_end_is_uncond_escalation(end) ? 'u' : '-',
+ xive2_end_is_silent_escalation(end) ? 's' : '-',
+ xive2_end_is_firmware1(end) ? 'f' : '-',
+ xive2_end_is_firmware2(end) ? 'F' : '-',
+ priority, nvp_blk, nvp_idx);
+
+ if (qaddr_base) {
+ monitor_printf(mon, " eq:@%08"PRIx64"% 6d/%5d ^%d",
+ qaddr_base, qindex, qentries, qgen);
+ xive2_end_queue_pic_print_info(end, 6, mon);
+ }
+ monitor_printf(mon, "\n");
+}
+
+void xive2_end_eas_pic_print_info(Xive2End *end, uint32_t end_idx,
+ Monitor *mon)
+{
+ Xive2Eas *eas = (Xive2Eas *) &end->w4;
+ uint8_t pq;
+
+ if (!xive2_end_is_escalate(end)) {
+ return;
+ }
+
+ pq = xive_get_field32(END2_W1_ESe, end->w1);
+
+ monitor_printf(mon, " %08x %c%c %c%c end:%02x/%04x data:%08x\n",
+ end_idx,
+ pq & XIVE_ESB_VAL_P ? 'P' : '-',
+ pq & XIVE_ESB_VAL_Q ? 'Q' : '-',
+ xive2_eas_is_valid(eas) ? 'v' : ' ',
+ xive2_eas_is_masked(eas) ? 'M' : ' ',
+ (uint8_t) xive_get_field64(EAS2_END_BLOCK, eas->w),
+ (uint32_t) xive_get_field64(EAS2_END_INDEX, eas->w),
+ (uint32_t) xive_get_field64(EAS2_END_DATA, eas->w));
+}
+
+static void xive2_end_enqueue(Xive2End *end, uint32_t data)
+{
+ uint64_t qaddr_base = xive2_end_qaddr(end);
+ uint32_t qsize = xive_get_field32(END2_W3_QSIZE, end->w3);
+ uint32_t qindex = xive_get_field32(END2_W1_PAGE_OFF, end->w1);
+ uint32_t qgen = xive_get_field32(END2_W1_GENERATION, end->w1);
+
+ uint64_t qaddr = qaddr_base + (qindex << 2);
+ uint32_t qdata = cpu_to_be32((qgen << 31) | (data & 0x7fffffff));
+ uint32_t qentries = 1 << (qsize + 10);
+
+ if (dma_memory_write(&address_space_memory, qaddr, &qdata, sizeof(qdata),
+ MEMTXATTRS_UNSPECIFIED)) {
+ qemu_log_mask(LOG_GUEST_ERROR, "XIVE: failed to write END data @0x%"
+ HWADDR_PRIx "\n", qaddr);
+ return;
+ }
+
+ qindex = (qindex + 1) & (qentries - 1);
+ if (qindex == 0) {
+ qgen ^= 1;
+ end->w1 = xive_set_field32(END2_W1_GENERATION, end->w1, qgen);
+
+ /* TODO(PowerNV): reset GF bit on a cache watch operation */
+ end->w1 = xive_set_field32(END2_W1_GEN_FLIPPED, end->w1, qgen);
+ }
+ end->w1 = xive_set_field32(END2_W1_PAGE_OFF, end->w1, qindex);
+}
+/*
+ * XIVE Router (aka. Virtualization Controller or IVRE)
+ */
+
+int xive2_router_get_eas(Xive2Router *xrtr, uint8_t eas_blk, uint32_t eas_idx,
+ Xive2Eas *eas)
+{
+ Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr);
+
+ return xrc->get_eas(xrtr, eas_blk, eas_idx, eas);
+}
+
+int xive2_router_get_end(Xive2Router *xrtr, uint8_t end_blk, uint32_t end_idx,
+ Xive2End *end)
+{
+ Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr);
+
+ return xrc->get_end(xrtr, end_blk, end_idx, end);
+}
+
+int xive2_router_write_end(Xive2Router *xrtr, uint8_t end_blk, uint32_t end_idx,
+ Xive2End *end, uint8_t word_number)
+{
+ Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr);
+
+ return xrc->write_end(xrtr, end_blk, end_idx, end, word_number);
+}
+
+int xive2_router_get_nvp(Xive2Router *xrtr, uint8_t nvp_blk, uint32_t nvp_idx,
+ Xive2Nvp *nvp)
+{
+ Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr);
+
+ return xrc->get_nvp(xrtr, nvp_blk, nvp_idx, nvp);
+}
+
+int xive2_router_write_nvp(Xive2Router *xrtr, uint8_t nvp_blk, uint32_t nvp_idx,
+ Xive2Nvp *nvp, uint8_t word_number)
+{
+ Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr);
+
+ return xrc->write_nvp(xrtr, nvp_blk, nvp_idx, nvp, word_number);
+}
+
+static int xive2_router_get_block_id(Xive2Router *xrtr)
+{
+ Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr);
+
+ return xrc->get_block_id(xrtr);
+}
+
+static void xive2_router_realize(DeviceState *dev, Error **errp)
+{
+ Xive2Router *xrtr = XIVE2_ROUTER(dev);
+
+ assert(xrtr->xfb);
+}
+
+/*
+ * Notification using the END ESe/ESn bit (Event State Buffer for
+ * escalation and notification). Profide futher coalescing in the
+ * Router.
+ */
+static bool xive2_router_end_es_notify(Xive2Router *xrtr, uint8_t end_blk,
+ uint32_t end_idx, Xive2End *end,
+ uint32_t end_esmask)
+{
+ uint8_t pq = xive_get_field32(end_esmask, end->w1);
+ bool notify = xive_esb_trigger(&pq);
+
+ if (pq != xive_get_field32(end_esmask, end->w1)) {
+ end->w1 = xive_set_field32(end_esmask, end->w1, pq);
+ xive2_router_write_end(xrtr, end_blk, end_idx, end, 1);
+ }
+
+ /* ESe/n[Q]=1 : end of notification */
+ return notify;
+}
+
+/*
+ * An END trigger can come from an event trigger (IPI or HW) or from
+ * another chip. We don't model the PowerBus but the END trigger
+ * message has the same parameters than in the function below.
+ */
+static void xive2_router_end_notify(Xive2Router *xrtr, uint8_t end_blk,
+ uint32_t end_idx, uint32_t end_data)
+{
+ Xive2End end;
+ uint8_t priority;
+ uint8_t format;
+ bool found;
+ Xive2Nvp nvp;
+ uint8_t nvp_blk;
+ uint32_t nvp_idx;
+
+ /* END cache lookup */
+ if (xive2_router_get_end(xrtr, end_blk, end_idx, &end)) {
+ qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No END %x/%x\n", end_blk,
+ end_idx);
+ return;
+ }
+
+ if (!xive2_end_is_valid(&end)) {
+ qemu_log_mask(LOG_GUEST_ERROR, "XIVE: END %x/%x is invalid\n",
+ end_blk, end_idx);
+ return;
+ }
+
+ if (xive2_end_is_enqueue(&end)) {
+ xive2_end_enqueue(&end, end_data);
+ /* Enqueuing event data modifies the EQ toggle and index */
+ xive2_router_write_end(xrtr, end_blk, end_idx, &end, 1);
+ }
+
+ /*
+ * When the END is silent, we skip the notification part.
+ */
+ if (xive2_end_is_silent_escalation(&end)) {
+ goto do_escalation;
+ }
+
+ /*
+ * The W7 format depends on the F bit in W6. It defines the type
+ * of the notification :
+ *
+ * F=0 : single or multiple NVP notification
+ * F=1 : User level Event-Based Branch (EBB) notification, no
+ * priority
+ */
+ format = xive_get_field32(END2_W6_FORMAT_BIT, end.w6);
+ priority = xive_get_field32(END2_W7_F0_PRIORITY, end.w7);
+
+ /* The END is masked */
+ if (format == 0 && priority == 0xff) {
+ return;
+ }
+
+ /*
+ * Check the END ESn (Event State Buffer for notification) for
+ * even futher coalescing in the Router
+ */
+ if (!xive2_end_is_notify(&end)) {
+ /* ESn[Q]=1 : end of notification */
+ if (!xive2_router_end_es_notify(xrtr, end_blk, end_idx,
+ &end, END2_W1_ESn)) {
+ return;
+ }
+ }
+
+ /*
+ * Follows IVPE notification
+ */
+ nvp_blk = xive_get_field32(END2_W6_VP_BLOCK, end.w6);
+ nvp_idx = xive_get_field32(END2_W6_VP_OFFSET, end.w6);
+
+ /* NVP cache lookup */
+ if (xive2_router_get_nvp(xrtr, nvp_blk, nvp_idx, &nvp)) {
+ qemu_log_mask(LOG_GUEST_ERROR, "XIVE: no NVP %x/%x\n",
+ nvp_blk, nvp_idx);
+ return;
+ }
+
+ if (!xive2_nvp_is_valid(&nvp)) {
+ qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVP %x/%x is invalid\n",
+ nvp_blk, nvp_idx);
+ return;
+ }
+
+ found = xive_presenter_notify(xrtr->xfb, format, nvp_blk, nvp_idx,
+ xive_get_field32(END2_W6_IGNORE, end.w7),
+ priority,
+ xive_get_field32(END2_W7_F1_LOG_SERVER_ID, end.w7));
+
+ /* TODO: Auto EOI. */
+
+ if (found) {
+ return;
+ }
+
+ /*
+ * If no matching NVP is dispatched on a HW thread :
+ * - specific VP: update the NVP structure if backlog is activated
+ * - logical server : forward request to IVPE (not supported)
+ */
+ if (xive2_end_is_backlog(&end)) {
+ uint8_t ipb;
+
+ if (format == 1) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "XIVE: END %x/%x invalid config: F1 & backlog\n",
+ end_blk, end_idx);
+ return;
+ }
+
+ /*
+ * Record the IPB in the associated NVP structure for later
+ * use. The presenter will resend the interrupt when the vCPU
+ * is dispatched again on a HW thread.
+ */
+ ipb = xive_get_field32(NVP2_W2_IPB, nvp.w2) |
+ xive_priority_to_ipb(priority);
+ nvp.w2 = xive_set_field32(NVP2_W2_IPB, nvp.w2, ipb);
+ xive2_router_write_nvp(xrtr, nvp_blk, nvp_idx, &nvp, 2);
+
+ /*
+ * On HW, follows a "Broadcast Backlog" to IVPEs
+ */
+ }
+
+do_escalation:
+ /*
+ * If activated, escalate notification using the ESe PQ bits and
+ * the EAS in w4-5
+ */
+ if (!xive2_end_is_escalate(&end)) {
+ return;
+ }
+
+ /*
+ * Check the END ESe (Event State Buffer for escalation) for even
+ * futher coalescing in the Router
+ */
+ if (!xive2_end_is_uncond_escalation(&end)) {
+ /* ESe[Q]=1 : end of escalation notification */
+ if (!xive2_router_end_es_notify(xrtr, end_blk, end_idx,
+ &end, END2_W1_ESe)) {
+ return;
+ }
+ }
+
+ /*
+ * The END trigger becomes an Escalation trigger
+ */
+ xive2_router_end_notify(xrtr,
+ xive_get_field32(END2_W4_END_BLOCK, end.w4),
+ xive_get_field32(END2_W4_ESC_END_INDEX, end.w4),
+ xive_get_field32(END2_W5_ESC_END_DATA, end.w5));
+}
+
+void xive2_router_notify(XiveNotifier *xn, uint32_t lisn)
+{
+ Xive2Router *xrtr = XIVE2_ROUTER(xn);
+ uint8_t eas_blk = XIVE_EAS_BLOCK(lisn);
+ uint32_t eas_idx = XIVE_EAS_INDEX(lisn);
+ Xive2Eas eas;
+
+ /* EAS cache lookup */
+ if (xive2_router_get_eas(xrtr, eas_blk, eas_idx, &eas)) {
+ qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN %x\n", lisn);
+ return;
+ }
+
+ if (!xive2_eas_is_valid(&eas)) {
+ qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN %x\n", lisn);
+ return;
+ }
+
+ if (xive2_eas_is_masked(&eas)) {
+ /* Notification completed */
+ return;
+ }
+
+ /*
+ * The event trigger becomes an END trigger
+ */
+ xive2_router_end_notify(xrtr,
+ xive_get_field64(EAS2_END_BLOCK, eas.w),
+ xive_get_field64(EAS2_END_INDEX, eas.w),
+ xive_get_field64(EAS2_END_DATA, eas.w));
+}
+
+static Property xive2_router_properties[] = {
+ DEFINE_PROP_LINK("xive-fabric", Xive2Router, xfb,
+ TYPE_XIVE_FABRIC, XiveFabric *),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void xive2_router_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ XiveNotifierClass *xnc = XIVE_NOTIFIER_CLASS(klass);
+
+ dc->desc = "XIVE2 Router Engine";
+ device_class_set_props(dc, xive2_router_properties);
+ /* Parent is SysBusDeviceClass. No need to call its realize hook */
+ dc->realize = xive2_router_realize;
+ xnc->notify = xive2_router_notify;
+}
+
+static const TypeInfo xive2_router_info = {
+ .name = TYPE_XIVE2_ROUTER,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .abstract = true,
+ .instance_size = sizeof(Xive2Router),
+ .class_size = sizeof(Xive2RouterClass),
+ .class_init = xive2_router_class_init,
+ .interfaces = (InterfaceInfo[]) {
+ { TYPE_XIVE_NOTIFIER },
+ { TYPE_XIVE_PRESENTER },
+ { }
+ }
+};
+
+static inline bool addr_is_even(hwaddr addr, uint32_t shift)
+{
+ return !((addr >> shift) & 1);
+}
+
+static uint64_t xive2_end_source_read(void *opaque, hwaddr addr, unsigned size)
+{
+ Xive2EndSource *xsrc = XIVE2_END_SOURCE(opaque);
+ uint32_t offset = addr & 0xFFF;
+ uint8_t end_blk;
+ uint32_t end_idx;
+ Xive2End end;
+ uint32_t end_esmask;
+ uint8_t pq;
+ uint64_t ret;
+
+ /*
+ * The block id should be deduced from the load address on the END
+ * ESB MMIO but our model only supports a single block per XIVE chip.
+ */
+ end_blk = xive2_router_get_block_id(xsrc->xrtr);
+ end_idx = addr >> (xsrc->esb_shift + 1);
+
+ if (xive2_router_get_end(xsrc->xrtr, end_blk, end_idx, &end)) {
+ qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No END %x/%x\n", end_blk,
+ end_idx);
+ return -1;
+ }
+
+ if (!xive2_end_is_valid(&end)) {
+ qemu_log_mask(LOG_GUEST_ERROR, "XIVE: END %x/%x is invalid\n",
+ end_blk, end_idx);
+ return -1;
+ }
+
+ end_esmask = addr_is_even(addr, xsrc->esb_shift) ? END2_W1_ESn :
+ END2_W1_ESe;
+ pq = xive_get_field32(end_esmask, end.w1);
+
+ switch (offset) {
+ case XIVE_ESB_LOAD_EOI ... XIVE_ESB_LOAD_EOI + 0x7FF:
+ ret = xive_esb_eoi(&pq);
+
+ /* Forward the source event notification for routing ?? */
+ break;
+
+ case XIVE_ESB_GET ... XIVE_ESB_GET + 0x3FF:
+ ret = pq;
+ break;
+
+ case XIVE_ESB_SET_PQ_00 ... XIVE_ESB_SET_PQ_00 + 0x0FF:
+ case XIVE_ESB_SET_PQ_01 ... XIVE_ESB_SET_PQ_01 + 0x0FF:
+ case XIVE_ESB_SET_PQ_10 ... XIVE_ESB_SET_PQ_10 + 0x0FF:
+ case XIVE_ESB_SET_PQ_11 ... XIVE_ESB_SET_PQ_11 + 0x0FF:
+ ret = xive_esb_set(&pq, (offset >> 8) & 0x3);
+ break;
+ default:
+ qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid END ESB load addr %d\n",
+ offset);
+ return -1;
+ }
+
+ if (pq != xive_get_field32(end_esmask, end.w1)) {
+ end.w1 = xive_set_field32(end_esmask, end.w1, pq);
+ xive2_router_write_end(xsrc->xrtr, end_blk, end_idx, &end, 1);
+ }
+
+ return ret;
+}
+
+static void xive2_end_source_write(void *opaque, hwaddr addr,
+ uint64_t value, unsigned size)
+{
+ Xive2EndSource *xsrc = XIVE2_END_SOURCE(opaque);
+ uint32_t offset = addr & 0xFFF;
+ uint8_t end_blk;
+ uint32_t end_idx;
+ Xive2End end;
+ uint32_t end_esmask;
+ uint8_t pq;
+ bool notify = false;
+
+ /*
+ * The block id should be deduced from the load address on the END
+ * ESB MMIO but our model only supports a single block per XIVE chip.
+ */
+ end_blk = xive2_router_get_block_id(xsrc->xrtr);
+ end_idx = addr >> (xsrc->esb_shift + 1);
+
+ if (xive2_router_get_end(xsrc->xrtr, end_blk, end_idx, &end)) {
+ qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No END %x/%x\n", end_blk,
+ end_idx);
+ return;
+ }
+
+ if (!xive2_end_is_valid(&end)) {
+ qemu_log_mask(LOG_GUEST_ERROR, "XIVE: END %x/%x is invalid\n",
+ end_blk, end_idx);
+ return;
+ }
+
+ end_esmask = addr_is_even(addr, xsrc->esb_shift) ? END2_W1_ESn :
+ END2_W1_ESe;
+ pq = xive_get_field32(end_esmask, end.w1);
+
+ switch (offset) {
+ case 0 ... 0x3FF:
+ notify = xive_esb_trigger(&pq);
+ break;
+
+ case XIVE_ESB_STORE_EOI ... XIVE_ESB_STORE_EOI + 0x3FF:
+ /* TODO: can we check StoreEOI availability from the router ? */
+ notify = xive_esb_eoi(&pq);
+ break;
+
+ default:
+ qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid END ESB write addr %d\n",
+ offset);
+ return;
+ }
+
+ if (pq != xive_get_field32(end_esmask, end.w1)) {
+ end.w1 = xive_set_field32(end_esmask, end.w1, pq);
+ xive2_router_write_end(xsrc->xrtr, end_blk, end_idx, &end, 1);
+ }
+
+ /* TODO: Forward the source event notification for routing */
+ if (notify) {
+ ;
+ }
+}
+
+static const MemoryRegionOps xive2_end_source_ops = {
+ .read = xive2_end_source_read,
+ .write = xive2_end_source_write,
+ .endianness = DEVICE_BIG_ENDIAN,
+ .valid = {
+ .min_access_size = 8,
+ .max_access_size = 8,
+ },
+ .impl = {
+ .min_access_size = 8,
+ .max_access_size = 8,
+ },
+};
+
+static void xive2_end_source_realize(DeviceState *dev, Error **errp)
+{
+ Xive2EndSource *xsrc = XIVE2_END_SOURCE(dev);
+
+ assert(xsrc->xrtr);
+
+ if (!xsrc->nr_ends) {
+ error_setg(errp, "Number of interrupt needs to be greater than 0");
+ return;
+ }
+
+ if (xsrc->esb_shift != XIVE_ESB_4K &&
+ xsrc->esb_shift != XIVE_ESB_64K) {
+ error_setg(errp, "Invalid ESB shift setting");
+ return;
+ }
+
+ /*
+ * Each END is assigned an even/odd pair of MMIO pages, the even page
+ * manages the ESn field while the odd page manages the ESe field.
+ */
+ memory_region_init_io(&xsrc->esb_mmio, OBJECT(xsrc),
+ &xive2_end_source_ops, xsrc, "xive.end",
+ (1ull << (xsrc->esb_shift + 1)) * xsrc->nr_ends);
+}
+
+static Property xive2_end_source_properties[] = {
+ DEFINE_PROP_UINT32("nr-ends", Xive2EndSource, nr_ends, 0),
+ DEFINE_PROP_UINT32("shift", Xive2EndSource, esb_shift, XIVE_ESB_64K),
+ DEFINE_PROP_LINK("xive", Xive2EndSource, xrtr, TYPE_XIVE2_ROUTER,
+ Xive2Router *),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void xive2_end_source_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->desc = "XIVE END Source";
+ device_class_set_props(dc, xive2_end_source_properties);
+ dc->realize = xive2_end_source_realize;
+}
+
+static const TypeInfo xive2_end_source_info = {
+ .name = TYPE_XIVE2_END_SOURCE,
+ .parent = TYPE_DEVICE,
+ .instance_size = sizeof(Xive2EndSource),
+ .class_init = xive2_end_source_class_init,
+};
+
+static void xive2_register_types(void)
+{
+ type_register_static(&xive2_router_info);
+ type_register_static(&xive2_end_source_info);
+}
+
+type_init(xive2_register_types)
diff --git a/hw/intc/meson.build b/hw/intc/meson.build
index 746602440289..128cebe0a32b 100644
--- a/hw/intc/meson.build
+++ b/hw/intc/meson.build
@@ -52,7 +52,7 @@ specific_ss.add(when: 'CONFIG_SH_INTC', if_true: files('sh_intc.c'))
specific_ss.add(when: 'CONFIG_RISCV_ACLINT', if_true: files('riscv_aclint.c'))
specific_ss.add(when: 'CONFIG_RISCV_APLIC', if_true: files('riscv_aplic.c'))
specific_ss.add(when: 'CONFIG_SIFIVE_PLIC', if_true: files('sifive_plic.c'))
-specific_ss.add(when: 'CONFIG_XICS', if_true: files('xics.c'))
+specific_ss.add(when: 'CONFIG_XICS', if_true: files('xics.c', 'xive2.c'))
specific_ss.add(when: ['CONFIG_KVM', 'CONFIG_XICS'],
if_true: files('xics_kvm.c'))
specific_ss.add(when: 'CONFIG_PSERIES', if_true: files('xics_spapr.c', 'spapr_xive.c'))
--
2.34.1
^ permalink raw reply related [flat|nested] 89+ messages in thread* [PULL 57/87] ppc/xive2: Introduce a presenter matching routine
2022-03-02 11:06 [PULL 00/87] ppc queue Cédric Le Goater
` (55 preceding siblings ...)
2022-03-02 11:07 ` [PULL 56/87] ppc/xive2: Introduce a XIVE2 core framework Cédric Le Goater
@ 2022-03-02 11:07 ` Cédric Le Goater
2022-03-02 11:07 ` [PULL 58/87] ppc/pnv: Add a XIVE2 controller to the POWER10 chip Cédric Le Goater
` (30 subsequent siblings)
87 siblings, 0 replies; 89+ messages in thread
From: Cédric Le Goater @ 2022-03-02 11:07 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Daniel Henrique Barboza, Cédric Le Goater
The VP space is larger in XIVE2 (P10), 24 bits instead of 19bits on
XIVE (P9), and the CAM line can use a 7bits or 8bits thread id.
For now, we only use 7bits thread ids, same as P9, but because of the
change of the size of the VP space, the CAM matching routine is
different between P9 and P10. It is easier to duplicate the whole
routine than to add extra handlers in xive_presenter_tctx_match() used
for P9.
We might come with a better solution later on, after we have added
some more support for the XIVE2 controller.
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
include/hw/ppc/xive2.h | 9 +++++
hw/intc/xive2.c | 82 ++++++++++++++++++++++++++++++++++++++++++
2 files changed, 91 insertions(+)
diff --git a/include/hw/ppc/xive2.h b/include/hw/ppc/xive2.h
index 69b2117e65bd..0897ddbd4874 100644
--- a/include/hw/ppc/xive2.h
+++ b/include/hw/ppc/xive2.h
@@ -55,6 +55,15 @@ int xive2_router_write_nvp(Xive2Router *xrtr, uint8_t nvp_blk, uint32_t nvp_idx,
void xive2_router_notify(XiveNotifier *xn, uint32_t lisn);
+/*
+ * XIVE2 Presenter (POWER10)
+ */
+
+int xive2_presenter_tctx_match(XivePresenter *xptr, XiveTCTX *tctx,
+ uint8_t format,
+ uint8_t nvt_blk, uint32_t nvt_idx,
+ bool cam_ignore, uint32_t logic_serv);
+
/*
* XIVE2 END ESBs (POWER10)
*/
diff --git a/hw/intc/xive2.c b/hw/intc/xive2.c
index 0248d43e37e4..8f278f3bf680 100644
--- a/hw/intc/xive2.c
+++ b/hw/intc/xive2.c
@@ -210,6 +210,88 @@ static int xive2_router_get_block_id(Xive2Router *xrtr)
return xrc->get_block_id(xrtr);
}
+/*
+ * Encode the HW CAM line with 7bit or 8bit thread id. The thread id
+ * width and block id width is configurable at the IC level.
+ *
+ * chipid << 24 | 0000 0000 0000 0000 1 threadid (7Bit)
+ * chipid << 24 | 0000 0000 0000 0001 threadid (8Bit)
+ */
+static uint32_t xive2_tctx_hw_cam_line(XivePresenter *xptr, XiveTCTX *tctx)
+{
+ Xive2Router *xrtr = XIVE2_ROUTER(xptr);
+ CPUPPCState *env = &POWERPC_CPU(tctx->cs)->env;
+ uint32_t pir = env->spr_cb[SPR_PIR].default_value;
+ uint8_t blk = xive2_router_get_block_id(xrtr);
+ uint8_t tid_shift = 7;
+ uint8_t tid_mask = (1 << tid_shift) - 1;
+
+ return xive2_nvp_cam_line(blk, 1 << tid_shift | (pir & tid_mask));
+}
+
+/*
+ * The thread context register words are in big-endian format.
+ */
+int xive2_presenter_tctx_match(XivePresenter *xptr, XiveTCTX *tctx,
+ uint8_t format,
+ uint8_t nvt_blk, uint32_t nvt_idx,
+ bool cam_ignore, uint32_t logic_serv)
+{
+ uint32_t cam = xive2_nvp_cam_line(nvt_blk, nvt_idx);
+ uint32_t qw3w2 = xive_tctx_word2(&tctx->regs[TM_QW3_HV_PHYS]);
+ uint32_t qw2w2 = xive_tctx_word2(&tctx->regs[TM_QW2_HV_POOL]);
+ uint32_t qw1w2 = xive_tctx_word2(&tctx->regs[TM_QW1_OS]);
+ uint32_t qw0w2 = xive_tctx_word2(&tctx->regs[TM_QW0_USER]);
+
+ /*
+ * TODO (PowerNV): ignore mode. The low order bits of the NVT
+ * identifier are ignored in the "CAM" match.
+ */
+
+ if (format == 0) {
+ if (cam_ignore == true) {
+ /*
+ * F=0 & i=1: Logical server notification (bits ignored at
+ * the end of the NVT identifier)
+ */
+ qemu_log_mask(LOG_UNIMP, "XIVE: no support for LS NVT %x/%x\n",
+ nvt_blk, nvt_idx);
+ return -1;
+ }
+
+ /* F=0 & i=0: Specific NVT notification */
+
+ /* PHYS ring */
+ if ((be32_to_cpu(qw3w2) & TM2_QW3W2_VT) &&
+ cam == xive2_tctx_hw_cam_line(xptr, tctx)) {
+ return TM_QW3_HV_PHYS;
+ }
+
+ /* HV POOL ring */
+ if ((be32_to_cpu(qw2w2) & TM2_QW2W2_VP) &&
+ cam == xive_get_field32(TM2_QW2W2_POOL_CAM, qw2w2)) {
+ return TM_QW2_HV_POOL;
+ }
+
+ /* OS ring */
+ if ((be32_to_cpu(qw1w2) & TM2_QW1W2_VO) &&
+ cam == xive_get_field32(TM2_QW1W2_OS_CAM, qw1w2)) {
+ return TM_QW1_OS;
+ }
+ } else {
+ /* F=1 : User level Event-Based Branch (EBB) notification */
+
+ /* USER ring */
+ if ((be32_to_cpu(qw1w2) & TM2_QW1W2_VO) &&
+ (cam == xive_get_field32(TM2_QW1W2_OS_CAM, qw1w2)) &&
+ (be32_to_cpu(qw0w2) & TM2_QW0W2_VU) &&
+ (logic_serv == xive_get_field32(TM2_QW0W2_LOGIC_SERV, qw0w2))) {
+ return TM_QW0_USER;
+ }
+ }
+ return -1;
+}
+
static void xive2_router_realize(DeviceState *dev, Error **errp)
{
Xive2Router *xrtr = XIVE2_ROUTER(dev);
--
2.34.1
^ permalink raw reply related [flat|nested] 89+ messages in thread* [PULL 58/87] ppc/pnv: Add a XIVE2 controller to the POWER10 chip
2022-03-02 11:06 [PULL 00/87] ppc queue Cédric Le Goater
` (56 preceding siblings ...)
2022-03-02 11:07 ` [PULL 57/87] ppc/xive2: Introduce a presenter matching routine Cédric Le Goater
@ 2022-03-02 11:07 ` Cédric Le Goater
2022-03-02 11:07 ` [PULL 59/87] ppc/pnv: Add a OCC model for POWER10 Cédric Le Goater
` (29 subsequent siblings)
87 siblings, 0 replies; 89+ messages in thread
From: Cédric Le Goater @ 2022-03-02 11:07 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Daniel Henrique Barboza, Cédric Le Goater
The XIVE2 interrupt controller of the POWER10 processor follows the
same logic than on POWER9 but the HW interface has been largely
reviewed. It has a new register interface, different BARs, extra
VSDs, new layout for the XIVE2 structures, and a set of new features
which are described below.
This is a model of the POWER10 XIVE2 interrupt controller for the
PowerNV machine. It focuses primarily on the needs of the skiboot
firmware but some initial hypervisor support is implemented for KVM
use (escalation).
Support for new features will be implemented in time and will require
new support from the OS.
* XIVE2 BARS
The interrupt controller BARs have a different layout outlined below.
Each sub-engine has now own its range and the indirect TIMA access was
replaced with a set of pages, one per CPU, under the IC BAR:
- IC BAR (Interrupt Controller)
. 4 pages, one per sub-engine
. 128 indirect TIMA pages
- TM BAR (Thread Interrupt Management Area)
. 4 pages
- ESB BAR (ESB pages for IPIs)
. up to 1TB
- END BAR (ESB pages for ENDs)
. up to 2TB
- NVC BAR (Notification Virtual Crowd)
. up to 128
- NVPG BAR (Notification Virtual Process and Group)
. up to 1TB
- Direct mapped Thread Context Area (reads & writes)
OPAL does not use the grouping and crowd capability.
* Virtual Structure Tables
XIVE2 adds new tables types and also changes the field layout of the END
and NVP Virtualization Structure Descriptors.
- EAS
- END new layout
- NVT was splitted in :
. NVP (Processor), 32B
. NVG (Group), 32B
. NVC (Crowd == P9 block group) 32B
- IC for remote configuration
- SYNC for cache injection
- ERQ for event input queue
The setup is slighly different on XIVE2 because the indexing has changed
for some of the tables, block ID or the chip topology ID can be used.
* XIVE2 features
SCOM and MMIO registers have a new layout and XIVE2 adds a new global
capability and configuration registers.
The lowlevel hardware offers a set of new features among which :
- a configurable number of priorities : 1 - 8
- StoreEOI with load-after-store ordering is activated by default
- Gen2 TIMA layout
- A P9-compat mode, or Gen1, TIMA toggle bit for SW compatibility
- increase to 24bit for VP number
Other features will have some impact on the Hypervisor and guest OS
when activated, but this is not required for initial support of the
controller.
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/intc/pnv_xive2_regs.h | 428 ++++++++
include/hw/ppc/pnv.h | 22 +
include/hw/ppc/pnv_xive.h | 71 ++
include/hw/ppc/pnv_xscom.h | 3 +
hw/intc/pnv_xive2.c | 2028 ++++++++++++++++++++++++++++++++++++
hw/ppc/pnv.c | 85 +-
hw/intc/meson.build | 2 +-
7 files changed, 2635 insertions(+), 4 deletions(-)
create mode 100644 hw/intc/pnv_xive2_regs.h
create mode 100644 hw/intc/pnv_xive2.c
diff --git a/hw/intc/pnv_xive2_regs.h b/hw/intc/pnv_xive2_regs.h
new file mode 100644
index 000000000000..d45d17cedcca
--- /dev/null
+++ b/hw/intc/pnv_xive2_regs.h
@@ -0,0 +1,428 @@
+/*
+ * QEMU PowerPC XIVE2 interrupt controller model (POWER10)
+ *
+ * Copyright (c) 2019-2022, IBM Corporation.
+ *
+ * This code is licensed under the GPL version 2 or later. See the
+ * COPYING file in the top-level directory.
+ */
+
+#ifndef PPC_PNV_XIVE2_REGS_H
+#define PPC_PNV_XIVE2_REGS_H
+
+/*
+ * CQ Common Queue (PowerBus bridge) Registers
+ */
+
+/* XIVE2 Capabilities */
+#define X_CQ_XIVE_CAP 0x02
+#define CQ_XIVE_CAP 0x010
+#define CQ_XIVE_CAP_VERSION PPC_BITMASK(0, 3)
+/* 4:6 reserved */
+#define CQ_XIVE_CAP_USER_INT_PRIO PPC_BITMASK(8, 9)
+#define CQ_XIVE_CAP_USER_INT_PRIO_1 0
+#define CQ_XIVE_CAP_USER_INT_PRIO_1_2 1
+#define CQ_XIVE_CAP_USER_INT_PRIO_1_4 2
+#define CQ_XIVE_CAP_USER_INT_PRIO_1_8 3
+#define CQ_XIVE_CAP_VP_INT_PRIO PPC_BITMASK(10, 11)
+#define CQ_XIVE_CAP_VP_INT_PRIO_1_8 0
+#define CQ_XIVE_CAP_VP_INT_PRIO_2_8 1
+#define CQ_XIVE_CAP_VP_INT_PRIO_4_8 2
+#define CQ_XIVE_CAP_VP_INT_PRIO_8 3
+#define CQ_XIVE_CAP_BLOCK_ID_WIDTH PPC_BITMASK(12, 13)
+
+/* XIVE2 Configuration */
+#define X_CQ_XIVE_CFG 0x03
+#define CQ_XIVE_CFG 0x018
+
+/* 0:7 reserved */
+#define CQ_XIVE_CFG_USER_INT_PRIO PPC_BITMASK(8, 9)
+#define CQ_XIVE_CFG_VP_INT_PRIO PPC_BITMASK(10, 11)
+#define CQ_XIVE_CFG_INT_PRIO_1 0
+#define CQ_XIVE_CFG_INT_PRIO_2 1
+#define CQ_XIVE_CFG_INT_PRIO_4 2
+#define CQ_XIVE_CFG_INT_PRIO_8 3
+#define CQ_XIVE_CFG_BLOCK_ID_WIDTH PPC_BITMASK(12, 13)
+#define CQ_XIVE_CFG_BLOCK_ID_4BITS 0
+#define CQ_XIVE_CFG_BLOCK_ID_5BITS 1
+#define CQ_XIVE_CFG_BLOCK_ID_6BITS 2
+#define CQ_XIVE_CFG_BLOCK_ID_7BITS 3
+#define CQ_XIVE_CFG_HYP_HARD_RANGE PPC_BITMASK(14, 15)
+#define CQ_XIVE_CFG_THREADID_7BITS 0
+#define CQ_XIVE_CFG_THREADID_8BITS 1
+#define CQ_XIVE_CFG_THREADID_9BITS 2
+#define CQ_XIVE_CFG_THREADID_10BITs 3
+#define CQ_XIVE_CFG_HYP_HARD_BLKID_OVERRIDE PPC_BIT(16)
+#define CQ_XIVE_CFG_HYP_HARD_BLOCK_ID PPC_BITMASK(17, 23)
+
+/* Interrupt Controller Base Address Register - 512 pages (32M) */
+#define X_CQ_IC_BAR 0x08
+#define CQ_IC_BAR 0x040
+#define CQ_IC_BAR_VALID PPC_BIT(0)
+#define CQ_IC_BAR_64K PPC_BIT(1)
+/* 2:7 reserved */
+#define CQ_IC_BAR_ADDR PPC_BITMASK(8, 42)
+/* 43:63 reserved */
+
+/* Thread Management Base Address Register - 4 pages */
+#define X_CQ_TM_BAR 0x09
+#define CQ_TM_BAR 0x048
+#define CQ_TM_BAR_VALID PPC_BIT(0)
+#define CQ_TM_BAR_64K PPC_BIT(1)
+#define CQ_TM_BAR_ADDR PPC_BITMASK(8, 49)
+
+/* ESB Base Address Register */
+#define X_CQ_ESB_BAR 0x0A
+#define CQ_ESB_BAR 0x050
+#define CQ_BAR_VALID PPC_BIT(0)
+#define CQ_BAR_64K PPC_BIT(1)
+/* 2:7 reserved */
+#define CQ_BAR_ADDR PPC_BITMASK(8, 39)
+#define CQ_BAR_SET_DIV PPC_BITMASK(56, 58)
+#define CQ_BAR_RANGE PPC_BITMASK(59, 63)
+ /* 0 (16M) - 16 (16T) */
+
+/* END Base Address Register */
+#define X_CQ_END_BAR 0x0B
+#define CQ_END_BAR 0x058
+
+/* NVPG Base Address Register */
+#define X_CQ_NVPG_BAR 0x0C
+#define CQ_NVPG_BAR 0x060
+
+/* NVC Base Address Register */
+#define X_CQ_NVC_BAR 0x0D
+#define CQ_NVC_BAR 0x068
+
+/* Table Address Register */
+#define X_CQ_TAR 0x0E
+#define CQ_TAR 0x070
+#define CQ_TAR_AUTOINC PPC_BIT(0)
+#define CQ_TAR_SELECT PPC_BITMASK(12, 15)
+#define CQ_TAR_ESB 0 /* 0 - 15 */
+#define CQ_TAR_END 2 /* 0 - 15 */
+#define CQ_TAR_NVPG 3 /* 0 - 15 */
+#define CQ_TAR_NVC 5 /* 0 - 15 */
+#define CQ_TAR_ENTRY_SELECT PPC_BITMASK(28, 31)
+
+/* Table Data Register */
+#define X_CQ_TDR 0x0F
+#define CQ_TDR 0x078
+/* for the NVPG, NVC, ESB, END Set Translation Tables */
+#define CQ_TDR_VALID PPC_BIT(0)
+#define CQ_TDR_BLOCK_ID PPC_BITMASK(60, 63)
+
+/*
+ * Processor Cores Enabled for MsgSnd
+ * Identifies which of the 32 possible core chiplets are enabled and
+ * available to receive the MsgSnd command
+ */
+#define X_CQ_MSGSND 0x10
+#define CQ_MSGSND 0x080
+
+/* Interrupt Unit Reset Control */
+#define X_CQ_RST_CTL 0x12
+#define CQ_RST_CTL 0x090
+#define CQ_RST_SYNC_RESET PPC_BIT(0) /* Write Only */
+#define CQ_RST_QUIESCE_PB PPC_BIT(1) /* RW */
+#define CQ_RST_MASTER_IDLE PPC_BIT(2) /* Read Only */
+#define CQ_RST_SAVE_IDLE PPC_BIT(3) /* Read Only */
+#define CQ_RST_PB_BAR_RESET PPC_BIT(4) /* Write Only */
+
+/* PowerBus General Configuration */
+#define X_CQ_CFG_PB_GEN 0x14
+#define CQ_CFG_PB_GEN 0x0A0
+#define CQ_CFG_PB_GEN_PB_INIT PPC_BIT(45)
+
+/*
+ * FIR
+ * (And-Mask)
+ * (Or-Mask)
+ */
+#define X_CQ_FIR 0x30
+#define X_CQ_FIR_AND 0x31
+#define X_CQ_FIR_OR 0x32
+#define CQ_FIR 0x180
+#define CQ_FIR_AND 0x188
+#define CQ_FIR_OR 0x190
+#define CQ_FIR_PB_RCMDX_CI_ERR1 PPC_BIT(19)
+#define CQ_FIR_VC_INFO_ERROR_0_2 PPC_BITMASK(61, 63)
+
+/*
+ * FIR Mask
+ * (And-Mask)
+ * (Or-Mask)
+ */
+#define X_CQ_FIRMASK 0x33
+#define X_CQ_FIRMASK_AND 0x34
+#define X_CQ_FIRMASK_OR 0x35
+#define CQ_FIRMASK 0x198
+#define CQ_FIRMASK_AND 0x1A0
+#define CQ_FIRMASK_OR 0x1A8
+
+/*
+ * VC0
+ */
+
+/* VSD table address */
+#define X_VC_VSD_TABLE_ADDR 0x100
+#define VC_VSD_TABLE_ADDR 0x000
+#define VC_VSD_TABLE_AUTOINC PPC_BIT(0)
+#define VC_VSD_TABLE_SELECT PPC_BITMASK(12, 15)
+#define VC_VSD_TABLE_ADDRESS PPC_BITMASK(28, 31)
+
+/* VSD table data */
+#define X_VC_VSD_TABLE_DATA 0x101
+#define VC_VSD_TABLE_DATA 0x008
+
+/* AIB AT macro indirect kill */
+#define X_VC_AT_MACRO_KILL 0x102
+#define VC_AT_MACRO_KILL 0x010
+#define VC_AT_MACRO_KILL_VALID PPC_BIT(0)
+#define VC_AT_MACRO_KILL_VSD PPC_BITMASK(12, 15)
+#define VC_AT_MACRO_KILL_BLOCK_ID PPC_BITMASK(28, 31)
+#define VC_AT_MACRO_KILL_OFFSET PPC_BITMASK(48, 60)
+
+/* AIB AT macro indirect kill mask (same bit definitions) */
+#define X_VC_AT_MACRO_KILL_MASK 0x103
+#define VC_AT_MACRO_KILL_MASK 0x018
+
+/* Remote IRQs and ERQs configuration [n] (n = 0:6) */
+#define X_VC_QUEUES_CFG_REM0 0x117
+
+#define VC_QUEUES_CFG_REM0 0x0B8
+#define VC_QUEUES_CFG_REM1 0x0C0
+#define VC_QUEUES_CFG_REM2 0x0C8
+#define VC_QUEUES_CFG_REM3 0x0D0
+#define VC_QUEUES_CFG_REM4 0x0D8
+#define VC_QUEUES_CFG_REM5 0x0E0
+#define VC_QUEUES_CFG_REM6 0x0E8
+#define VC_QUEUES_CFG_MEMB_EN PPC_BIT(38)
+#define VC_QUEUES_CFG_MEMB_SZ PPC_BITMASK(42, 47)
+
+/*
+ * VC1
+ */
+
+/* ESBC cache flush control trigger */
+#define X_VC_ESBC_FLUSH_CTRL 0x140
+#define VC_ESBC_FLUSH_CTRL 0x200
+#define VC_ESBC_FLUSH_CTRL_POLL_VALID PPC_BIT(0)
+#define VC_ESBC_FLUSH_CTRL_WANT_CACHE_DISABLE PPC_BIT(2)
+
+/* ESBC cache flush poll trigger */
+#define X_VC_ESBC_FLUSH_POLL 0x141
+#define VC_ESBC_FLUSH_POLL 0x208
+#define VC_ESBC_FLUSH_POLL_BLOCK_ID PPC_BITMASK(0, 3)
+#define VC_ESBC_FLUSH_POLL_OFFSET PPC_BITMASK(4, 31) /* 28-bit */
+#define VC_ESBC_FLUSH_POLL_BLOCK_ID_MASK PPC_BITMASK(32, 35)
+#define VC_ESBC_FLUSH_POLL_OFFSET_MASK PPC_BITMASK(36, 63) /* 28-bit */
+
+/* EASC flush control register */
+#define X_VC_EASC_FLUSH_CTRL 0x160
+#define VC_EASC_FLUSH_CTRL 0x300
+#define VC_EASC_FLUSH_CTRL_POLL_VALID PPC_BIT(0)
+#define VC_EASC_FLUSH_CTRL_WANT_CACHE_DISABLE PPC_BIT(2)
+
+/* EASC flush poll register */
+#define X_VC_EASC_FLUSH_POLL 0x161
+#define VC_EASC_FLUSH_POLL 0x308
+#define VC_EASC_FLUSH_POLL_BLOCK_ID PPC_BITMASK(0, 3)
+#define VC_EASC_FLUSH_POLL_OFFSET PPC_BITMASK(4, 31) /* 28-bit */
+#define VC_EASC_FLUSH_POLL_BLOCK_ID_MASK PPC_BITMASK(32, 35)
+#define VC_EASC_FLUSH_POLL_OFFSET_MASK PPC_BITMASK(36, 63) /* 28-bit */
+
+/*
+ * VC2
+ */
+
+/* ENDC flush control register */
+#define X_VC_ENDC_FLUSH_CTRL 0x180
+#define VC_ENDC_FLUSH_CTRL 0x400
+#define VC_ENDC_FLUSH_CTRL_POLL_VALID PPC_BIT(0)
+#define VC_ENDC_FLUSH_CTRL_WANT_CACHE_DISABLE PPC_BIT(2)
+#define VC_ENDC_FLUSH_CTRL_WANT_INVALIDATE PPC_BIT(3)
+#define VC_ENDC_FLUSH_CTRL_INJECT_INVALIDATE PPC_BIT(7)
+
+/* ENDC flush poll register */
+#define X_VC_ENDC_FLUSH_POLL 0x181
+#define VC_ENDC_FLUSH_POLL 0x408
+#define VC_ENDC_FLUSH_POLL_BLOCK_ID PPC_BITMASK(4, 7)
+#define VC_ENDC_FLUSH_POLL_OFFSET PPC_BITMASK(8, 31) /* 24-bit */
+#define VC_ENDC_FLUSH_POLL_BLOCK_ID_MASK PPC_BITMASK(36, 39)
+#define VC_ENDC_FLUSH_POLL_OFFSET_MASK PPC_BITMASK(40, 63) /* 24-bit */
+
+/* ENDC Sync done */
+#define X_VC_ENDC_SYNC_DONE 0x184
+#define VC_ENDC_SYNC_DONE 0x420
+#define VC_ENDC_SYNC_POLL_DONE PPC_BITMASK(0, 6)
+#define VC_ENDC_SYNC_QUEUE_IPI PPC_BIT(0)
+#define VC_ENDC_SYNC_QUEUE_HWD PPC_BIT(1)
+#define VC_ENDC_SYNC_QUEUE_NXC PPC_BIT(2)
+#define VC_ENDC_SYNC_QUEUE_INT PPC_BIT(3)
+#define VC_ENDC_SYNC_QUEUE_OS PPC_BIT(4)
+#define VC_ENDC_SYNC_QUEUE_POOL PPC_BIT(5)
+#define VC_ENDC_SYNC_QUEUE_HARD PPC_BIT(6)
+#define VC_QUEUE_COUNT 7
+
+/* ENDC cache watch specification 0 */
+#define X_VC_ENDC_WATCH0_SPEC 0x1A0
+#define VC_ENDC_WATCH0_SPEC 0x500
+#define VC_ENDC_WATCH_CONFLICT PPC_BIT(0)
+#define VC_ENDC_WATCH_FULL PPC_BIT(8)
+#define VC_ENDC_WATCH_BLOCK_ID PPC_BITMASK(28, 31)
+#define VC_ENDC_WATCH_INDEX PPC_BITMASK(40, 63)
+
+/* ENDC cache watch data 0 */
+#define X_VC_ENDC_WATCH0_DATA0 0x1A4
+#define X_VC_ENDC_WATCH0_DATA1 0x1A5
+#define X_VC_ENDC_WATCH0_DATA2 0x1A6
+#define X_VC_ENDC_WATCH0_DATA3 0x1A7
+
+#define VC_ENDC_WATCH0_DATA0 0x520
+#define VC_ENDC_WATCH0_DATA1 0x528
+#define VC_ENDC_WATCH0_DATA2 0x530
+#define VC_ENDC_WATCH0_DATA3 0x538
+
+/*
+ * PC LSB1
+ */
+
+/* VSD table address register */
+#define X_PC_VSD_TABLE_ADDR 0x200
+#define PC_VSD_TABLE_ADDR 0x000
+#define PC_VSD_TABLE_AUTOINC PPC_BIT(0)
+#define PC_VSD_TABLE_SELECT PPC_BITMASK(12, 15)
+#define PC_VSD_TABLE_ADDRESS PPC_BITMASK(28, 31)
+
+/* VSD table data register */
+#define X_PC_VSD_TABLE_DATA 0x201
+#define PC_VSD_TABLE_DATA 0x008
+
+/* AT indirect kill register */
+#define X_PC_AT_KILL 0x202
+#define PC_AT_KILL 0x010
+#define PC_AT_KILL_VALID PPC_BIT(0)
+#define PC_AT_KILL_VSD_TYPE PPC_BITMASK(24, 27)
+/* Only NVP, NVG, NVC */
+#define PC_AT_KILL_BLOCK_ID PPC_BITMASK(28, 31)
+#define PC_AT_KILL_OFFSET PPC_BITMASK(48, 60)
+
+/* AT indirect kill mask register */
+#define X_PC_AT_KILL_MASK 0x203
+#define PC_AT_KILL_MASK 0x018
+#define PC_AT_KILL_MASK_VSD_TYPE PPC_BITMASK(24, 27)
+#define PC_AT_KILL_MASK_BLOCK_ID PPC_BITMASK(28, 31)
+#define PC_AT_KILL_MASK_OFFSET PPC_BITMASK(48, 60)
+
+/*
+ * PC LSB2
+ */
+
+/* NxC Cache flush control */
+#define X_PC_NXC_FLUSH_CTRL 0x280
+#define PC_NXC_FLUSH_CTRL 0x400
+#define PC_NXC_FLUSH_CTRL_POLL_VALID PPC_BIT(0)
+#define PC_NXC_FLUSH_CTRL_WANT_CACHE_DISABLE PPC_BIT(2)
+#define PC_NXC_FLUSH_CTRL_WANT_INVALIDATE PPC_BIT(3)
+#define PC_NXC_FLUSH_CTRL_INJECT_INVALIDATE PPC_BIT(7)
+
+/* NxC Cache flush poll */
+#define X_PC_NXC_FLUSH_POLL 0x281
+#define PC_NXC_FLUSH_POLL 0x408
+#define PC_NXC_FLUSH_POLL_NXC_TYPE PPC_BITMASK(2, 3)
+#define PC_NXC_FLUSH_POLL_NXC_TYPE_NVP 0
+#define PC_NXC_FLUSH_POLL_NXC_TYPE_NVG 2
+#define PC_NXC_FLUSH_POLL_NXC_TYPE_NVC 3
+#define PC_NXC_FLUSH_POLL_BLOCK_ID PPC_BITMASK(4, 7)
+#define PC_NXC_FLUSH_POLL_OFFSET PPC_BITMASK(8, 31) /* 24-bit */
+#define PC_NXC_FLUSH_POLL_NXC_TYPE_MASK PPC_BITMASK(34, 35) /* 0: Ign */
+#define PC_NXC_FLUSH_POLL_BLOCK_ID_MASK PPC_BITMASK(36, 39)
+#define PC_NXC_FLUSH_POLL_OFFSET_MASK PPC_BITMASK(40, 63) /* 24-bit */
+
+/* NxC Cache Watch 0 Specification */
+#define X_PC_NXC_WATCH0_SPEC 0x2A0
+#define PC_NXC_WATCH0_SPEC 0x500
+#define PC_NXC_WATCH_CONFLICT PPC_BIT(0)
+#define PC_NXC_WATCH_FULL PPC_BIT(8)
+#define PC_NXC_WATCH_NXC_TYPE PPC_BITMASK(26, 27)
+#define PC_NXC_WATCH_NXC_NVP 0
+#define PC_NXC_WATCH_NXC_NVG 2
+#define PC_NXC_WATCH_NXC_NVC 3
+#define PC_NXC_WATCH_BLOCK_ID PPC_BITMASK(28, 31)
+#define PC_NXC_WATCH_INDEX PPC_BITMASK(40, 63)
+
+/* NxC Cache Watch 0 Data */
+#define X_PC_NXC_WATCH0_DATA0 0x2A4
+#define X_PC_NXC_WATCH0_DATA1 0x2A5
+#define X_PC_NXC_WATCH0_DATA2 0x2A6
+#define X_PC_NXC_WATCH0_DATA3 0x2A7
+
+#define PC_NXC_WATCH0_DATA0 0x520
+#define PC_NXC_WATCH0_DATA1 0x528
+#define PC_NXC_WATCH0_DATA2 0x530
+#define PC_NXC_WATCH0_DATA3 0x538
+
+/*
+ * TCTXT Registers
+ */
+
+/* Physical Thread Enable0 register */
+#define X_TCTXT_EN0 0x300
+#define TCTXT_EN0 0x000
+
+/* Physical Thread Enable0 Set register */
+#define X_TCTXT_EN0_SET 0x302
+#define TCTXT_EN0_SET 0x010
+
+/* Physical Thread Enable0 Reset register */
+#define X_TCTXT_EN0_RESET 0x303
+#define TCTXT_EN0_RESET 0x018
+
+/* Physical Thread Enable1 register */
+#define X_TCTXT_EN1 0x304
+#define TCTXT_EN1 0x020
+
+/* Physical Thread Enable1 Set register */
+#define X_TCTXT_EN1_SET 0x306
+#define TCTXT_EN1_SET 0x030
+
+/* Physical Thread Enable1 Reset register */
+#define X_TCTXT_EN1_RESET 0x307
+#define TCTXT_EN1_RESET 0x038
+
+/*
+ * VSD Tables
+ */
+#define VST_ESB 0
+#define VST_EAS 1 /* No used by PC */
+#define VST_END 2
+#define VST_NVP 3
+#define VST_NVG 4
+#define VST_NVC 5
+#define VST_IC 6 /* No used by PC */
+#define VST_SYNC 7
+#define VST_ERQ 8 /* No used by PC */
+
+/*
+ * Bits in a VSD entry.
+ *
+ * Note: the address is naturally aligned, we don't use a PPC_BITMASK,
+ * but just a mask to apply to the address before OR'ing it in.
+ *
+ * Note: VSD_FIRMWARE is a SW bit ! It hijacks an unused bit in the
+ * VSD and is only meant to be used in indirect mode !
+ */
+#define VSD_MODE PPC_BITMASK(0, 1)
+#define VSD_MODE_SHARED 1
+#define VSD_MODE_EXCLUSIVE 2
+#define VSD_MODE_FORWARD 3
+#define VSD_FIRMWARE PPC_BIT(2) /* Read warning */
+#define VSD_FIRMWARE2 PPC_BIT(3) /* unused */
+#define VSD_RESERVED PPC_BITMASK(4, 7) /* P10 reserved */
+#define VSD_ADDRESS_MASK 0x00fffffffffff000ull
+#define VSD_MIGRATION_REG PPC_BITMASK(52, 55)
+#define VSD_INDIRECT PPC_BIT(56)
+#define VSD_TSIZE PPC_BITMASK(59, 63)
+
+#endif /* PPC_PNV_XIVE2_REGS_H */
diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h
index 0e9e16544f30..6b3457b4495d 100644
--- a/include/hw/ppc/pnv.h
+++ b/include/hw/ppc/pnv.h
@@ -125,10 +125,14 @@ struct Pnv10Chip {
PnvChip parent_obj;
/*< public >*/
+ PnvXive2 xive;
Pnv9Psi psi;
PnvLpcController lpc;
};
+#define PNV10_PIR2FUSEDCORE(pir) (((pir) >> 3) & 0xf)
+#define PNV10_PIR2CHIP(pir) (((pir) >> 8) & 0x7f)
+
struct PnvChipClass {
/*< private >*/
SysBusDeviceClass parent_class;
@@ -329,10 +333,28 @@ void pnv_bmc_set_pnor(IPMIBmc *bmc, PnvPnor *pnor);
#define PNV10_LPCM_SIZE 0x0000000100000000ull
#define PNV10_LPCM_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006030000000000ull)
+#define PNV10_XIVE2_IC_SIZE 0x0000000002000000ull
+#define PNV10_XIVE2_IC_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006030200000000ull)
+
#define PNV10_PSIHB_ESB_SIZE 0x0000000000100000ull
#define PNV10_PSIHB_ESB_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006030202000000ull)
#define PNV10_PSIHB_SIZE 0x0000000000100000ull
#define PNV10_PSIHB_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006030203000000ull)
+#define PNV10_XIVE2_TM_SIZE 0x0000000000040000ull
+#define PNV10_XIVE2_TM_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006030203180000ull)
+
+#define PNV10_XIVE2_NVC_SIZE 0x0000000008000000ull
+#define PNV10_XIVE2_NVC_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006030208000000ull)
+
+#define PNV10_XIVE2_NVPG_SIZE 0x0000010000000000ull
+#define PNV10_XIVE2_NVPG_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006040000000000ull)
+
+#define PNV10_XIVE2_ESB_SIZE 0x0000010000000000ull
+#define PNV10_XIVE2_ESB_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006050000000000ull)
+
+#define PNV10_XIVE2_END_SIZE 0x0000020000000000ull
+#define PNV10_XIVE2_END_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006060000000000ull)
+
#endif /* PPC_PNV_H */
diff --git a/include/hw/ppc/pnv_xive.h b/include/hw/ppc/pnv_xive.h
index 7928e279639a..b5d91505e53c 100644
--- a/include/hw/ppc/pnv_xive.h
+++ b/include/hw/ppc/pnv_xive.h
@@ -12,6 +12,7 @@
#include "hw/ppc/xive.h"
#include "qom/object.h"
+#include "hw/ppc/xive2.h"
struct PnvChip;
@@ -95,4 +96,74 @@ struct PnvXiveClass {
void pnv_xive_pic_print_info(PnvXive *xive, Monitor *mon);
+/*
+ * XIVE2 interrupt controller (POWER10)
+ */
+#define TYPE_PNV_XIVE2 "pnv-xive2"
+OBJECT_DECLARE_TYPE(PnvXive2, PnvXive2Class, PNV_XIVE2);
+
+typedef struct PnvXive2 {
+ Xive2Router parent_obj;
+
+ /* Owning chip */
+ struct PnvChip *chip;
+
+ /* XSCOM addresses giving access to the controller registers */
+ MemoryRegion xscom_regs;
+
+ MemoryRegion ic_mmio;
+ MemoryRegion ic_mmios[8];
+ MemoryRegion esb_mmio;
+ MemoryRegion end_mmio;
+ MemoryRegion nvc_mmio;
+ MemoryRegion nvpg_mmio;
+ MemoryRegion tm_mmio;
+
+ /* Shortcut values for the Main MMIO regions */
+ hwaddr ic_base;
+ uint32_t ic_shift;
+ hwaddr esb_base;
+ uint32_t esb_shift;
+ hwaddr end_base;
+ uint32_t end_shift;
+ hwaddr nvc_base;
+ uint32_t nvc_shift;
+ hwaddr nvpg_base;
+ uint32_t nvpg_shift;
+ hwaddr tm_base;
+ uint32_t tm_shift;
+
+ /* Interrupt controller registers */
+ uint64_t cq_regs[0x40];
+ uint64_t vc_regs[0x100];
+ uint64_t pc_regs[0x100];
+ uint64_t tctxt_regs[0x30];
+
+ /* To change default behavior */
+ uint64_t capabilities;
+ uint64_t config;
+
+ /* Our XIVE source objects for IPIs and ENDs */
+ XiveSource ipi_source;
+ Xive2EndSource end_source;
+
+ /*
+ * Virtual Structure Descriptor tables
+ * These are in a SRAM protected by ECC.
+ */
+ uint64_t vsds[9][XIVE_BLOCK_MAX];
+
+ /* Translation tables */
+ uint64_t tables[8][XIVE_BLOCK_MAX];
+
+} PnvXive2;
+
+typedef struct PnvXive2Class {
+ Xive2RouterClass parent_class;
+
+ DeviceRealize parent_realize;
+} PnvXive2Class;
+
+void pnv_xive2_pic_print_info(PnvXive2 *xive, Monitor *mon);
+
#endif /* PPC_PNV_XIVE_H */
diff --git a/include/hw/ppc/pnv_xscom.h b/include/hw/ppc/pnv_xscom.h
index 2ff9f7a8d6fe..188da874a4b0 100644
--- a/include/hw/ppc/pnv_xscom.h
+++ b/include/hw/ppc/pnv_xscom.h
@@ -131,6 +131,9 @@ struct PnvXScomInterfaceClass {
#define PNV10_XSCOM_PSIHB_BASE 0x3011D00
#define PNV10_XSCOM_PSIHB_SIZE 0x100
+#define PNV10_XSCOM_XIVE2_BASE 0x2010800
+#define PNV10_XSCOM_XIVE2_SIZE 0x400
+
void pnv_xscom_realize(PnvChip *chip, uint64_t size, Error **errp);
int pnv_dt_xscom(PnvChip *chip, void *fdt, int root_offset,
uint64_t xscom_base, uint64_t xscom_size,
diff --git a/hw/intc/pnv_xive2.c b/hw/intc/pnv_xive2.c
new file mode 100644
index 000000000000..35a7f7ae4dd8
--- /dev/null
+++ b/hw/intc/pnv_xive2.c
@@ -0,0 +1,2028 @@
+/*
+ * QEMU PowerPC XIVE2 interrupt controller model (POWER10)
+ *
+ * Copyright (c) 2019-2022, IBM Corporation.
+ *
+ * This code is licensed under the GPL version 2 or later. See the
+ * COPYING file in the top-level directory.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/log.h"
+#include "qapi/error.h"
+#include "target/ppc/cpu.h"
+#include "sysemu/cpus.h"
+#include "sysemu/dma.h"
+#include "monitor/monitor.h"
+#include "hw/ppc/fdt.h"
+#include "hw/ppc/pnv.h"
+#include "hw/ppc/pnv_core.h"
+#include "hw/ppc/pnv_xscom.h"
+#include "hw/ppc/xive2.h"
+#include "hw/ppc/pnv_xive.h"
+#include "hw/ppc/xive_regs.h"
+#include "hw/ppc/xive2_regs.h"
+#include "hw/ppc/ppc.h"
+#include "hw/qdev-properties.h"
+#include "sysemu/reset.h"
+
+#include <libfdt.h>
+
+#include "pnv_xive2_regs.h"
+
+#undef XIVE2_DEBUG
+
+/*
+ * Virtual structures table (VST)
+ */
+#define SBE_PER_BYTE 4
+
+typedef struct XiveVstInfo {
+ const char *name;
+ uint32_t size;
+ uint32_t max_blocks;
+} XiveVstInfo;
+
+static const XiveVstInfo vst_infos[] = {
+
+ [VST_EAS] = { "EAT", sizeof(Xive2Eas), 16 },
+ [VST_ESB] = { "ESB", 1, 16 },
+ [VST_END] = { "ENDT", sizeof(Xive2End), 16 },
+
+ [VST_NVP] = { "NVPT", sizeof(Xive2Nvp), 16 },
+ [VST_NVG] = { "NVGT", sizeof(Xive2Nvgc), 16 },
+ [VST_NVC] = { "NVCT", sizeof(Xive2Nvgc), 16 },
+
+ [VST_IC] = { "IC", 1 /* ? */ , 16 }, /* Topology # */
+ [VST_SYNC] = { "SYNC", 1 /* ? */ , 16 }, /* Topology # */
+
+ /*
+ * This table contains the backing store pages for the interrupt
+ * fifos of the VC sub-engine in case of overflow.
+ *
+ * 0 - IPI,
+ * 1 - HWD,
+ * 2 - NxC,
+ * 3 - INT,
+ * 4 - OS-Queue,
+ * 5 - Pool-Queue,
+ * 6 - Hard-Queue
+ */
+ [VST_ERQ] = { "ERQ", 1, VC_QUEUE_COUNT },
+};
+
+#define xive2_error(xive, fmt, ...) \
+ qemu_log_mask(LOG_GUEST_ERROR, "XIVE[%x] - " fmt "\n", \
+ (xive)->chip->chip_id, ## __VA_ARGS__);
+
+/*
+ * QEMU version of the GETFIELD/SETFIELD macros
+ *
+ * TODO: It might be better to use the existing extract64() and
+ * deposit64() but this means that all the register definitions will
+ * change and become incompatible with the ones found in skiboot.
+ *
+ * Keep it as it is for now until we find a common ground.
+ */
+static inline uint64_t GETFIELD(uint64_t mask, uint64_t word)
+{
+ return (word & mask) >> ctz64(mask);
+}
+
+static inline uint64_t SETFIELD(uint64_t mask, uint64_t word,
+ uint64_t value)
+{
+ return (word & ~mask) | ((value << ctz64(mask)) & mask);
+}
+
+/*
+ * TODO: Document block id override
+ */
+static uint32_t pnv_xive2_block_id(PnvXive2 *xive)
+{
+ uint8_t blk = xive->chip->chip_id;
+ uint64_t cfg_val = xive->cq_regs[CQ_XIVE_CFG >> 3];
+
+ if (cfg_val & CQ_XIVE_CFG_HYP_HARD_BLKID_OVERRIDE) {
+ blk = GETFIELD(CQ_XIVE_CFG_HYP_HARD_BLOCK_ID, cfg_val);
+ }
+
+ return blk;
+}
+
+/*
+ * Remote access to controllers. HW uses MMIOs. For now, a simple scan
+ * of the chips is good enough.
+ *
+ * TODO: Block scope support
+ */
+static PnvXive2 *pnv_xive2_get_remote(uint8_t blk)
+{
+ PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine());
+ int i;
+
+ for (i = 0; i < pnv->num_chips; i++) {
+ Pnv10Chip *chip10 = PNV10_CHIP(pnv->chips[i]);
+ PnvXive2 *xive = &chip10->xive;
+
+ if (pnv_xive2_block_id(xive) == blk) {
+ return xive;
+ }
+ }
+ return NULL;
+}
+
+/*
+ * VST accessors for ESB, EAT, ENDT, NVP
+ *
+ * Indirect VST tables are arrays of VSDs pointing to a page (of same
+ * size). Each page is a direct VST table.
+ */
+
+#define XIVE_VSD_SIZE 8
+
+/* Indirect page size can be 4K, 64K, 2M, 16M. */
+static uint64_t pnv_xive2_vst_page_size_allowed(uint32_t page_shift)
+{
+ return page_shift == 12 || page_shift == 16 ||
+ page_shift == 21 || page_shift == 24;
+}
+
+static uint64_t pnv_xive2_vst_addr_direct(PnvXive2 *xive, uint32_t type,
+ uint64_t vsd, uint32_t idx)
+{
+ const XiveVstInfo *info = &vst_infos[type];
+ uint64_t vst_addr = vsd & VSD_ADDRESS_MASK;
+ uint64_t vst_tsize = 1ull << (GETFIELD(VSD_TSIZE, vsd) + 12);
+ uint32_t idx_max;
+
+ idx_max = vst_tsize / info->size - 1;
+ if (idx > idx_max) {
+#ifdef XIVE2_DEBUG
+ xive2_error(xive, "VST: %s entry %x out of range [ 0 .. %x ] !?",
+ info->name, idx, idx_max);
+#endif
+ return 0;
+ }
+
+ return vst_addr + idx * info->size;
+}
+
+static uint64_t pnv_xive2_vst_addr_indirect(PnvXive2 *xive, uint32_t type,
+ uint64_t vsd, uint32_t idx)
+{
+ const XiveVstInfo *info = &vst_infos[type];
+ uint64_t vsd_addr;
+ uint32_t vsd_idx;
+ uint32_t page_shift;
+ uint32_t vst_per_page;
+
+ /* Get the page size of the indirect table. */
+ vsd_addr = vsd & VSD_ADDRESS_MASK;
+ ldq_be_dma(&address_space_memory, vsd_addr, &vsd, MEMTXATTRS_UNSPECIFIED);
+
+ if (!(vsd & VSD_ADDRESS_MASK)) {
+ xive2_error(xive, "VST: invalid %s entry %x !?", info->name, idx);
+ return 0;
+ }
+
+ page_shift = GETFIELD(VSD_TSIZE, vsd) + 12;
+
+ if (!pnv_xive2_vst_page_size_allowed(page_shift)) {
+ xive2_error(xive, "VST: invalid %s page shift %d", info->name,
+ page_shift);
+ return 0;
+ }
+
+ vst_per_page = (1ull << page_shift) / info->size;
+ vsd_idx = idx / vst_per_page;
+
+ /* Load the VSD we are looking for, if not already done */
+ if (vsd_idx) {
+ vsd_addr = vsd_addr + vsd_idx * XIVE_VSD_SIZE;
+ ldq_be_dma(&address_space_memory, vsd_addr, &vsd,
+ MEMTXATTRS_UNSPECIFIED);
+
+ if (!(vsd & VSD_ADDRESS_MASK)) {
+ xive2_error(xive, "VST: invalid %s entry %x !?", info->name, idx);
+ return 0;
+ }
+
+ /*
+ * Check that the pages have a consistent size across the
+ * indirect table
+ */
+ if (page_shift != GETFIELD(VSD_TSIZE, vsd) + 12) {
+ xive2_error(xive, "VST: %s entry %x indirect page size differ !?",
+ info->name, idx);
+ return 0;
+ }
+ }
+
+ return pnv_xive2_vst_addr_direct(xive, type, vsd, (idx % vst_per_page));
+}
+
+static uint64_t pnv_xive2_vst_addr(PnvXive2 *xive, uint32_t type, uint8_t blk,
+ uint32_t idx)
+{
+ const XiveVstInfo *info = &vst_infos[type];
+ uint64_t vsd;
+
+ if (blk >= info->max_blocks) {
+ xive2_error(xive, "VST: invalid block id %d for VST %s %d !?",
+ blk, info->name, idx);
+ return 0;
+ }
+
+ vsd = xive->vsds[type][blk];
+
+ /* Remote VST access */
+ if (GETFIELD(VSD_MODE, vsd) == VSD_MODE_FORWARD) {
+ xive = pnv_xive2_get_remote(blk);
+
+ return xive ? pnv_xive2_vst_addr(xive, type, blk, idx) : 0;
+ }
+
+ if (VSD_INDIRECT & vsd) {
+ return pnv_xive2_vst_addr_indirect(xive, type, vsd, idx);
+ }
+
+ return pnv_xive2_vst_addr_direct(xive, type, vsd, idx);
+}
+
+static int pnv_xive2_vst_read(PnvXive2 *xive, uint32_t type, uint8_t blk,
+ uint32_t idx, void *data)
+{
+ const XiveVstInfo *info = &vst_infos[type];
+ uint64_t addr = pnv_xive2_vst_addr(xive, type, blk, idx);
+
+ if (!addr) {
+ return -1;
+ }
+
+ cpu_physical_memory_read(addr, data, info->size);
+ return 0;
+}
+
+#define XIVE_VST_WORD_ALL -1
+
+static int pnv_xive2_vst_write(PnvXive2 *xive, uint32_t type, uint8_t blk,
+ uint32_t idx, void *data, uint32_t word_number)
+{
+ const XiveVstInfo *info = &vst_infos[type];
+ uint64_t addr = pnv_xive2_vst_addr(xive, type, blk, idx);
+
+ if (!addr) {
+ return -1;
+ }
+
+ if (word_number == XIVE_VST_WORD_ALL) {
+ cpu_physical_memory_write(addr, data, info->size);
+ } else {
+ cpu_physical_memory_write(addr + word_number * 4,
+ data + word_number * 4, 4);
+ }
+ return 0;
+}
+
+static int pnv_xive2_get_end(Xive2Router *xrtr, uint8_t blk, uint32_t idx,
+ Xive2End *end)
+{
+ return pnv_xive2_vst_read(PNV_XIVE2(xrtr), VST_END, blk, idx, end);
+}
+
+static int pnv_xive2_write_end(Xive2Router *xrtr, uint8_t blk, uint32_t idx,
+ Xive2End *end, uint8_t word_number)
+{
+ return pnv_xive2_vst_write(PNV_XIVE2(xrtr), VST_END, blk, idx, end,
+ word_number);
+}
+
+static int pnv_xive2_end_update(PnvXive2 *xive)
+{
+ uint8_t blk = GETFIELD(VC_ENDC_WATCH_BLOCK_ID,
+ xive->vc_regs[(VC_ENDC_WATCH0_SPEC >> 3)]);
+ uint32_t idx = GETFIELD(VC_ENDC_WATCH_INDEX,
+ xive->vc_regs[(VC_ENDC_WATCH0_SPEC >> 3)]);
+ int i;
+ uint64_t endc_watch[4];
+
+ for (i = 0; i < ARRAY_SIZE(endc_watch); i++) {
+ endc_watch[i] =
+ cpu_to_be64(xive->vc_regs[(VC_ENDC_WATCH0_DATA0 >> 3) + i]);
+ }
+
+ return pnv_xive2_vst_write(xive, VST_END, blk, idx, endc_watch,
+ XIVE_VST_WORD_ALL);
+}
+
+static void pnv_xive2_end_cache_load(PnvXive2 *xive)
+{
+ uint8_t blk = GETFIELD(VC_ENDC_WATCH_BLOCK_ID,
+ xive->vc_regs[(VC_ENDC_WATCH0_SPEC >> 3)]);
+ uint32_t idx = GETFIELD(VC_ENDC_WATCH_INDEX,
+ xive->vc_regs[(VC_ENDC_WATCH0_SPEC >> 3)]);
+ uint64_t endc_watch[4] = { 0 };
+ int i;
+
+ if (pnv_xive2_vst_read(xive, VST_END, blk, idx, endc_watch)) {
+ xive2_error(xive, "VST: no END entry %x/%x !?", blk, idx);
+ }
+
+ for (i = 0; i < ARRAY_SIZE(endc_watch); i++) {
+ xive->vc_regs[(VC_ENDC_WATCH0_DATA0 >> 3) + i] =
+ be64_to_cpu(endc_watch[i]);
+ }
+}
+
+static int pnv_xive2_get_nvp(Xive2Router *xrtr, uint8_t blk, uint32_t idx,
+ Xive2Nvp *nvp)
+{
+ return pnv_xive2_vst_read(PNV_XIVE2(xrtr), VST_NVP, blk, idx, nvp);
+}
+
+static int pnv_xive2_write_nvp(Xive2Router *xrtr, uint8_t blk, uint32_t idx,
+ Xive2Nvp *nvp, uint8_t word_number)
+{
+ return pnv_xive2_vst_write(PNV_XIVE2(xrtr), VST_NVP, blk, idx, nvp,
+ word_number);
+}
+
+static int pnv_xive2_nvp_update(PnvXive2 *xive)
+{
+ uint8_t blk = GETFIELD(PC_NXC_WATCH_BLOCK_ID,
+ xive->pc_regs[(PC_NXC_WATCH0_SPEC >> 3)]);
+ uint32_t idx = GETFIELD(PC_NXC_WATCH_INDEX,
+ xive->pc_regs[(PC_NXC_WATCH0_SPEC >> 3)]);
+ int i;
+ uint64_t nxc_watch[4];
+
+ for (i = 0; i < ARRAY_SIZE(nxc_watch); i++) {
+ nxc_watch[i] =
+ cpu_to_be64(xive->pc_regs[(PC_NXC_WATCH0_DATA0 >> 3) + i]);
+ }
+
+ return pnv_xive2_vst_write(xive, VST_NVP, blk, idx, nxc_watch,
+ XIVE_VST_WORD_ALL);
+}
+
+static void pnv_xive2_nvp_cache_load(PnvXive2 *xive)
+{
+ uint8_t blk = GETFIELD(PC_NXC_WATCH_BLOCK_ID,
+ xive->pc_regs[(PC_NXC_WATCH0_SPEC >> 3)]);
+ uint32_t idx = GETFIELD(PC_NXC_WATCH_INDEX,
+ xive->pc_regs[(PC_NXC_WATCH0_SPEC >> 3)]);
+ uint64_t nxc_watch[4] = { 0 };
+ int i;
+
+ if (pnv_xive2_vst_read(xive, VST_NVP, blk, idx, nxc_watch)) {
+ xive2_error(xive, "VST: no NVP entry %x/%x !?", blk, idx);
+ }
+
+ for (i = 0; i < ARRAY_SIZE(nxc_watch); i++) {
+ xive->pc_regs[(PC_NXC_WATCH0_DATA0 >> 3) + i] =
+ be64_to_cpu(nxc_watch[i]);
+ }
+}
+
+static int pnv_xive2_get_eas(Xive2Router *xrtr, uint8_t blk, uint32_t idx,
+ Xive2Eas *eas)
+{
+ PnvXive2 *xive = PNV_XIVE2(xrtr);
+
+ if (pnv_xive2_block_id(xive) != blk) {
+ xive2_error(xive, "VST: EAS %x is remote !?", XIVE_EAS(blk, idx));
+ return -1;
+ }
+
+ return pnv_xive2_vst_read(xive, VST_EAS, blk, idx, eas);
+}
+
+static bool pnv_xive2_is_cpu_enabled(PnvXive2 *xive, PowerPCCPU *cpu)
+{
+ int pir = ppc_cpu_pir(cpu);
+ uint32_t fc = PNV10_PIR2FUSEDCORE(pir);
+ uint64_t reg = fc < 8 ? TCTXT_EN0 : TCTXT_EN1;
+ uint32_t bit = pir & 0x3f;
+
+ return xive->tctxt_regs[reg >> 3] & PPC_BIT(bit);
+}
+
+static int pnv_xive2_match_nvt(XivePresenter *xptr, uint8_t format,
+ uint8_t nvt_blk, uint32_t nvt_idx,
+ bool cam_ignore, uint8_t priority,
+ uint32_t logic_serv, XiveTCTXMatch *match)
+{
+ PnvXive2 *xive = PNV_XIVE2(xptr);
+ PnvChip *chip = xive->chip;
+ int count = 0;
+ int i, j;
+
+ for (i = 0; i < chip->nr_cores; i++) {
+ PnvCore *pc = chip->cores[i];
+ CPUCore *cc = CPU_CORE(pc);
+
+ for (j = 0; j < cc->nr_threads; j++) {
+ PowerPCCPU *cpu = pc->threads[j];
+ XiveTCTX *tctx;
+ int ring;
+
+ if (!pnv_xive2_is_cpu_enabled(xive, cpu)) {
+ continue;
+ }
+
+ tctx = XIVE_TCTX(pnv_cpu_state(cpu)->intc);
+
+ ring = xive2_presenter_tctx_match(xptr, tctx, format, nvt_blk,
+ nvt_idx, cam_ignore,
+ logic_serv);
+
+ /*
+ * Save the context and follow on to catch duplicates,
+ * that we don't support yet.
+ */
+ if (ring != -1) {
+ if (match->tctx) {
+ qemu_log_mask(LOG_GUEST_ERROR, "XIVE: already found a "
+ "thread context NVT %x/%x\n",
+ nvt_blk, nvt_idx);
+ return false;
+ }
+
+ match->ring = ring;
+ match->tctx = tctx;
+ count++;
+ }
+ }
+ }
+
+ return count;
+}
+
+static uint8_t pnv_xive2_get_block_id(Xive2Router *xrtr)
+{
+ return pnv_xive2_block_id(PNV_XIVE2(xrtr));
+}
+
+/*
+ * The TIMA MMIO space is shared among the chips and to identify the
+ * chip from which the access is being done, we extract the chip id
+ * from the PIR.
+ */
+static PnvXive2 *pnv_xive2_tm_get_xive(PowerPCCPU *cpu)
+{
+ int pir = ppc_cpu_pir(cpu);
+ XivePresenter *xptr = XIVE_TCTX(pnv_cpu_state(cpu)->intc)->xptr;
+ PnvXive2 *xive = PNV_XIVE2(xptr);
+
+ if (!pnv_xive2_is_cpu_enabled(xive, cpu)) {
+ xive2_error(xive, "IC: CPU %x is not enabled", pir);
+ }
+ return xive;
+}
+
+/*
+ * The internal sources of the interrupt controller have no knowledge
+ * of the XIVE2 chip on which they reside. Encode the block id in the
+ * source interrupt number before forwarding the source event
+ * notification to the Router. This is required on a multichip system.
+ */
+static void pnv_xive2_notify(XiveNotifier *xn, uint32_t srcno)
+{
+ PnvXive2 *xive = PNV_XIVE2(xn);
+ uint8_t blk = pnv_xive2_block_id(xive);
+
+ xive2_router_notify(xn, XIVE_EAS(blk, srcno));
+}
+
+/*
+ * Set Translation Tables
+ *
+ * TODO add support for multiple sets
+ */
+static int pnv_xive2_stt_set_data(PnvXive2 *xive, uint64_t val)
+{
+ uint8_t tsel = GETFIELD(CQ_TAR_SELECT, xive->cq_regs[CQ_TAR >> 3]);
+ uint8_t entry = GETFIELD(CQ_TAR_ENTRY_SELECT,
+ xive->cq_regs[CQ_TAR >> 3]);
+
+ switch (tsel) {
+ case CQ_TAR_NVPG:
+ case CQ_TAR_ESB:
+ case CQ_TAR_END:
+ xive->tables[tsel][entry] = val;
+ break;
+ default:
+ xive2_error(xive, "IC: unsupported table %d", tsel);
+ return -1;
+ }
+
+ if (xive->cq_regs[CQ_TAR >> 3] & CQ_TAR_AUTOINC) {
+ xive->cq_regs[CQ_TAR >> 3] = SETFIELD(CQ_TAR_ENTRY_SELECT,
+ xive->cq_regs[CQ_TAR >> 3], ++entry);
+ }
+
+ return 0;
+}
+/*
+ * Virtual Structure Tables (VST) configuration
+ */
+static void pnv_xive2_vst_set_exclusive(PnvXive2 *xive, uint8_t type,
+ uint8_t blk, uint64_t vsd)
+{
+ Xive2EndSource *end_xsrc = &xive->end_source;
+ XiveSource *xsrc = &xive->ipi_source;
+ const XiveVstInfo *info = &vst_infos[type];
+ uint32_t page_shift = GETFIELD(VSD_TSIZE, vsd) + 12;
+ uint64_t vst_tsize = 1ull << page_shift;
+ uint64_t vst_addr = vsd & VSD_ADDRESS_MASK;
+
+ /* Basic checks */
+
+ if (VSD_INDIRECT & vsd) {
+ if (!pnv_xive2_vst_page_size_allowed(page_shift)) {
+ xive2_error(xive, "VST: invalid %s page shift %d", info->name,
+ page_shift);
+ return;
+ }
+ }
+
+ if (!QEMU_IS_ALIGNED(vst_addr, 1ull << page_shift)) {
+ xive2_error(xive, "VST: %s table address 0x%"PRIx64
+ " is not aligned with page shift %d",
+ info->name, vst_addr, page_shift);
+ return;
+ }
+
+ /* Record the table configuration (in SRAM on HW) */
+ xive->vsds[type][blk] = vsd;
+
+ /* Now tune the models with the configuration provided by the FW */
+
+ switch (type) {
+ case VST_ESB:
+ /*
+ * Backing store pages for the source PQ bits. The model does
+ * not use these PQ bits backed in RAM because the XiveSource
+ * model has its own.
+ *
+ * If the table is direct, we can compute the number of PQ
+ * entries provisioned by FW (such as skiboot) and resize the
+ * ESB window accordingly.
+ */
+ if (!(VSD_INDIRECT & vsd)) {
+ memory_region_set_size(&xsrc->esb_mmio, vst_tsize * SBE_PER_BYTE
+ * (1ull << xsrc->esb_shift));
+ }
+
+ memory_region_add_subregion(&xive->esb_mmio, 0, &xsrc->esb_mmio);
+ break;
+
+ case VST_EAS: /* Nothing to be done */
+ break;
+
+ case VST_END:
+ /*
+ * Backing store pages for the END.
+ */
+ if (!(VSD_INDIRECT & vsd)) {
+ memory_region_set_size(&end_xsrc->esb_mmio, (vst_tsize / info->size)
+ * (1ull << end_xsrc->esb_shift));
+ }
+ memory_region_add_subregion(&xive->end_mmio, 0, &end_xsrc->esb_mmio);
+ break;
+
+ case VST_NVP: /* Not modeled */
+ case VST_NVG: /* Not modeled */
+ case VST_NVC: /* Not modeled */
+ case VST_IC: /* Not modeled */
+ case VST_SYNC: /* Not modeled */
+ case VST_ERQ: /* Not modeled */
+ break;
+
+ default:
+ g_assert_not_reached();
+ }
+}
+
+/*
+ * Both PC and VC sub-engines are configured as each use the Virtual
+ * Structure Tables
+ */
+static void pnv_xive2_vst_set_data(PnvXive2 *xive, uint64_t vsd)
+{
+ uint8_t mode = GETFIELD(VSD_MODE, vsd);
+ uint8_t type = GETFIELD(VC_VSD_TABLE_SELECT,
+ xive->vc_regs[VC_VSD_TABLE_ADDR >> 3]);
+ uint8_t blk = GETFIELD(VC_VSD_TABLE_ADDRESS,
+ xive->vc_regs[VC_VSD_TABLE_ADDR >> 3]);
+ uint64_t vst_addr = vsd & VSD_ADDRESS_MASK;
+
+ if (type > VST_ERQ) {
+ xive2_error(xive, "VST: invalid table type %d", type);
+ return;
+ }
+
+ if (blk >= vst_infos[type].max_blocks) {
+ xive2_error(xive, "VST: invalid block id %d for"
+ " %s table", blk, vst_infos[type].name);
+ return;
+ }
+
+ if (!vst_addr) {
+ xive2_error(xive, "VST: invalid %s table address",
+ vst_infos[type].name);
+ return;
+ }
+
+ switch (mode) {
+ case VSD_MODE_FORWARD:
+ xive->vsds[type][blk] = vsd;
+ break;
+
+ case VSD_MODE_EXCLUSIVE:
+ pnv_xive2_vst_set_exclusive(xive, type, blk, vsd);
+ break;
+
+ default:
+ xive2_error(xive, "VST: unsupported table mode %d", mode);
+ return;
+ }
+}
+
+/*
+ * MMIO handlers
+ */
+
+
+/*
+ * IC BAR layout
+ *
+ * Page 0: Internal CQ register accesses (reads & writes)
+ * Page 1: Internal PC register accesses (reads & writes)
+ * Page 2: Internal VC register accesses (reads & writes)
+ * Page 3: Internal TCTXT (TIMA) reg accesses (read & writes)
+ * Page 4: Notify Port page (writes only, w/data),
+ * Page 5: Reserved
+ * Page 6: Sync Poll page (writes only, dataless)
+ * Page 7: Sync Inject page (writes only, dataless)
+ * Page 8: LSI Trigger page (writes only, dataless)
+ * Page 9: LSI SB Management page (reads & writes dataless)
+ * Pages 10-255: Reserved
+ * Pages 256-383: Direct mapped Thread Context Area (reads & writes)
+ * covering the 128 threads in P10.
+ * Pages 384-511: Reserved
+ */
+typedef struct PnvXive2Region {
+ const char *name;
+ uint32_t pgoff;
+ uint32_t pgsize;
+ const MemoryRegionOps *ops;
+} PnvXive2Region;
+
+static const MemoryRegionOps pnv_xive2_ic_cq_ops;
+static const MemoryRegionOps pnv_xive2_ic_pc_ops;
+static const MemoryRegionOps pnv_xive2_ic_vc_ops;
+static const MemoryRegionOps pnv_xive2_ic_tctxt_ops;
+static const MemoryRegionOps pnv_xive2_ic_notify_ops;
+static const MemoryRegionOps pnv_xive2_ic_sync_ops;
+static const MemoryRegionOps pnv_xive2_ic_lsi_ops;
+static const MemoryRegionOps pnv_xive2_ic_tm_indirect_ops;
+
+/* 512 pages. 4K: 2M range, 64K: 32M range */
+static const PnvXive2Region pnv_xive2_ic_regions[] = {
+ { "xive-ic-cq", 0, 1, &pnv_xive2_ic_cq_ops },
+ { "xive-ic-vc", 1, 1, &pnv_xive2_ic_vc_ops },
+ { "xive-ic-pc", 2, 1, &pnv_xive2_ic_pc_ops },
+ { "xive-ic-tctxt", 3, 1, &pnv_xive2_ic_tctxt_ops },
+ { "xive-ic-notify", 4, 1, &pnv_xive2_ic_notify_ops },
+ /* page 5 reserved */
+ { "xive-ic-sync", 6, 2, &pnv_xive2_ic_sync_ops },
+ { "xive-ic-lsi", 8, 2, &pnv_xive2_ic_lsi_ops },
+ /* pages 10-255 reserved */
+ { "xive-ic-tm-indirect", 256, 128, &pnv_xive2_ic_tm_indirect_ops },
+ /* pages 384-511 reserved */
+};
+
+/*
+ * CQ operations
+ */
+
+static uint64_t pnv_xive2_ic_cq_read(void *opaque, hwaddr offset,
+ unsigned size)
+{
+ PnvXive2 *xive = PNV_XIVE2(opaque);
+ uint32_t reg = offset >> 3;
+ uint64_t val = 0;
+
+ switch (offset) {
+ case CQ_XIVE_CAP: /* Set at reset */
+ case CQ_XIVE_CFG:
+ val = xive->cq_regs[reg];
+ break;
+ case CQ_MSGSND: /* TODO check the #cores of the machine */
+ val = 0xffffffff00000000;
+ break;
+ case CQ_CFG_PB_GEN:
+ val = CQ_CFG_PB_GEN_PB_INIT; /* TODO: fix CQ_CFG_PB_GEN default value */
+ break;
+ default:
+ xive2_error(xive, "CQ: invalid read @%"HWADDR_PRIx, offset);
+ }
+
+ return val;
+}
+
+static uint64_t pnv_xive2_bar_size(uint64_t val)
+{
+ return 1ull << (GETFIELD(CQ_BAR_RANGE, val) + 24);
+}
+
+static void pnv_xive2_ic_cq_write(void *opaque, hwaddr offset,
+ uint64_t val, unsigned size)
+{
+ PnvXive2 *xive = PNV_XIVE2(opaque);
+ MemoryRegion *sysmem = get_system_memory();
+ uint32_t reg = offset >> 3;
+ int i;
+
+ switch (offset) {
+ case CQ_XIVE_CFG:
+ case CQ_RST_CTL: /* TODO: reset all BARs */
+ break;
+
+ case CQ_IC_BAR:
+ xive->ic_shift = val & CQ_IC_BAR_64K ? 16 : 12;
+ if (!(val & CQ_IC_BAR_VALID)) {
+ xive->ic_base = 0;
+ if (xive->cq_regs[reg] & CQ_IC_BAR_VALID) {
+ for (i = 0; i < ARRAY_SIZE(xive->ic_mmios); i++) {
+ memory_region_del_subregion(&xive->ic_mmio,
+ &xive->ic_mmios[i]);
+ }
+ memory_region_del_subregion(sysmem, &xive->ic_mmio);
+ }
+ } else {
+ xive->ic_base = val & ~(CQ_IC_BAR_VALID | CQ_IC_BAR_64K);
+ if (!(xive->cq_regs[reg] & CQ_IC_BAR_VALID)) {
+ for (i = 0; i < ARRAY_SIZE(xive->ic_mmios); i++) {
+ memory_region_add_subregion(&xive->ic_mmio,
+ pnv_xive2_ic_regions[i].pgoff << xive->ic_shift,
+ &xive->ic_mmios[i]);
+ }
+ memory_region_add_subregion(sysmem, xive->ic_base,
+ &xive->ic_mmio);
+ }
+ }
+ break;
+
+ case CQ_TM_BAR:
+ xive->tm_shift = val & CQ_TM_BAR_64K ? 16 : 12;
+ if (!(val & CQ_TM_BAR_VALID)) {
+ xive->tm_base = 0;
+ if (xive->cq_regs[reg] & CQ_TM_BAR_VALID) {
+ memory_region_del_subregion(sysmem, &xive->tm_mmio);
+ }
+ } else {
+ xive->tm_base = val & ~(CQ_TM_BAR_VALID | CQ_TM_BAR_64K);
+ if (!(xive->cq_regs[reg] & CQ_TM_BAR_VALID)) {
+ memory_region_add_subregion(sysmem, xive->tm_base,
+ &xive->tm_mmio);
+ }
+ }
+ break;
+
+ case CQ_ESB_BAR:
+ xive->esb_shift = val & CQ_BAR_64K ? 16 : 12;
+ if (!(val & CQ_BAR_VALID)) {
+ xive->esb_base = 0;
+ if (xive->cq_regs[reg] & CQ_BAR_VALID) {
+ memory_region_del_subregion(sysmem, &xive->esb_mmio);
+ }
+ } else {
+ xive->esb_base = val & CQ_BAR_ADDR;
+ if (!(xive->cq_regs[reg] & CQ_BAR_VALID)) {
+ memory_region_set_size(&xive->esb_mmio,
+ pnv_xive2_bar_size(val));
+ memory_region_add_subregion(sysmem, xive->esb_base,
+ &xive->esb_mmio);
+ }
+ }
+ break;
+
+ case CQ_END_BAR:
+ xive->end_shift = val & CQ_BAR_64K ? 16 : 12;
+ if (!(val & CQ_BAR_VALID)) {
+ xive->end_base = 0;
+ if (xive->cq_regs[reg] & CQ_BAR_VALID) {
+ memory_region_del_subregion(sysmem, &xive->end_mmio);
+ }
+ } else {
+ xive->end_base = val & CQ_BAR_ADDR;
+ if (!(xive->cq_regs[reg] & CQ_BAR_VALID)) {
+ memory_region_set_size(&xive->end_mmio,
+ pnv_xive2_bar_size(val));
+ memory_region_add_subregion(sysmem, xive->end_base,
+ &xive->end_mmio);
+ }
+ }
+ break;
+
+ case CQ_NVC_BAR:
+ xive->nvc_shift = val & CQ_BAR_64K ? 16 : 12;
+ if (!(val & CQ_BAR_VALID)) {
+ xive->nvc_base = 0;
+ if (xive->cq_regs[reg] & CQ_BAR_VALID) {
+ memory_region_del_subregion(sysmem, &xive->nvc_mmio);
+ }
+ } else {
+ xive->nvc_base = val & CQ_BAR_ADDR;
+ if (!(xive->cq_regs[reg] & CQ_BAR_VALID)) {
+ memory_region_set_size(&xive->nvc_mmio,
+ pnv_xive2_bar_size(val));
+ memory_region_add_subregion(sysmem, xive->nvc_base,
+ &xive->nvc_mmio);
+ }
+ }
+ break;
+
+ case CQ_NVPG_BAR:
+ xive->nvpg_shift = val & CQ_BAR_64K ? 16 : 12;
+ if (!(val & CQ_BAR_VALID)) {
+ xive->nvpg_base = 0;
+ if (xive->cq_regs[reg] & CQ_BAR_VALID) {
+ memory_region_del_subregion(sysmem, &xive->nvpg_mmio);
+ }
+ } else {
+ xive->nvpg_base = val & CQ_BAR_ADDR;
+ if (!(xive->cq_regs[reg] & CQ_BAR_VALID)) {
+ memory_region_set_size(&xive->nvpg_mmio,
+ pnv_xive2_bar_size(val));
+ memory_region_add_subregion(sysmem, xive->nvpg_base,
+ &xive->nvpg_mmio);
+ }
+ }
+ break;
+
+ case CQ_TAR: /* Set Translation Table Address */
+ break;
+ case CQ_TDR: /* Set Translation Table Data */
+ pnv_xive2_stt_set_data(xive, val);
+ break;
+ case CQ_FIRMASK_OR: /* FIR error reporting */
+ break;
+ default:
+ xive2_error(xive, "CQ: invalid write 0x%"HWADDR_PRIx, offset);
+ return;
+ }
+
+ xive->cq_regs[reg] = val;
+}
+
+static const MemoryRegionOps pnv_xive2_ic_cq_ops = {
+ .read = pnv_xive2_ic_cq_read,
+ .write = pnv_xive2_ic_cq_write,
+ .endianness = DEVICE_BIG_ENDIAN,
+ .valid = {
+ .min_access_size = 8,
+ .max_access_size = 8,
+ },
+ .impl = {
+ .min_access_size = 8,
+ .max_access_size = 8,
+ },
+};
+
+static uint64_t pnv_xive2_ic_vc_read(void *opaque, hwaddr offset,
+ unsigned size)
+{
+ PnvXive2 *xive = PNV_XIVE2(opaque);
+ uint64_t val = 0;
+ uint32_t reg = offset >> 3;
+
+ switch (offset) {
+ /*
+ * VSD table settings.
+ */
+ case VC_VSD_TABLE_ADDR:
+ case VC_VSD_TABLE_DATA:
+ val = xive->vc_regs[reg];
+ break;
+
+ /*
+ * ESB cache updates (not modeled)
+ */
+ case VC_ESBC_FLUSH_CTRL:
+ xive->vc_regs[reg] &= ~VC_ESBC_FLUSH_CTRL_POLL_VALID;
+ val = xive->vc_regs[reg];
+ break;
+
+ /*
+ * EAS cache updates (not modeled)
+ */
+ case VC_EASC_FLUSH_CTRL:
+ xive->vc_regs[reg] &= ~VC_EASC_FLUSH_CTRL_POLL_VALID;
+ val = xive->vc_regs[reg];
+ break;
+
+ /*
+ * END cache updates
+ */
+ case VC_ENDC_WATCH0_SPEC:
+ xive->vc_regs[reg] &= ~(VC_ENDC_WATCH_FULL | VC_ENDC_WATCH_CONFLICT);
+ val = xive->vc_regs[reg];
+ break;
+
+ case VC_ENDC_WATCH0_DATA0:
+ /*
+ * Load DATA registers from cache with data requested by the
+ * SPEC register
+ */
+ pnv_xive2_end_cache_load(xive);
+ val = xive->vc_regs[reg];
+ break;
+
+ case VC_ENDC_WATCH0_DATA1 ... VC_ENDC_WATCH0_DATA3:
+ val = xive->vc_regs[reg];
+ break;
+
+ case VC_ENDC_FLUSH_CTRL:
+ xive->vc_regs[reg] &= ~VC_ENDC_FLUSH_CTRL_POLL_VALID;
+ val = xive->vc_regs[reg];
+ break;
+
+ /*
+ * Indirect invalidation
+ */
+ case VC_AT_MACRO_KILL_MASK:
+ val = xive->vc_regs[reg];
+ break;
+
+ case VC_AT_MACRO_KILL:
+ xive->vc_regs[reg] &= ~VC_AT_MACRO_KILL_VALID;
+ val = xive->vc_regs[reg];
+ break;
+
+ /*
+ * Interrupt fifo overflow in memory backing store (Not modeled)
+ */
+ case VC_QUEUES_CFG_REM0 ... VC_QUEUES_CFG_REM6:
+ val = xive->vc_regs[reg];
+ break;
+
+ /*
+ * Synchronisation
+ */
+ case VC_ENDC_SYNC_DONE:
+ val = VC_ENDC_SYNC_POLL_DONE;
+ break;
+ default:
+ xive2_error(xive, "VC: invalid read @%"HWADDR_PRIx, offset);
+ }
+
+ return val;
+}
+
+static void pnv_xive2_ic_vc_write(void *opaque, hwaddr offset,
+ uint64_t val, unsigned size)
+{
+ PnvXive2 *xive = PNV_XIVE2(opaque);
+ uint32_t reg = offset >> 3;
+
+ switch (offset) {
+ /*
+ * VSD table settings.
+ */
+ case VC_VSD_TABLE_ADDR:
+ break;
+ case VC_VSD_TABLE_DATA:
+ pnv_xive2_vst_set_data(xive, val);
+ break;
+
+ /*
+ * ESB cache updates (not modeled)
+ */
+ /* case VC_ESBC_FLUSH_CTRL: */
+ case VC_ESBC_FLUSH_POLL:
+ xive->vc_regs[VC_ESBC_FLUSH_CTRL >> 3] |= VC_ESBC_FLUSH_CTRL_POLL_VALID;
+ /* ESB update */
+ break;
+
+ /*
+ * EAS cache updates (not modeled)
+ */
+ /* case VC_EASC_FLUSH_CTRL: */
+ case VC_EASC_FLUSH_POLL:
+ xive->vc_regs[VC_EASC_FLUSH_CTRL >> 3] |= VC_EASC_FLUSH_CTRL_POLL_VALID;
+ /* EAS update */
+ break;
+
+ /*
+ * END cache updates
+ */
+ case VC_ENDC_WATCH0_SPEC:
+ val &= ~VC_ENDC_WATCH_CONFLICT; /* HW will set this bit */
+ break;
+
+ case VC_ENDC_WATCH0_DATA1 ... VC_ENDC_WATCH0_DATA3:
+ break;
+ case VC_ENDC_WATCH0_DATA0:
+ /* writing to DATA0 triggers the cache write */
+ xive->vc_regs[reg] = val;
+ pnv_xive2_end_update(xive);
+ break;
+
+
+ /* case VC_ENDC_FLUSH_CTRL: */
+ case VC_ENDC_FLUSH_POLL:
+ xive->vc_regs[VC_ENDC_FLUSH_CTRL >> 3] |= VC_ENDC_FLUSH_CTRL_POLL_VALID;
+ break;
+
+ /*
+ * Indirect invalidation
+ */
+ case VC_AT_MACRO_KILL:
+ case VC_AT_MACRO_KILL_MASK:
+ break;
+
+ /*
+ * Interrupt fifo overflow in memory backing store (Not modeled)
+ */
+ case VC_QUEUES_CFG_REM0 ... VC_QUEUES_CFG_REM6:
+ break;
+
+ /*
+ * Synchronisation
+ */
+ case VC_ENDC_SYNC_DONE:
+ break;
+
+ default:
+ xive2_error(xive, "VC: invalid write @%"HWADDR_PRIx, offset);
+ return;
+ }
+
+ xive->vc_regs[reg] = val;
+}
+
+static const MemoryRegionOps pnv_xive2_ic_vc_ops = {
+ .read = pnv_xive2_ic_vc_read,
+ .write = pnv_xive2_ic_vc_write,
+ .endianness = DEVICE_BIG_ENDIAN,
+ .valid = {
+ .min_access_size = 8,
+ .max_access_size = 8,
+ },
+ .impl = {
+ .min_access_size = 8,
+ .max_access_size = 8,
+ },
+};
+
+static uint64_t pnv_xive2_ic_pc_read(void *opaque, hwaddr offset,
+ unsigned size)
+{
+ PnvXive2 *xive = PNV_XIVE2(opaque);
+ uint64_t val = -1;
+ uint32_t reg = offset >> 3;
+
+ switch (offset) {
+ /*
+ * VSD table settings.
+ */
+ case PC_VSD_TABLE_ADDR:
+ case PC_VSD_TABLE_DATA:
+ val = xive->pc_regs[reg];
+ break;
+
+ /*
+ * cache updates
+ */
+ case PC_NXC_WATCH0_SPEC:
+ xive->pc_regs[reg] &= ~(PC_NXC_WATCH_FULL | PC_NXC_WATCH_CONFLICT);
+ val = xive->pc_regs[reg];
+ break;
+
+ case PC_NXC_WATCH0_DATA0:
+ /*
+ * Load DATA registers from cache with data requested by the
+ * SPEC register
+ */
+ pnv_xive2_nvp_cache_load(xive);
+ val = xive->pc_regs[reg];
+ break;
+
+ case PC_NXC_WATCH0_DATA1 ... PC_NXC_WATCH0_DATA3:
+ val = xive->pc_regs[reg];
+ break;
+
+ case PC_NXC_FLUSH_CTRL:
+ xive->pc_regs[reg] &= ~PC_NXC_FLUSH_CTRL_POLL_VALID;
+ val = xive->pc_regs[reg];
+ break;
+
+ /*
+ * Indirect invalidation
+ */
+ case PC_AT_KILL:
+ xive->pc_regs[reg] &= ~PC_AT_KILL_VALID;
+ val = xive->pc_regs[reg];
+ break;
+
+ default:
+ xive2_error(xive, "PC: invalid read @%"HWADDR_PRIx, offset);
+ }
+
+ return val;
+}
+
+static void pnv_xive2_ic_pc_write(void *opaque, hwaddr offset,
+ uint64_t val, unsigned size)
+{
+ PnvXive2 *xive = PNV_XIVE2(opaque);
+ uint32_t reg = offset >> 3;
+
+ switch (offset) {
+
+ /*
+ * VSD table settings. Only taken into account in the VC
+ * sub-engine because the Xive2Router model combines both VC and PC
+ * sub-engines
+ */
+ case PC_VSD_TABLE_ADDR:
+ case PC_VSD_TABLE_DATA:
+ break;
+
+ /*
+ * cache updates
+ */
+ case PC_NXC_WATCH0_SPEC:
+ val &= ~PC_NXC_WATCH_CONFLICT; /* HW will set this bit */
+ break;
+
+ case PC_NXC_WATCH0_DATA1 ... PC_NXC_WATCH0_DATA3:
+ break;
+ case PC_NXC_WATCH0_DATA0:
+ /* writing to DATA0 triggers the cache write */
+ xive->pc_regs[reg] = val;
+ pnv_xive2_nvp_update(xive);
+ break;
+
+ /* case PC_NXC_FLUSH_CTRL: */
+ case PC_NXC_FLUSH_POLL:
+ xive->pc_regs[PC_NXC_FLUSH_CTRL >> 3] |= PC_NXC_FLUSH_CTRL_POLL_VALID;
+ break;
+
+ /*
+ * Indirect invalidation
+ */
+ case PC_AT_KILL:
+ case PC_AT_KILL_MASK:
+ break;
+
+ default:
+ xive2_error(xive, "PC: invalid write @%"HWADDR_PRIx, offset);
+ return;
+ }
+
+ xive->pc_regs[reg] = val;
+}
+
+static const MemoryRegionOps pnv_xive2_ic_pc_ops = {
+ .read = pnv_xive2_ic_pc_read,
+ .write = pnv_xive2_ic_pc_write,
+ .endianness = DEVICE_BIG_ENDIAN,
+ .valid = {
+ .min_access_size = 8,
+ .max_access_size = 8,
+ },
+ .impl = {
+ .min_access_size = 8,
+ .max_access_size = 8,
+ },
+};
+
+
+static uint64_t pnv_xive2_ic_tctxt_read(void *opaque, hwaddr offset,
+ unsigned size)
+{
+ PnvXive2 *xive = PNV_XIVE2(opaque);
+ uint64_t val = -1;
+ uint32_t reg = offset >> 3;
+
+ switch (offset) {
+ /*
+ * XIVE2 hardware thread enablement
+ */
+ case TCTXT_EN0:
+ case TCTXT_EN1:
+ val = xive->tctxt_regs[reg];
+ break;
+
+ case TCTXT_EN0_SET:
+ case TCTXT_EN0_RESET:
+ val = xive->tctxt_regs[TCTXT_EN0 >> 3];
+ break;
+ case TCTXT_EN1_SET:
+ case TCTXT_EN1_RESET:
+ val = xive->tctxt_regs[TCTXT_EN1 >> 3];
+ break;
+ default:
+ xive2_error(xive, "TCTXT: invalid read @%"HWADDR_PRIx, offset);
+ }
+
+ return val;
+}
+
+static void pnv_xive2_ic_tctxt_write(void *opaque, hwaddr offset,
+ uint64_t val, unsigned size)
+{
+ PnvXive2 *xive = PNV_XIVE2(opaque);
+ uint32_t reg = offset >> 3;
+
+ switch (offset) {
+ /*
+ * XIVE2 hardware thread enablement
+ */
+ case TCTXT_EN0: /* Physical Thread Enable */
+ case TCTXT_EN1: /* Physical Thread Enable (fused core) */
+ break;
+
+ case TCTXT_EN0_SET:
+ xive->tctxt_regs[TCTXT_EN0 >> 3] |= val;
+ break;
+ case TCTXT_EN1_SET:
+ xive->tctxt_regs[TCTXT_EN1 >> 3] |= val;
+ break;
+ case TCTXT_EN0_RESET:
+ xive->tctxt_regs[TCTXT_EN0 >> 3] &= ~val;
+ break;
+ case TCTXT_EN1_RESET:
+ xive->tctxt_regs[TCTXT_EN1 >> 3] &= ~val;
+ break;
+
+ default:
+ xive2_error(xive, "TCTXT: invalid write @%"HWADDR_PRIx, offset);
+ return;
+ }
+
+ xive->pc_regs[reg] = val;
+}
+
+static const MemoryRegionOps pnv_xive2_ic_tctxt_ops = {
+ .read = pnv_xive2_ic_tctxt_read,
+ .write = pnv_xive2_ic_tctxt_write,
+ .endianness = DEVICE_BIG_ENDIAN,
+ .valid = {
+ .min_access_size = 8,
+ .max_access_size = 8,
+ },
+ .impl = {
+ .min_access_size = 8,
+ .max_access_size = 8,
+ },
+};
+
+/*
+ * Redirect XSCOM to MMIO handlers
+ */
+static uint64_t pnv_xive2_xscom_read(void *opaque, hwaddr offset,
+ unsigned size)
+{
+ PnvXive2 *xive = PNV_XIVE2(opaque);
+ uint64_t val = -1;
+ uint32_t xscom_reg = offset >> 3;
+ uint32_t mmio_offset = (xscom_reg & 0xFF) << 3;
+
+ switch (xscom_reg) {
+ case 0x000 ... 0x0FF:
+ val = pnv_xive2_ic_cq_read(opaque, mmio_offset, size);
+ break;
+ case 0x100 ... 0x1FF:
+ val = pnv_xive2_ic_vc_read(opaque, mmio_offset, size);
+ break;
+ case 0x200 ... 0x2FF:
+ val = pnv_xive2_ic_pc_read(opaque, mmio_offset, size);
+ break;
+ case 0x300 ... 0x3FF:
+ val = pnv_xive2_ic_tctxt_read(opaque, mmio_offset, size);
+ break;
+ default:
+ xive2_error(xive, "XSCOM: invalid read @%"HWADDR_PRIx, offset);
+ }
+
+ return val;
+}
+
+static void pnv_xive2_xscom_write(void *opaque, hwaddr offset,
+ uint64_t val, unsigned size)
+{
+ PnvXive2 *xive = PNV_XIVE2(opaque);
+ uint32_t xscom_reg = offset >> 3;
+ uint32_t mmio_offset = (xscom_reg & 0xFF) << 3;
+
+ switch (xscom_reg) {
+ case 0x000 ... 0x0FF:
+ pnv_xive2_ic_cq_write(opaque, mmio_offset, val, size);
+ break;
+ case 0x100 ... 0x1FF:
+ pnv_xive2_ic_vc_write(opaque, mmio_offset, val, size);
+ break;
+ case 0x200 ... 0x2FF:
+ pnv_xive2_ic_pc_write(opaque, mmio_offset, val, size);
+ break;
+ case 0x300 ... 0x3FF:
+ pnv_xive2_ic_tctxt_write(opaque, mmio_offset, val, size);
+ break;
+ default:
+ xive2_error(xive, "XSCOM: invalid write @%"HWADDR_PRIx, offset);
+ }
+}
+
+static const MemoryRegionOps pnv_xive2_xscom_ops = {
+ .read = pnv_xive2_xscom_read,
+ .write = pnv_xive2_xscom_write,
+ .endianness = DEVICE_BIG_ENDIAN,
+ .valid = {
+ .min_access_size = 8,
+ .max_access_size = 8,
+ },
+ .impl = {
+ .min_access_size = 8,
+ .max_access_size = 8,
+ },
+};
+
+/*
+ * Notify port page. The layout is compatible between 4K and 64K pages :
+ *
+ * Page 1 Notify page (writes only)
+ * 0x000 - 0x7FF IPI interrupt (NPU)
+ * 0x800 - 0xFFF HW interrupt triggers (PSI, PHB)
+ */
+
+static void pnv_xive2_ic_hw_trigger(PnvXive2 *xive, hwaddr addr,
+ uint64_t val)
+{
+ uint8_t blk;
+ uint32_t idx;
+
+ if (val & XIVE_TRIGGER_END) {
+ xive2_error(xive, "IC: END trigger at @0x%"HWADDR_PRIx" data 0x%"PRIx64,
+ addr, val);
+ return;
+ }
+
+ /*
+ * Forward the source event notification directly to the Router.
+ * The source interrupt number should already be correctly encoded
+ * with the chip block id by the sending device (PHB, PSI).
+ */
+ blk = XIVE_EAS_BLOCK(val);
+ idx = XIVE_EAS_INDEX(val);
+
+ xive2_router_notify(XIVE_NOTIFIER(xive), XIVE_EAS(blk, idx));
+}
+
+static void pnv_xive2_ic_notify_write(void *opaque, hwaddr offset,
+ uint64_t val, unsigned size)
+{
+ PnvXive2 *xive = PNV_XIVE2(opaque);
+
+ /* VC: IPI triggers */
+ switch (offset) {
+ case 0x000 ... 0x7FF:
+ /* TODO: check IPI notify sub-page routing */
+ pnv_xive2_ic_hw_trigger(opaque, offset, val);
+ break;
+
+ /* VC: HW triggers */
+ case 0x800 ... 0xFFF:
+ pnv_xive2_ic_hw_trigger(opaque, offset, val);
+ break;
+
+ default:
+ xive2_error(xive, "NOTIFY: invalid write @%"HWADDR_PRIx, offset);
+ }
+}
+
+static uint64_t pnv_xive2_ic_notify_read(void *opaque, hwaddr offset,
+ unsigned size)
+{
+ PnvXive2 *xive = PNV_XIVE2(opaque);
+
+ /* loads are invalid */
+ xive2_error(xive, "NOTIFY: invalid read @%"HWADDR_PRIx, offset);
+ return -1;
+}
+
+static const MemoryRegionOps pnv_xive2_ic_notify_ops = {
+ .read = pnv_xive2_ic_notify_read,
+ .write = pnv_xive2_ic_notify_write,
+ .endianness = DEVICE_BIG_ENDIAN,
+ .valid = {
+ .min_access_size = 8,
+ .max_access_size = 8,
+ },
+ .impl = {
+ .min_access_size = 8,
+ .max_access_size = 8,
+ },
+};
+
+static uint64_t pnv_xive2_ic_lsi_read(void *opaque, hwaddr offset,
+ unsigned size)
+{
+ PnvXive2 *xive = PNV_XIVE2(opaque);
+
+ xive2_error(xive, "LSI: invalid read @%"HWADDR_PRIx, offset);
+ return -1;
+}
+
+static void pnv_xive2_ic_lsi_write(void *opaque, hwaddr offset,
+ uint64_t val, unsigned size)
+{
+ PnvXive2 *xive = PNV_XIVE2(opaque);
+
+ xive2_error(xive, "LSI: invalid write @%"HWADDR_PRIx, offset);
+}
+
+static const MemoryRegionOps pnv_xive2_ic_lsi_ops = {
+ .read = pnv_xive2_ic_lsi_read,
+ .write = pnv_xive2_ic_lsi_write,
+ .endianness = DEVICE_BIG_ENDIAN,
+ .valid = {
+ .min_access_size = 8,
+ .max_access_size = 8,
+ },
+ .impl = {
+ .min_access_size = 8,
+ .max_access_size = 8,
+ },
+};
+
+/*
+ * Sync MMIO page (write only)
+ */
+#define PNV_XIVE2_SYNC_IPI 0x000
+#define PNV_XIVE2_SYNC_HW 0x080
+#define PNV_XIVE2_SYNC_NxC 0x100
+#define PNV_XIVE2_SYNC_INT 0x180
+#define PNV_XIVE2_SYNC_OS_ESC 0x200
+#define PNV_XIVE2_SYNC_POOL_ESC 0x280
+#define PNV_XIVE2_SYNC_HARD_ESC 0x300
+
+static uint64_t pnv_xive2_ic_sync_read(void *opaque, hwaddr offset,
+ unsigned size)
+{
+ PnvXive2 *xive = PNV_XIVE2(opaque);
+
+ /* loads are invalid */
+ xive2_error(xive, "SYNC: invalid read @%"HWADDR_PRIx, offset);
+ return -1;
+}
+
+static void pnv_xive2_ic_sync_write(void *opaque, hwaddr offset,
+ uint64_t val, unsigned size)
+{
+ PnvXive2 *xive = PNV_XIVE2(opaque);
+
+ switch (offset) {
+ case PNV_XIVE2_SYNC_IPI:
+ case PNV_XIVE2_SYNC_HW:
+ case PNV_XIVE2_SYNC_NxC:
+ case PNV_XIVE2_SYNC_INT:
+ case PNV_XIVE2_SYNC_OS_ESC:
+ case PNV_XIVE2_SYNC_POOL_ESC:
+ case PNV_XIVE2_SYNC_HARD_ESC:
+ break;
+ default:
+ xive2_error(xive, "SYNC: invalid write @%"HWADDR_PRIx, offset);
+ }
+}
+
+static const MemoryRegionOps pnv_xive2_ic_sync_ops = {
+ .read = pnv_xive2_ic_sync_read,
+ .write = pnv_xive2_ic_sync_write,
+ .endianness = DEVICE_BIG_ENDIAN,
+ .valid = {
+ .min_access_size = 8,
+ .max_access_size = 8,
+ },
+ .impl = {
+ .min_access_size = 8,
+ .max_access_size = 8,
+ },
+};
+
+/*
+ * When the TM direct pages of the IC controller are accessed, the
+ * target HW thread is deduced from the page offset.
+ */
+static XiveTCTX *pnv_xive2_get_indirect_tctx(PnvXive2 *xive, uint32_t pir)
+{
+ PnvChip *chip = xive->chip;
+ PowerPCCPU *cpu = NULL;
+
+ cpu = pnv_chip_find_cpu(chip, pir);
+ if (!cpu) {
+ xive2_error(xive, "IC: invalid PIR %x for indirect access", pir);
+ return NULL;
+ }
+
+ if (!pnv_xive2_is_cpu_enabled(xive, cpu)) {
+ xive2_error(xive, "IC: CPU %x is not enabled", pir);
+ }
+
+ return XIVE_TCTX(pnv_cpu_state(cpu)->intc);
+}
+
+static uint64_t pnv_xive2_ic_tm_indirect_read(void *opaque, hwaddr offset,
+ unsigned size)
+{
+ PnvXive2 *xive = PNV_XIVE2(opaque);
+ uint32_t pir = offset >> xive->ic_shift;
+ XiveTCTX *tctx = pnv_xive2_get_indirect_tctx(xive, pir);
+ uint64_t val = -1;
+
+ if (tctx) {
+ val = xive_tctx_tm_read(NULL, tctx, offset, size);
+ }
+
+ return val;
+}
+
+static void pnv_xive2_ic_tm_indirect_write(void *opaque, hwaddr offset,
+ uint64_t val, unsigned size)
+{
+ PnvXive2 *xive = PNV_XIVE2(opaque);
+ uint32_t pir = offset >> xive->ic_shift;
+ XiveTCTX *tctx = pnv_xive2_get_indirect_tctx(xive, pir);
+
+ if (tctx) {
+ xive_tctx_tm_write(NULL, tctx, offset, val, size);
+ }
+}
+
+static const MemoryRegionOps pnv_xive2_ic_tm_indirect_ops = {
+ .read = pnv_xive2_ic_tm_indirect_read,
+ .write = pnv_xive2_ic_tm_indirect_write,
+ .endianness = DEVICE_BIG_ENDIAN,
+ .valid = {
+ .min_access_size = 8,
+ .max_access_size = 8,
+ },
+ .impl = {
+ .min_access_size = 8,
+ .max_access_size = 8,
+ },
+};
+
+/*
+ * TIMA ops
+ */
+
+static void pnv_xive2_tm_write(void *opaque, hwaddr offset,
+ uint64_t value, unsigned size)
+{
+ PowerPCCPU *cpu = POWERPC_CPU(current_cpu);
+ PnvXive2 *xive = pnv_xive2_tm_get_xive(cpu);
+ XiveTCTX *tctx = XIVE_TCTX(pnv_cpu_state(cpu)->intc);
+
+ /* Other TM ops are the same as XIVE1 */
+ xive_tctx_tm_write(XIVE_PRESENTER(xive), tctx, offset, value, size);
+}
+
+static uint64_t pnv_xive2_tm_read(void *opaque, hwaddr offset, unsigned size)
+{
+ PowerPCCPU *cpu = POWERPC_CPU(current_cpu);
+ PnvXive2 *xive = pnv_xive2_tm_get_xive(cpu);
+ XiveTCTX *tctx = XIVE_TCTX(pnv_cpu_state(cpu)->intc);
+
+ /* Other TM ops are the same as XIVE1 */
+ return xive_tctx_tm_read(XIVE_PRESENTER(xive), tctx, offset, size);
+}
+
+static const MemoryRegionOps pnv_xive2_tm_ops = {
+ .read = pnv_xive2_tm_read,
+ .write = pnv_xive2_tm_write,
+ .endianness = DEVICE_BIG_ENDIAN,
+ .valid = {
+ .min_access_size = 1,
+ .max_access_size = 8,
+ },
+ .impl = {
+ .min_access_size = 1,
+ .max_access_size = 8,
+ },
+};
+
+static uint64_t pnv_xive2_nvc_read(void *opaque, hwaddr offset,
+ unsigned size)
+{
+ PnvXive2 *xive = PNV_XIVE2(opaque);
+
+ xive2_error(xive, "NVC: invalid read @%"HWADDR_PRIx, offset);
+ return -1;
+}
+
+static void pnv_xive2_nvc_write(void *opaque, hwaddr offset,
+ uint64_t val, unsigned size)
+{
+ PnvXive2 *xive = PNV_XIVE2(opaque);
+
+ xive2_error(xive, "NVC: invalid write @%"HWADDR_PRIx, offset);
+}
+
+static const MemoryRegionOps pnv_xive2_nvc_ops = {
+ .read = pnv_xive2_nvc_read,
+ .write = pnv_xive2_nvc_write,
+ .endianness = DEVICE_BIG_ENDIAN,
+ .valid = {
+ .min_access_size = 8,
+ .max_access_size = 8,
+ },
+ .impl = {
+ .min_access_size = 8,
+ .max_access_size = 8,
+ },
+};
+
+static uint64_t pnv_xive2_nvpg_read(void *opaque, hwaddr offset,
+ unsigned size)
+{
+ PnvXive2 *xive = PNV_XIVE2(opaque);
+
+ xive2_error(xive, "NVPG: invalid read @%"HWADDR_PRIx, offset);
+ return -1;
+}
+
+static void pnv_xive2_nvpg_write(void *opaque, hwaddr offset,
+ uint64_t val, unsigned size)
+{
+ PnvXive2 *xive = PNV_XIVE2(opaque);
+
+ xive2_error(xive, "NVPG: invalid write @%"HWADDR_PRIx, offset);
+}
+
+static const MemoryRegionOps pnv_xive2_nvpg_ops = {
+ .read = pnv_xive2_nvpg_read,
+ .write = pnv_xive2_nvpg_write,
+ .endianness = DEVICE_BIG_ENDIAN,
+ .valid = {
+ .min_access_size = 8,
+ .max_access_size = 8,
+ },
+ .impl = {
+ .min_access_size = 8,
+ .max_access_size = 8,
+ },
+};
+
+/*
+ * POWER10 default capabilities: 0x2000120076f00000
+ */
+#define PNV_XIVE2_CAPABILITIES 0x2000120076f00000
+
+/*
+ * POWER10 default configuration: 0x0030000033000000
+ *
+ * 8bits thread id was dropped for P10
+ */
+#define PNV_XIVE2_CONFIGURATION 0x0030000033000000
+
+static void pnv_xive2_reset(void *dev)
+{
+ PnvXive2 *xive = PNV_XIVE2(dev);
+ XiveSource *xsrc = &xive->ipi_source;
+ Xive2EndSource *end_xsrc = &xive->end_source;
+
+ xive->cq_regs[CQ_XIVE_CAP >> 3] = xive->capabilities;
+ xive->cq_regs[CQ_XIVE_CFG >> 3] = xive->config;
+
+ /* HW hardwires the #Topology of the chip in the block field */
+ xive->cq_regs[CQ_XIVE_CFG >> 3] |=
+ SETFIELD(CQ_XIVE_CFG_HYP_HARD_BLOCK_ID, 0ull, xive->chip->chip_id);
+
+ /* Set default page size to 64k */
+ xive->ic_shift = xive->esb_shift = xive->end_shift = 16;
+ xive->nvc_shift = xive->nvpg_shift = xive->tm_shift = 16;
+
+ /* Clear source MMIOs */
+ if (memory_region_is_mapped(&xsrc->esb_mmio)) {
+ memory_region_del_subregion(&xive->esb_mmio, &xsrc->esb_mmio);
+ }
+
+ if (memory_region_is_mapped(&end_xsrc->esb_mmio)) {
+ memory_region_del_subregion(&xive->end_mmio, &end_xsrc->esb_mmio);
+ }
+}
+
+/*
+ * Maximum number of IRQs and ENDs supported by HW. Will be tuned by
+ * software.
+ */
+#define PNV_XIVE2_NR_IRQS (PNV10_XIVE2_ESB_SIZE / (1ull << XIVE_ESB_64K_2PAGE))
+#define PNV_XIVE2_NR_ENDS (PNV10_XIVE2_END_SIZE / (1ull << XIVE_ESB_64K_2PAGE))
+
+static void pnv_xive2_realize(DeviceState *dev, Error **errp)
+{
+ PnvXive2 *xive = PNV_XIVE2(dev);
+ PnvXive2Class *pxc = PNV_XIVE2_GET_CLASS(dev);
+ XiveSource *xsrc = &xive->ipi_source;
+ Xive2EndSource *end_xsrc = &xive->end_source;
+ Error *local_err = NULL;
+ int i;
+
+ pxc->parent_realize(dev, &local_err);
+ if (local_err) {
+ error_propagate(errp, local_err);
+ return;
+ }
+
+ assert(xive->chip);
+
+ /*
+ * The XiveSource and Xive2EndSource objects are realized with the
+ * maximum allowed HW configuration. The ESB MMIO regions will be
+ * resized dynamically when the controller is configured by the FW
+ * to limit accesses to resources not provisioned.
+ */
+ object_property_set_int(OBJECT(xsrc), "flags", XIVE_SRC_STORE_EOI,
+ &error_fatal);
+ object_property_set_int(OBJECT(xsrc), "nr-irqs", PNV_XIVE2_NR_IRQS,
+ &error_fatal);
+ object_property_set_link(OBJECT(xsrc), "xive", OBJECT(xive),
+ &error_fatal);
+ qdev_realize(DEVICE(xsrc), NULL, &local_err);
+ if (local_err) {
+ error_propagate(errp, local_err);
+ return;
+ }
+
+ object_property_set_int(OBJECT(end_xsrc), "nr-ends", PNV_XIVE2_NR_ENDS,
+ &error_fatal);
+ object_property_set_link(OBJECT(end_xsrc), "xive", OBJECT(xive),
+ &error_abort);
+ qdev_realize(DEVICE(end_xsrc), NULL, &local_err);
+ if (local_err) {
+ error_propagate(errp, local_err);
+ return;
+ }
+
+ /* XSCOM region, used for initial configuration of the BARs */
+ memory_region_init_io(&xive->xscom_regs, OBJECT(dev),
+ &pnv_xive2_xscom_ops, xive, "xscom-xive",
+ PNV10_XSCOM_XIVE2_SIZE << 3);
+
+ /* Interrupt controller MMIO regions */
+ xive->ic_shift = 16;
+ memory_region_init(&xive->ic_mmio, OBJECT(dev), "xive-ic",
+ PNV10_XIVE2_IC_SIZE);
+
+ for (i = 0; i < ARRAY_SIZE(xive->ic_mmios); i++) {
+ memory_region_init_io(&xive->ic_mmios[i], OBJECT(dev),
+ pnv_xive2_ic_regions[i].ops, xive,
+ pnv_xive2_ic_regions[i].name,
+ pnv_xive2_ic_regions[i].pgsize << xive->ic_shift);
+ }
+
+ /*
+ * VC MMIO regions.
+ */
+ xive->esb_shift = 16;
+ xive->end_shift = 16;
+ memory_region_init(&xive->esb_mmio, OBJECT(xive), "xive-esb",
+ PNV10_XIVE2_ESB_SIZE);
+ memory_region_init(&xive->end_mmio, OBJECT(xive), "xive-end",
+ PNV10_XIVE2_END_SIZE);
+
+ /* Presenter Controller MMIO region (not modeled) */
+ xive->nvc_shift = 16;
+ xive->nvpg_shift = 16;
+ memory_region_init_io(&xive->nvc_mmio, OBJECT(dev),
+ &pnv_xive2_nvc_ops, xive,
+ "xive-nvc", PNV10_XIVE2_NVC_SIZE);
+
+ memory_region_init_io(&xive->nvpg_mmio, OBJECT(dev),
+ &pnv_xive2_nvpg_ops, xive,
+ "xive-nvpg", PNV10_XIVE2_NVPG_SIZE);
+
+ /* Thread Interrupt Management Area (Direct) */
+ xive->tm_shift = 16;
+ memory_region_init_io(&xive->tm_mmio, OBJECT(dev), &pnv_xive2_tm_ops,
+ xive, "xive-tima", PNV10_XIVE2_TM_SIZE);
+
+ qemu_register_reset(pnv_xive2_reset, dev);
+}
+
+static Property pnv_xive2_properties[] = {
+ DEFINE_PROP_UINT64("ic-bar", PnvXive2, ic_base, 0),
+ DEFINE_PROP_UINT64("esb-bar", PnvXive2, esb_base, 0),
+ DEFINE_PROP_UINT64("end-bar", PnvXive2, end_base, 0),
+ DEFINE_PROP_UINT64("nvc-bar", PnvXive2, nvc_base, 0),
+ DEFINE_PROP_UINT64("nvpg-bar", PnvXive2, nvpg_base, 0),
+ DEFINE_PROP_UINT64("tm-bar", PnvXive2, tm_base, 0),
+ DEFINE_PROP_UINT64("capabilities", PnvXive2, capabilities,
+ PNV_XIVE2_CAPABILITIES),
+ DEFINE_PROP_UINT64("config", PnvXive2, config,
+ PNV_XIVE2_CONFIGURATION),
+ DEFINE_PROP_LINK("chip", PnvXive2, chip, TYPE_PNV_CHIP, PnvChip *),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void pnv_xive2_instance_init(Object *obj)
+{
+ PnvXive2 *xive = PNV_XIVE2(obj);
+
+ object_initialize_child(obj, "ipi_source", &xive->ipi_source,
+ TYPE_XIVE_SOURCE);
+ object_initialize_child(obj, "end_source", &xive->end_source,
+ TYPE_XIVE2_END_SOURCE);
+}
+
+static int pnv_xive2_dt_xscom(PnvXScomInterface *dev, void *fdt,
+ int xscom_offset)
+{
+ const char compat_p10[] = "ibm,power10-xive-x";
+ char *name;
+ int offset;
+ uint32_t reg[] = {
+ cpu_to_be32(PNV10_XSCOM_XIVE2_BASE),
+ cpu_to_be32(PNV10_XSCOM_XIVE2_SIZE)
+ };
+
+ name = g_strdup_printf("xive@%x", PNV10_XSCOM_XIVE2_BASE);
+ offset = fdt_add_subnode(fdt, xscom_offset, name);
+ _FDT(offset);
+ g_free(name);
+
+ _FDT((fdt_setprop(fdt, offset, "reg", reg, sizeof(reg))));
+ _FDT(fdt_setprop(fdt, offset, "compatible", compat_p10,
+ sizeof(compat_p10)));
+ return 0;
+}
+
+static void pnv_xive2_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ PnvXScomInterfaceClass *xdc = PNV_XSCOM_INTERFACE_CLASS(klass);
+ Xive2RouterClass *xrc = XIVE2_ROUTER_CLASS(klass);
+ XiveNotifierClass *xnc = XIVE_NOTIFIER_CLASS(klass);
+ XivePresenterClass *xpc = XIVE_PRESENTER_CLASS(klass);
+ PnvXive2Class *pxc = PNV_XIVE2_CLASS(klass);
+
+ xdc->dt_xscom = pnv_xive2_dt_xscom;
+
+ dc->desc = "PowerNV XIVE2 Interrupt Controller (POWER10)";
+ device_class_set_parent_realize(dc, pnv_xive2_realize,
+ &pxc->parent_realize);
+ device_class_set_props(dc, pnv_xive2_properties);
+
+ xrc->get_eas = pnv_xive2_get_eas;
+ xrc->get_end = pnv_xive2_get_end;
+ xrc->write_end = pnv_xive2_write_end;
+ xrc->get_nvp = pnv_xive2_get_nvp;
+ xrc->write_nvp = pnv_xive2_write_nvp;
+ xrc->get_block_id = pnv_xive2_get_block_id;
+
+ xnc->notify = pnv_xive2_notify;
+
+ xpc->match_nvt = pnv_xive2_match_nvt;
+};
+
+static const TypeInfo pnv_xive2_info = {
+ .name = TYPE_PNV_XIVE2,
+ .parent = TYPE_XIVE2_ROUTER,
+ .instance_init = pnv_xive2_instance_init,
+ .instance_size = sizeof(PnvXive2),
+ .class_init = pnv_xive2_class_init,
+ .class_size = sizeof(PnvXive2Class),
+ .interfaces = (InterfaceInfo[]) {
+ { TYPE_PNV_XSCOM_INTERFACE },
+ { }
+ }
+};
+
+static void pnv_xive2_register_types(void)
+{
+ type_register_static(&pnv_xive2_info);
+}
+
+type_init(pnv_xive2_register_types)
+
+static void xive2_nvp_pic_print_info(Xive2Nvp *nvp, uint32_t nvp_idx,
+ Monitor *mon)
+{
+ uint8_t eq_blk = xive_get_field32(NVP2_W5_VP_END_BLOCK, nvp->w5);
+ uint32_t eq_idx = xive_get_field32(NVP2_W5_VP_END_INDEX, nvp->w5);
+
+ if (!xive2_nvp_is_valid(nvp)) {
+ return;
+ }
+
+ monitor_printf(mon, " %08x end:%02x/%04x IPB:%02x\n",
+ nvp_idx, eq_blk, eq_idx,
+ xive_get_field32(NVP2_W2_IPB, nvp->w2));
+}
+
+/*
+ * If the table is direct, we can compute the number of PQ entries
+ * provisioned by FW.
+ */
+static uint32_t pnv_xive2_nr_esbs(PnvXive2 *xive)
+{
+ uint8_t blk = pnv_xive2_block_id(xive);
+ uint64_t vsd = xive->vsds[VST_ESB][blk];
+ uint64_t vst_tsize = 1ull << (GETFIELD(VSD_TSIZE, vsd) + 12);
+
+ return VSD_INDIRECT & vsd ? 0 : vst_tsize * SBE_PER_BYTE;
+}
+
+/*
+ * Compute the number of entries per indirect subpage.
+ */
+static uint64_t pnv_xive2_vst_per_subpage(PnvXive2 *xive, uint32_t type)
+{
+ uint8_t blk = pnv_xive2_block_id(xive);
+ uint64_t vsd = xive->vsds[type][blk];
+ const XiveVstInfo *info = &vst_infos[type];
+ uint64_t vsd_addr;
+ uint32_t page_shift;
+
+ /* For direct tables, fake a valid value */
+ if (!(VSD_INDIRECT & vsd)) {
+ return 1;
+ }
+
+ /* Get the page size of the indirect table. */
+ vsd_addr = vsd & VSD_ADDRESS_MASK;
+ ldq_be_dma(&address_space_memory, vsd_addr, &vsd, MEMTXATTRS_UNSPECIFIED);
+
+ if (!(vsd & VSD_ADDRESS_MASK)) {
+#ifdef XIVE2_DEBUG
+ xive2_error(xive, "VST: invalid %s entry!?", info->name);
+#endif
+ return 0;
+ }
+
+ page_shift = GETFIELD(VSD_TSIZE, vsd) + 12;
+
+ if (!pnv_xive2_vst_page_size_allowed(page_shift)) {
+ xive2_error(xive, "VST: invalid %s page shift %d", info->name,
+ page_shift);
+ return 0;
+ }
+
+ return (1ull << page_shift) / info->size;
+}
+
+void pnv_xive2_pic_print_info(PnvXive2 *xive, Monitor *mon)
+{
+ Xive2Router *xrtr = XIVE2_ROUTER(xive);
+ uint8_t blk = pnv_xive2_block_id(xive);
+ uint8_t chip_id = xive->chip->chip_id;
+ uint32_t srcno0 = XIVE_EAS(blk, 0);
+ uint32_t nr_esbs = pnv_xive2_nr_esbs(xive);
+ Xive2Eas eas;
+ Xive2End end;
+ Xive2Nvp nvp;
+ int i;
+ uint64_t xive_nvp_per_subpage;
+
+ monitor_printf(mon, "XIVE[%x] Source %08x .. %08x\n", blk, srcno0,
+ srcno0 + nr_esbs - 1);
+ xive_source_pic_print_info(&xive->ipi_source, srcno0, mon);
+
+ monitor_printf(mon, "XIVE[%x] EAT %08x .. %08x\n", blk, srcno0,
+ srcno0 + nr_esbs - 1);
+ for (i = 0; i < nr_esbs; i++) {
+ if (xive2_router_get_eas(xrtr, blk, i, &eas)) {
+ break;
+ }
+ if (!xive2_eas_is_masked(&eas)) {
+ xive2_eas_pic_print_info(&eas, i, mon);
+ }
+ }
+
+ monitor_printf(mon, "XIVE[%x] #%d END Escalation EAT\n", chip_id, blk);
+ i = 0;
+ while (!xive2_router_get_end(xrtr, blk, i, &end)) {
+ xive2_end_eas_pic_print_info(&end, i++, mon);
+ }
+
+ monitor_printf(mon, "XIVE[%x] #%d ENDT\n", chip_id, blk);
+ i = 0;
+ while (!xive2_router_get_end(xrtr, blk, i, &end)) {
+ xive2_end_pic_print_info(&end, i++, mon);
+ }
+
+ monitor_printf(mon, "XIVE[%x] #%d NVPT %08x .. %08x\n", chip_id, blk,
+ 0, XIVE2_NVP_COUNT - 1);
+ xive_nvp_per_subpage = pnv_xive2_vst_per_subpage(xive, VST_NVP);
+ for (i = 0; i < XIVE2_NVP_COUNT; i += xive_nvp_per_subpage) {
+ while (!xive2_router_get_nvp(xrtr, blk, i, &nvp)) {
+ xive2_nvp_pic_print_info(&nvp, i++, mon);
+ }
+ }
+}
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 441bf958cadb..f486fdfb5c72 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -725,6 +725,7 @@ static void pnv_chip_power10_pic_print_info(PnvChip *chip, Monitor *mon)
{
Pnv10Chip *chip10 = PNV10_CHIP(chip);
+ pnv_xive2_pic_print_info(&chip10->xive, mon);
pnv_psi_pic_print_info(&chip10->psi, mon);
}
@@ -1047,27 +1048,45 @@ static void pnv_chip_power9_intc_print_info(PnvChip *chip, PowerPCCPU *cpu,
static void pnv_chip_power10_intc_create(PnvChip *chip, PowerPCCPU *cpu,
Error **errp)
{
+ Pnv10Chip *chip10 = PNV10_CHIP(chip);
+ Error *local_err = NULL;
+ Object *obj;
PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
- /* Will be defined when the interrupt controller is */
- pnv_cpu->intc = NULL;
+ /*
+ * The core creates its interrupt presenter but the XIVE2 interrupt
+ * controller object is initialized afterwards. Hopefully, it's
+ * only used at runtime.
+ */
+ obj = xive_tctx_create(OBJECT(cpu), XIVE_PRESENTER(&chip10->xive),
+ &local_err);
+ if (local_err) {
+ error_propagate(errp, local_err);
+ return;
+ }
+
+ pnv_cpu->intc = obj;
}
static void pnv_chip_power10_intc_reset(PnvChip *chip, PowerPCCPU *cpu)
{
- ;
+ PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
+
+ xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc));
}
static void pnv_chip_power10_intc_destroy(PnvChip *chip, PowerPCCPU *cpu)
{
PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
+ xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc));
pnv_cpu->intc = NULL;
}
static void pnv_chip_power10_intc_print_info(PnvChip *chip, PowerPCCPU *cpu,
Monitor *mon)
{
+ xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), mon);
}
/*
@@ -1558,6 +1577,9 @@ static void pnv_chip_power10_instance_init(Object *obj)
{
Pnv10Chip *chip10 = PNV10_CHIP(obj);
+ object_initialize_child(obj, "xive", &chip10->xive, TYPE_PNV_XIVE2);
+ object_property_add_alias(obj, "xive-fabric", OBJECT(&chip10->xive),
+ "xive-fabric");
object_initialize_child(obj, "psi", &chip10->psi, TYPE_PNV10_PSI);
object_initialize_child(obj, "lpc", &chip10->lpc, TYPE_PNV10_LPC);
}
@@ -1583,6 +1605,27 @@ static void pnv_chip_power10_realize(DeviceState *dev, Error **errp)
return;
}
+ /* XIVE2 interrupt controller (POWER10) */
+ object_property_set_int(OBJECT(&chip10->xive), "ic-bar",
+ PNV10_XIVE2_IC_BASE(chip), &error_fatal);
+ object_property_set_int(OBJECT(&chip10->xive), "esb-bar",
+ PNV10_XIVE2_ESB_BASE(chip), &error_fatal);
+ object_property_set_int(OBJECT(&chip10->xive), "end-bar",
+ PNV10_XIVE2_END_BASE(chip), &error_fatal);
+ object_property_set_int(OBJECT(&chip10->xive), "nvpg-bar",
+ PNV10_XIVE2_NVPG_BASE(chip), &error_fatal);
+ object_property_set_int(OBJECT(&chip10->xive), "nvc-bar",
+ PNV10_XIVE2_NVC_BASE(chip), &error_fatal);
+ object_property_set_int(OBJECT(&chip10->xive), "tm-bar",
+ PNV10_XIVE2_TM_BASE(chip), &error_fatal);
+ object_property_set_link(OBJECT(&chip10->xive), "chip", OBJECT(chip),
+ &error_abort);
+ if (!sysbus_realize(SYS_BUS_DEVICE(&chip10->xive), errp)) {
+ return;
+ }
+ pnv_xscom_add_subregion(chip, PNV10_XSCOM_XIVE2_BASE,
+ &chip10->xive.xscom_regs);
+
/* Processor Service Interface (PSI) Host Bridge */
object_property_set_int(OBJECT(&chip10->psi), "bar",
PNV10_PSIHB_BASE(chip), &error_fatal);
@@ -1927,6 +1970,35 @@ static int pnv_match_nvt(XiveFabric *xfb, uint8_t format,
return total_count;
}
+static int pnv10_xive_match_nvt(XiveFabric *xfb, uint8_t format,
+ uint8_t nvt_blk, uint32_t nvt_idx,
+ bool cam_ignore, uint8_t priority,
+ uint32_t logic_serv,
+ XiveTCTXMatch *match)
+{
+ PnvMachineState *pnv = PNV_MACHINE(xfb);
+ int total_count = 0;
+ int i;
+
+ for (i = 0; i < pnv->num_chips; i++) {
+ Pnv10Chip *chip10 = PNV10_CHIP(pnv->chips[i]);
+ XivePresenter *xptr = XIVE_PRESENTER(&chip10->xive);
+ XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr);
+ int count;
+
+ count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore,
+ priority, logic_serv, match);
+
+ if (count < 0) {
+ return count;
+ }
+
+ total_count += count;
+ }
+
+ return total_count;
+}
+
static void pnv_machine_power8_class_init(ObjectClass *oc, void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
@@ -1971,6 +2043,7 @@ static void pnv_machine_power10_class_init(ObjectClass *oc, void *data)
{
MachineClass *mc = MACHINE_CLASS(oc);
PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc);
+ XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc);
static const char compat[] = "qemu,powernv10\0ibm,powernv";
mc->desc = "IBM PowerNV (Non-Virtualized) POWER10";
@@ -1979,6 +2052,8 @@ static void pnv_machine_power10_class_init(ObjectClass *oc, void *data)
pmc->compat = compat;
pmc->compat_size = sizeof(compat);
pmc->dt_power_mgt = pnv_dt_power_mgt;
+
+ xfc->match_nvt = pnv10_xive_match_nvt;
}
static bool pnv_machine_get_hb(Object *obj, Error **errp)
@@ -2090,6 +2165,10 @@ static const TypeInfo types[] = {
.name = MACHINE_TYPE_NAME("powernv10"),
.parent = TYPE_PNV_MACHINE,
.class_init = pnv_machine_power10_class_init,
+ .interfaces = (InterfaceInfo[]) {
+ { TYPE_XIVE_FABRIC },
+ { },
+ },
},
{
.name = MACHINE_TYPE_NAME("powernv9"),
diff --git a/hw/intc/meson.build b/hw/intc/meson.build
index 128cebe0a32b..d953197413f0 100644
--- a/hw/intc/meson.build
+++ b/hw/intc/meson.build
@@ -42,7 +42,7 @@ specific_ss.add(when: 'CONFIG_OMAP', if_true: files('omap_intc.c'))
specific_ss.add(when: 'CONFIG_OMPIC', if_true: files('ompic.c'))
specific_ss.add(when: ['CONFIG_KVM', 'CONFIG_OPENPIC'],
if_true: files('openpic_kvm.c'))
-specific_ss.add(when: 'CONFIG_POWERNV', if_true: files('xics_pnv.c', 'pnv_xive.c'))
+specific_ss.add(when: 'CONFIG_POWERNV', if_true: files('xics_pnv.c', 'pnv_xive.c', 'pnv_xive2.c'))
specific_ss.add(when: 'CONFIG_PPC_UIC', if_true: files('ppc-uic.c'))
specific_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_ic.c', 'bcm2836_control.c'))
specific_ss.add(when: 'CONFIG_RX_ICU', if_true: files('rx_icu.c'))
--
2.34.1
^ permalink raw reply related [flat|nested] 89+ messages in thread* [PULL 59/87] ppc/pnv: Add a OCC model for POWER10
2022-03-02 11:06 [PULL 00/87] ppc queue Cédric Le Goater
` (57 preceding siblings ...)
2022-03-02 11:07 ` [PULL 58/87] ppc/pnv: Add a XIVE2 controller to the POWER10 chip Cédric Le Goater
@ 2022-03-02 11:07 ` Cédric Le Goater
2022-03-02 11:07 ` [PULL 60/87] ppc/pnv: Add POWER10 quads Cédric Le Goater
` (28 subsequent siblings)
87 siblings, 0 replies; 89+ messages in thread
From: Cédric Le Goater @ 2022-03-02 11:07 UTC (permalink / raw)
To: qemu-ppc, qemu-devel; +Cc: Peter Maydell, Cédric Le Goater, David Gibson
Our OCC model is very mininal and POWER10 can simply reuse the OCC
model we introduced for POWER9.
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
include/hw/ppc/pnv.h | 1 +
include/hw/ppc/pnv_occ.h | 2 ++
include/hw/ppc/pnv_xscom.h | 3 +++
hw/ppc/pnv.c | 10 ++++++++++
hw/ppc/pnv_occ.c | 16 ++++++++++++++++
5 files changed, 32 insertions(+)
diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h
index 6b3457b4495d..21e69b0fc187 100644
--- a/include/hw/ppc/pnv.h
+++ b/include/hw/ppc/pnv.h
@@ -128,6 +128,7 @@ struct Pnv10Chip {
PnvXive2 xive;
Pnv9Psi psi;
PnvLpcController lpc;
+ PnvOCC occ;
};
#define PNV10_PIR2FUSEDCORE(pir) (((pir) >> 3) & 0xf)
diff --git a/include/hw/ppc/pnv_occ.h b/include/hw/ppc/pnv_occ.h
index b78185aecaf2..f982ba002481 100644
--- a/include/hw/ppc/pnv_occ.h
+++ b/include/hw/ppc/pnv_occ.h
@@ -32,6 +32,8 @@ DECLARE_INSTANCE_CHECKER(PnvOCC, PNV8_OCC,
#define TYPE_PNV9_OCC TYPE_PNV_OCC "-POWER9"
DECLARE_INSTANCE_CHECKER(PnvOCC, PNV9_OCC,
TYPE_PNV9_OCC)
+#define TYPE_PNV10_OCC TYPE_PNV_OCC "-POWER10"
+DECLARE_INSTANCE_CHECKER(PnvOCC, PNV10_OCC, TYPE_PNV10_OCC)
#define PNV_OCC_SENSOR_DATA_BLOCK_OFFSET 0x00580000
#define PNV_OCC_SENSOR_DATA_BLOCK_SIZE 0x00025800
diff --git a/include/hw/ppc/pnv_xscom.h b/include/hw/ppc/pnv_xscom.h
index 188da874a4b0..151df15378d1 100644
--- a/include/hw/ppc/pnv_xscom.h
+++ b/include/hw/ppc/pnv_xscom.h
@@ -131,6 +131,9 @@ struct PnvXScomInterfaceClass {
#define PNV10_XSCOM_PSIHB_BASE 0x3011D00
#define PNV10_XSCOM_PSIHB_SIZE 0x100
+#define PNV10_XSCOM_OCC_BASE PNV9_XSCOM_OCC_BASE
+#define PNV10_XSCOM_OCC_SIZE PNV9_XSCOM_OCC_SIZE
+
#define PNV10_XSCOM_XIVE2_BASE 0x2010800
#define PNV10_XSCOM_XIVE2_SIZE 0x400
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index f486fdfb5c72..2431a7a5a38a 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -1582,6 +1582,7 @@ static void pnv_chip_power10_instance_init(Object *obj)
"xive-fabric");
object_initialize_child(obj, "psi", &chip10->psi, TYPE_PNV10_PSI);
object_initialize_child(obj, "lpc", &chip10->lpc, TYPE_PNV10_LPC);
+ object_initialize_child(obj, "occ", &chip10->occ, TYPE_PNV10_OCC);
}
static void pnv_chip_power10_realize(DeviceState *dev, Error **errp)
@@ -1647,6 +1648,15 @@ static void pnv_chip_power10_realize(DeviceState *dev, Error **errp)
chip->fw_mr = &chip10->lpc.isa_fw;
chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0",
(uint64_t) PNV10_LPCM_BASE(chip));
+
+ /* Create the simplified OCC model */
+ object_property_set_link(OBJECT(&chip10->occ), "psi", OBJECT(&chip10->psi),
+ &error_abort);
+ if (!qdev_realize(DEVICE(&chip10->occ), NULL, errp)) {
+ return;
+ }
+ pnv_xscom_add_subregion(chip, PNV10_XSCOM_OCC_BASE,
+ &chip10->occ.xscom_regs);
}
static uint32_t pnv_chip_power10_xscom_pcba(PnvChip *chip, uint64_t addr)
diff --git a/hw/ppc/pnv_occ.c b/hw/ppc/pnv_occ.c
index 5a716c256edc..4ed66f5e1fcc 100644
--- a/hw/ppc/pnv_occ.c
+++ b/hw/ppc/pnv_occ.c
@@ -236,7 +236,9 @@ static const MemoryRegionOps pnv_occ_power9_xscom_ops = {
static void pnv_occ_power9_class_init(ObjectClass *klass, void *data)
{
PnvOCCClass *poc = PNV_OCC_CLASS(klass);
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ dc->desc = "PowerNV OCC Controller (POWER9)";
poc->xscom_size = PNV9_XSCOM_OCC_SIZE;
poc->xscom_ops = &pnv_occ_power9_xscom_ops;
poc->psi_irq = PSIHB9_IRQ_OCC;
@@ -249,6 +251,19 @@ static const TypeInfo pnv_occ_power9_type_info = {
.class_init = pnv_occ_power9_class_init,
};
+static void pnv_occ_power10_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->desc = "PowerNV OCC Controller (POWER10)";
+}
+
+static const TypeInfo pnv_occ_power10_type_info = {
+ .name = TYPE_PNV10_OCC,
+ .parent = TYPE_PNV9_OCC,
+ .class_init = pnv_occ_power10_class_init,
+};
+
static void pnv_occ_realize(DeviceState *dev, Error **errp)
{
PnvOCC *occ = PNV_OCC(dev);
@@ -297,6 +312,7 @@ static void pnv_occ_register_types(void)
type_register_static(&pnv_occ_type_info);
type_register_static(&pnv_occ_power8_type_info);
type_register_static(&pnv_occ_power9_type_info);
+ type_register_static(&pnv_occ_power10_type_info);
}
type_init(pnv_occ_register_types);
--
2.34.1
^ permalink raw reply related [flat|nested] 89+ messages in thread* [PULL 60/87] ppc/pnv: Add POWER10 quads
2022-03-02 11:06 [PULL 00/87] ppc queue Cédric Le Goater
` (58 preceding siblings ...)
2022-03-02 11:07 ` [PULL 59/87] ppc/pnv: Add a OCC model for POWER10 Cédric Le Goater
@ 2022-03-02 11:07 ` Cédric Le Goater
2022-03-02 11:07 ` [PULL 61/87] ppc/pnv: Add model for POWER10 PHB5 PCIe Host bridge Cédric Le Goater
` (27 subsequent siblings)
87 siblings, 0 replies; 89+ messages in thread
From: Cédric Le Goater @ 2022-03-02 11:07 UTC (permalink / raw)
To: qemu-ppc, qemu-devel; +Cc: Peter Maydell, Cédric Le Goater
and use a pnv_chip_power10_quad_realize() helper to avoid code
duplication with P9. This still needs some refinements on the XSCOM
registers handling in PnvQuad.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
include/hw/ppc/pnv.h | 3 +++
hw/ppc/pnv.c | 50 +++++++++++++++++++++++++++++++++++---------
2 files changed, 43 insertions(+), 10 deletions(-)
diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h
index 21e69b0fc187..6449fba39bfb 100644
--- a/include/hw/ppc/pnv.h
+++ b/include/hw/ppc/pnv.h
@@ -129,6 +129,9 @@ struct Pnv10Chip {
Pnv9Psi psi;
PnvLpcController lpc;
PnvOCC occ;
+
+ uint32_t nr_quads;
+ PnvQuad *quads;
};
#define PNV10_PIR2FUSEDCORE(pir) (((pir) >> 3) & 0xf)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 2431a7a5a38a..77f250b86d8f 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -1388,6 +1388,21 @@ static void pnv_chip_power9_instance_init(Object *obj)
}
}
+static void pnv_chip_quad_realize_one(PnvChip *chip, PnvQuad *eq,
+ PnvCore *pnv_core)
+{
+ char eq_name[32];
+ int core_id = CPU_CORE(pnv_core)->core_id;
+
+ snprintf(eq_name, sizeof(eq_name), "eq[%d]", core_id);
+ object_initialize_child_with_props(OBJECT(chip), eq_name, eq,
+ sizeof(*eq), TYPE_PNV_QUAD,
+ &error_fatal, NULL);
+
+ object_property_set_int(OBJECT(eq), "quad-id", core_id, &error_fatal);
+ qdev_realize(DEVICE(eq), NULL, &error_fatal);
+}
+
static void pnv_chip_quad_realize(Pnv9Chip *chip9, Error **errp)
{
PnvChip *chip = PNV_CHIP(chip9);
@@ -1397,18 +1412,9 @@ static void pnv_chip_quad_realize(Pnv9Chip *chip9, Error **errp)
chip9->quads = g_new0(PnvQuad, chip9->nr_quads);
for (i = 0; i < chip9->nr_quads; i++) {
- char eq_name[32];
PnvQuad *eq = &chip9->quads[i];
- PnvCore *pnv_core = chip->cores[i * 4];
- int core_id = CPU_CORE(pnv_core)->core_id;
-
- snprintf(eq_name, sizeof(eq_name), "eq[%d]", core_id);
- object_initialize_child_with_props(OBJECT(chip), eq_name, eq,
- sizeof(*eq), TYPE_PNV_QUAD,
- &error_fatal, NULL);
- object_property_set_int(OBJECT(eq), "quad-id", core_id, &error_fatal);
- qdev_realize(DEVICE(eq), NULL, &error_fatal);
+ pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4]);
pnv_xscom_add_subregion(chip, PNV9_XSCOM_EQ_BASE(eq->quad_id),
&eq->xscom_regs);
@@ -1585,6 +1591,24 @@ static void pnv_chip_power10_instance_init(Object *obj)
object_initialize_child(obj, "occ", &chip10->occ, TYPE_PNV10_OCC);
}
+static void pnv_chip_power10_quad_realize(Pnv10Chip *chip10, Error **errp)
+{
+ PnvChip *chip = PNV_CHIP(chip10);
+ int i;
+
+ chip10->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4);
+ chip10->quads = g_new0(PnvQuad, chip10->nr_quads);
+
+ for (i = 0; i < chip10->nr_quads; i++) {
+ PnvQuad *eq = &chip10->quads[i];
+
+ pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4]);
+
+ pnv_xscom_add_subregion(chip, PNV10_XSCOM_EQ_BASE(eq->quad_id),
+ &eq->xscom_regs);
+ }
+}
+
static void pnv_chip_power10_realize(DeviceState *dev, Error **errp)
{
PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev);
@@ -1606,6 +1630,12 @@ static void pnv_chip_power10_realize(DeviceState *dev, Error **errp)
return;
}
+ pnv_chip_power10_quad_realize(chip10, &local_err);
+ if (local_err) {
+ error_propagate(errp, local_err);
+ return;
+ }
+
/* XIVE2 interrupt controller (POWER10) */
object_property_set_int(OBJECT(&chip10->xive), "ic-bar",
PNV10_XIVE2_IC_BASE(chip), &error_fatal);
--
2.34.1
^ permalink raw reply related [flat|nested] 89+ messages in thread* [PULL 61/87] ppc/pnv: Add model for POWER10 PHB5 PCIe Host bridge
2022-03-02 11:06 [PULL 00/87] ppc queue Cédric Le Goater
` (59 preceding siblings ...)
2022-03-02 11:07 ` [PULL 60/87] ppc/pnv: Add POWER10 quads Cédric Le Goater
@ 2022-03-02 11:07 ` Cédric Le Goater
2022-03-02 11:07 ` [PULL 62/87] ppc/pnv: Add a HOMER model to POWER10 Cédric Le Goater
` (26 subsequent siblings)
87 siblings, 0 replies; 89+ messages in thread
From: Cédric Le Goater @ 2022-03-02 11:07 UTC (permalink / raw)
To: qemu-ppc, qemu-devel; +Cc: Peter Maydell, Cédric Le Goater
PHB4 and PHB5 are very similar. Use the PHB4 models with some minor
adjustements in a subclass for P10.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
include/hw/pci-host/pnv_phb4.h | 12 ++++++++
include/hw/ppc/pnv.h | 3 ++
include/hw/ppc/pnv_xscom.h | 6 ++++
hw/pci-host/pnv_phb4.c | 20 +++++++++++++
hw/pci-host/pnv_phb4_pec.c | 53 ++++++++++++++++++++++++++++++++++
hw/ppc/pnv.c | 51 ++++++++++++++++++++++++++++++++
6 files changed, 145 insertions(+)
diff --git a/include/hw/pci-host/pnv_phb4.h b/include/hw/pci-host/pnv_phb4.h
index 0c7635dec591..fbcf5bfb5585 100644
--- a/include/hw/pci-host/pnv_phb4.h
+++ b/include/hw/pci-host/pnv_phb4.h
@@ -49,6 +49,7 @@ typedef struct PnvPhb4DMASpace {
*/
#define TYPE_PNV_PHB4_ROOT_BUS "pnv-phb4-root"
#define TYPE_PNV_PHB4_ROOT_PORT "pnv-phb4-root-port"
+#define TYPE_PNV_PHB5_ROOT_PORT "pnv-phb5-root-port"
typedef struct PnvPHB4RootPort {
PCIESlot parent_obj;
@@ -206,4 +207,15 @@ struct PnvPhb4PecClass {
const char *rp_model;
};
+/*
+ * POWER10 definitions
+ */
+
+#define PNV_PHB5_VERSION 0x000000a500000001ull
+#define PNV_PHB5_DEVICE_ID 0x0652
+
+#define TYPE_PNV_PHB5_PEC "pnv-phb5-pec"
+#define PNV_PHB5_PEC(obj) \
+ OBJECT_CHECK(PnvPhb4PecState, (obj), TYPE_PNV_PHB5_PEC)
+
#endif /* PCI_HOST_PNV_PHB4_H */
diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h
index 6449fba39bfb..e5141851faed 100644
--- a/include/hw/ppc/pnv.h
+++ b/include/hw/ppc/pnv.h
@@ -132,6 +132,9 @@ struct Pnv10Chip {
uint32_t nr_quads;
PnvQuad *quads;
+
+#define PNV10_CHIP_MAX_PEC 2
+ PnvPhb4PecState pecs[PNV10_CHIP_MAX_PEC];
};
#define PNV10_PIR2FUSEDCORE(pir) (((pir) >> 3) & 0xf)
diff --git a/include/hw/ppc/pnv_xscom.h b/include/hw/ppc/pnv_xscom.h
index 151df15378d1..75db33d46af6 100644
--- a/include/hw/ppc/pnv_xscom.h
+++ b/include/hw/ppc/pnv_xscom.h
@@ -137,6 +137,12 @@ struct PnvXScomInterfaceClass {
#define PNV10_XSCOM_XIVE2_BASE 0x2010800
#define PNV10_XSCOM_XIVE2_SIZE 0x400
+#define PNV10_XSCOM_PEC_NEST_BASE 0x3011800 /* index goes downwards ... */
+#define PNV10_XSCOM_PEC_NEST_SIZE 0x100
+
+#define PNV10_XSCOM_PEC_PCI_BASE 0x8010800 /* index goes upwards ... */
+#define PNV10_XSCOM_PEC_PCI_SIZE 0x200
+
void pnv_xscom_realize(PnvChip *chip, uint64_t size, Error **errp);
int pnv_dt_xscom(PnvChip *chip, void *fdt, int root_offset,
uint64_t xscom_base, uint64_t xscom_size,
diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c
index 846e7d0c3e24..5344a6d4a693 100644
--- a/hw/pci-host/pnv_phb4.c
+++ b/hw/pci-host/pnv_phb4.c
@@ -1812,9 +1812,29 @@ static const TypeInfo pnv_phb4_root_port_info = {
.class_init = pnv_phb4_root_port_class_init,
};
+static void pnv_phb5_root_port_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
+
+ dc->desc = "IBM PHB5 PCIE Root Port";
+ dc->user_creatable = true;
+
+ k->vendor_id = PCI_VENDOR_ID_IBM;
+ k->device_id = PNV_PHB5_DEVICE_ID;
+}
+
+static const TypeInfo pnv_phb5_root_port_info = {
+ .name = TYPE_PNV_PHB5_ROOT_PORT,
+ .parent = TYPE_PNV_PHB4_ROOT_PORT,
+ .instance_size = sizeof(PnvPHB4RootPort),
+ .class_init = pnv_phb5_root_port_class_init,
+};
+
static void pnv_phb4_register_types(void)
{
type_register_static(&pnv_phb4_root_bus_info);
+ type_register_static(&pnv_phb5_root_port_info);
type_register_static(&pnv_phb4_root_port_info);
type_register_static(&pnv_phb4_type_info);
type_register_static(&pnv_phb4_iommu_memory_region_info);
diff --git a/hw/pci-host/pnv_phb4_pec.c b/hw/pci-host/pnv_phb4_pec.c
index 40d89fda56e5..0ab36e9c8f3c 100644
--- a/hw/pci-host/pnv_phb4_pec.c
+++ b/hw/pci-host/pnv_phb4_pec.c
@@ -281,9 +281,62 @@ static const TypeInfo pnv_pec_type_info = {
}
};
+/*
+ * POWER10 definitions
+ */
+
+static uint32_t pnv_phb5_pec_xscom_pci_base(PnvPhb4PecState *pec)
+{
+ return PNV10_XSCOM_PEC_PCI_BASE + 0x1000000 * pec->index;
+}
+
+static uint32_t pnv_phb5_pec_xscom_nest_base(PnvPhb4PecState *pec)
+{
+ /* index goes down ... */
+ return PNV10_XSCOM_PEC_NEST_BASE - 0x1000000 * pec->index;
+}
+
+/*
+ * PEC0 -> 3 stacks
+ * PEC1 -> 3 stacks
+ */
+static const uint32_t pnv_phb5_pec_num_stacks[] = { 3, 3 };
+
+static void pnv_phb5_pec_class_init(ObjectClass *klass, void *data)
+{
+ PnvPhb4PecClass *pecc = PNV_PHB4_PEC_CLASS(klass);
+ static const char compat[] = "ibm,power10-pbcq";
+ static const char stk_compat[] = "ibm,power10-phb-stack";
+
+ pecc->xscom_nest_base = pnv_phb5_pec_xscom_nest_base;
+ pecc->xscom_pci_base = pnv_phb5_pec_xscom_pci_base;
+ pecc->xscom_nest_size = PNV10_XSCOM_PEC_NEST_SIZE;
+ pecc->xscom_pci_size = PNV10_XSCOM_PEC_PCI_SIZE;
+ pecc->compat = compat;
+ pecc->compat_size = sizeof(compat);
+ pecc->stk_compat = stk_compat;
+ pecc->stk_compat_size = sizeof(stk_compat);
+ pecc->version = PNV_PHB5_VERSION;
+ pecc->num_phbs = pnv_phb5_pec_num_stacks;
+ pecc->rp_model = TYPE_PNV_PHB5_ROOT_PORT;
+}
+
+static const TypeInfo pnv_phb5_pec_type_info = {
+ .name = TYPE_PNV_PHB5_PEC,
+ .parent = TYPE_PNV_PHB4_PEC,
+ .instance_size = sizeof(PnvPhb4PecState),
+ .class_init = pnv_phb5_pec_class_init,
+ .class_size = sizeof(PnvPhb4PecClass),
+ .interfaces = (InterfaceInfo[]) {
+ { TYPE_PNV_XSCOM_INTERFACE },
+ { }
+ }
+};
+
static void pnv_pec_register_types(void)
{
type_register_static(&pnv_pec_type_info);
+ type_register_static(&pnv_phb5_pec_type_info);
}
type_init(pnv_pec_register_types);
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 77f250b86d8f..34659087e803 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -727,6 +727,9 @@ static void pnv_chip_power10_pic_print_info(PnvChip *chip, Monitor *mon)
pnv_xive2_pic_print_info(&chip10->xive, mon);
pnv_psi_pic_print_info(&chip10->psi, mon);
+
+ object_child_foreach_recursive(OBJECT(chip),
+ pnv_chip_power9_pic_print_info_child, mon);
}
/* Always give the first 1GB to chip 0 else we won't boot */
@@ -1581,7 +1584,10 @@ static void pnv_chip_power9_class_init(ObjectClass *klass, void *data)
static void pnv_chip_power10_instance_init(Object *obj)
{
+ PnvChip *chip = PNV_CHIP(obj);
Pnv10Chip *chip10 = PNV10_CHIP(obj);
+ PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj);
+ int i;
object_initialize_child(obj, "xive", &chip10->xive, TYPE_PNV_XIVE2);
object_property_add_alias(obj, "xive-fabric", OBJECT(&chip10->xive),
@@ -1589,6 +1595,15 @@ static void pnv_chip_power10_instance_init(Object *obj)
object_initialize_child(obj, "psi", &chip10->psi, TYPE_PNV10_PSI);
object_initialize_child(obj, "lpc", &chip10->lpc, TYPE_PNV10_LPC);
object_initialize_child(obj, "occ", &chip10->occ, TYPE_PNV10_OCC);
+
+ if (defaults_enabled()) {
+ chip->num_pecs = pcc->num_pecs;
+ }
+
+ for (i = 0; i < chip->num_pecs; i++) {
+ object_initialize_child(obj, "pec[*]", &chip10->pecs[i],
+ TYPE_PNV_PHB5_PEC);
+ }
}
static void pnv_chip_power10_quad_realize(Pnv10Chip *chip10, Error **errp)
@@ -1609,6 +1624,34 @@ static void pnv_chip_power10_quad_realize(Pnv10Chip *chip10, Error **errp)
}
}
+static void pnv_chip_power10_phb_realize(PnvChip *chip, Error **errp)
+{
+ Pnv10Chip *chip10 = PNV10_CHIP(chip);
+ int i;
+
+ for (i = 0; i < chip->num_pecs; i++) {
+ PnvPhb4PecState *pec = &chip10->pecs[i];
+ PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec);
+ uint32_t pec_nest_base;
+ uint32_t pec_pci_base;
+
+ object_property_set_int(OBJECT(pec), "index", i, &error_fatal);
+ object_property_set_int(OBJECT(pec), "chip-id", chip->chip_id,
+ &error_fatal);
+ object_property_set_link(OBJECT(pec), "chip", OBJECT(chip),
+ &error_fatal);
+ if (!qdev_realize(DEVICE(pec), NULL, errp)) {
+ return;
+ }
+
+ pec_nest_base = pecc->xscom_nest_base(pec);
+ pec_pci_base = pecc->xscom_pci_base(pec);
+
+ pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr);
+ pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr);
+ }
+}
+
static void pnv_chip_power10_realize(DeviceState *dev, Error **errp)
{
PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev);
@@ -1687,6 +1730,13 @@ static void pnv_chip_power10_realize(DeviceState *dev, Error **errp)
}
pnv_xscom_add_subregion(chip, PNV10_XSCOM_OCC_BASE,
&chip10->occ.xscom_regs);
+
+ /* PHBs */
+ pnv_chip_power10_phb_realize(chip, &local_err);
+ if (local_err) {
+ error_propagate(errp, local_err);
+ return;
+ }
}
static uint32_t pnv_chip_power10_xscom_pcba(PnvChip *chip, uint64_t addr)
@@ -1713,6 +1763,7 @@ static void pnv_chip_power10_class_init(ObjectClass *klass, void *data)
k->xscom_core_base = pnv_chip_power10_xscom_core_base;
k->xscom_pcba = pnv_chip_power10_xscom_pcba;
dc->desc = "PowerNV Chip POWER10";
+ k->num_pecs = PNV10_CHIP_MAX_PEC;
device_class_set_parent_realize(dc, pnv_chip_power10_realize,
&k->parent_realize);
--
2.34.1
^ permalink raw reply related [flat|nested] 89+ messages in thread* [PULL 62/87] ppc/pnv: Add a HOMER model to POWER10
2022-03-02 11:06 [PULL 00/87] ppc queue Cédric Le Goater
` (60 preceding siblings ...)
2022-03-02 11:07 ` [PULL 61/87] ppc/pnv: Add model for POWER10 PHB5 PCIe Host bridge Cédric Le Goater
@ 2022-03-02 11:07 ` Cédric Le Goater
2022-03-02 11:07 ` [PULL 63/87] ppc/psi: Add support for StoreEOI and 64k ESB pages (POWER10) Cédric Le Goater
` (25 subsequent siblings)
87 siblings, 0 replies; 89+ messages in thread
From: Cédric Le Goater @ 2022-03-02 11:07 UTC (permalink / raw)
To: qemu-ppc, qemu-devel; +Cc: Peter Maydell, Cédric Le Goater, David Gibson
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
include/hw/ppc/pnv.h | 10 ++++++
include/hw/ppc/pnv_homer.h | 3 ++
include/hw/ppc/pnv_xscom.h | 3 ++
hw/ppc/pnv.c | 20 ++++++++++++
hw/ppc/pnv_homer.c | 64 ++++++++++++++++++++++++++++++++++++++
5 files changed, 100 insertions(+)
diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h
index e5141851faed..1e34ddd502d8 100644
--- a/include/hw/ppc/pnv.h
+++ b/include/hw/ppc/pnv.h
@@ -129,6 +129,7 @@ struct Pnv10Chip {
Pnv9Psi psi;
PnvLpcController lpc;
PnvOCC occ;
+ PnvHomer homer;
uint32_t nr_quads;
PnvQuad *quads;
@@ -364,4 +365,13 @@ void pnv_bmc_set_pnor(IPMIBmc *bmc, PnvPnor *pnor);
#define PNV10_XIVE2_END_SIZE 0x0000020000000000ull
#define PNV10_XIVE2_END_BASE(chip) PNV10_CHIP_BASE(chip, 0x0006060000000000ull)
+#define PNV10_OCC_COMMON_AREA_SIZE 0x0000000000800000ull
+#define PNV10_OCC_COMMON_AREA_BASE 0x300fff800000ull
+#define PNV10_OCC_SENSOR_BASE(chip) (PNV10_OCC_COMMON_AREA_BASE + \
+ PNV_OCC_SENSOR_DATA_BLOCK_BASE((chip)->chip_id))
+
+#define PNV10_HOMER_SIZE 0x0000000000400000ull
+#define PNV10_HOMER_BASE(chip) \
+ (0x300ffd800000ll + ((uint64_t)(chip)->chip_id) * PNV10_HOMER_SIZE)
+
#endif /* PPC_PNV_H */
diff --git a/include/hw/ppc/pnv_homer.h b/include/hw/ppc/pnv_homer.h
index 1889e3083c57..07e8b193116e 100644
--- a/include/hw/ppc/pnv_homer.h
+++ b/include/hw/ppc/pnv_homer.h
@@ -32,6 +32,9 @@ DECLARE_INSTANCE_CHECKER(PnvHomer, PNV8_HOMER,
#define TYPE_PNV9_HOMER TYPE_PNV_HOMER "-POWER9"
DECLARE_INSTANCE_CHECKER(PnvHomer, PNV9_HOMER,
TYPE_PNV9_HOMER)
+#define TYPE_PNV10_HOMER TYPE_PNV_HOMER "-POWER10"
+DECLARE_INSTANCE_CHECKER(PnvHomer, PNV10_HOMER,
+ TYPE_PNV10_HOMER)
struct PnvHomer {
DeviceState parent;
diff --git a/include/hw/ppc/pnv_xscom.h b/include/hw/ppc/pnv_xscom.h
index 75db33d46af6..7c7440de0c40 100644
--- a/include/hw/ppc/pnv_xscom.h
+++ b/include/hw/ppc/pnv_xscom.h
@@ -134,6 +134,9 @@ struct PnvXScomInterfaceClass {
#define PNV10_XSCOM_OCC_BASE PNV9_XSCOM_OCC_BASE
#define PNV10_XSCOM_OCC_SIZE PNV9_XSCOM_OCC_SIZE
+#define PNV10_XSCOM_PBA_BASE 0x01010CDA
+#define PNV10_XSCOM_PBA_SIZE 0x40
+
#define PNV10_XSCOM_XIVE2_BASE 0x2010800
#define PNV10_XSCOM_XIVE2_SIZE 0x400
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 34659087e803..10ad16c1c55c 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -1595,6 +1595,7 @@ static void pnv_chip_power10_instance_init(Object *obj)
object_initialize_child(obj, "psi", &chip10->psi, TYPE_PNV10_PSI);
object_initialize_child(obj, "lpc", &chip10->lpc, TYPE_PNV10_LPC);
object_initialize_child(obj, "occ", &chip10->occ, TYPE_PNV10_OCC);
+ object_initialize_child(obj, "homer", &chip10->homer, TYPE_PNV10_HOMER);
if (defaults_enabled()) {
chip->num_pecs = pcc->num_pecs;
@@ -1731,6 +1732,25 @@ static void pnv_chip_power10_realize(DeviceState *dev, Error **errp)
pnv_xscom_add_subregion(chip, PNV10_XSCOM_OCC_BASE,
&chip10->occ.xscom_regs);
+ /* OCC SRAM model */
+ memory_region_add_subregion(get_system_memory(),
+ PNV10_OCC_SENSOR_BASE(chip),
+ &chip10->occ.sram_regs);
+
+ /* HOMER */
+ object_property_set_link(OBJECT(&chip10->homer), "chip", OBJECT(chip),
+ &error_abort);
+ if (!qdev_realize(DEVICE(&chip10->homer), NULL, errp)) {
+ return;
+ }
+ /* Homer Xscom region */
+ pnv_xscom_add_subregion(chip, PNV10_XSCOM_PBA_BASE,
+ &chip10->homer.pba_regs);
+
+ /* Homer mmio region */
+ memory_region_add_subregion(get_system_memory(), PNV10_HOMER_BASE(chip),
+ &chip10->homer.regs);
+
/* PHBs */
pnv_chip_power10_phb_realize(chip, &local_err);
if (local_err) {
diff --git a/hw/ppc/pnv_homer.c b/hw/ppc/pnv_homer.c
index 9a262629b73a..ea73919e54ca 100644
--- a/hw/ppc/pnv_homer.c
+++ b/hw/ppc/pnv_homer.c
@@ -332,6 +332,69 @@ static const TypeInfo pnv_homer_power9_type_info = {
.class_init = pnv_homer_power9_class_init,
};
+static uint64_t pnv_homer_power10_pba_read(void *opaque, hwaddr addr,
+ unsigned size)
+{
+ PnvHomer *homer = PNV_HOMER(opaque);
+ PnvChip *chip = homer->chip;
+ uint32_t reg = addr >> 3;
+ uint64_t val = 0;
+
+ switch (reg) {
+ case PBA_BAR0:
+ val = PNV10_HOMER_BASE(chip);
+ break;
+ case PBA_BARMASK0: /* P10 homer region mask */
+ val = (PNV10_HOMER_SIZE - 1) & 0x300000;
+ break;
+ case PBA_BAR2: /* P10 occ common area */
+ val = PNV10_OCC_COMMON_AREA_BASE;
+ break;
+ case PBA_BARMASK2: /* P10 occ common area size */
+ val = (PNV10_OCC_COMMON_AREA_SIZE - 1) & 0x700000;
+ break;
+ default:
+ qemu_log_mask(LOG_UNIMP, "PBA: read to unimplemented register: Ox%"
+ HWADDR_PRIx "\n", addr >> 3);
+ }
+ return val;
+}
+
+static void pnv_homer_power10_pba_write(void *opaque, hwaddr addr,
+ uint64_t val, unsigned size)
+{
+ qemu_log_mask(LOG_UNIMP, "PBA: write to unimplemented register: Ox%"
+ HWADDR_PRIx "\n", addr >> 3);
+}
+
+static const MemoryRegionOps pnv_homer_power10_pba_ops = {
+ .read = pnv_homer_power10_pba_read,
+ .write = pnv_homer_power10_pba_write,
+ .valid.min_access_size = 8,
+ .valid.max_access_size = 8,
+ .impl.min_access_size = 8,
+ .impl.max_access_size = 8,
+ .endianness = DEVICE_BIG_ENDIAN,
+};
+
+static void pnv_homer_power10_class_init(ObjectClass *klass, void *data)
+{
+ PnvHomerClass *homer = PNV_HOMER_CLASS(klass);
+
+ homer->pba_size = PNV10_XSCOM_PBA_SIZE;
+ homer->pba_ops = &pnv_homer_power10_pba_ops;
+ homer->homer_size = PNV10_HOMER_SIZE;
+ homer->homer_ops = &pnv_power9_homer_ops; /* TODO */
+ homer->core_max_base = PNV9_CORE_MAX_BASE;
+}
+
+static const TypeInfo pnv_homer_power10_type_info = {
+ .name = TYPE_PNV10_HOMER,
+ .parent = TYPE_PNV_HOMER,
+ .instance_size = sizeof(PnvHomer),
+ .class_init = pnv_homer_power10_class_init,
+};
+
static void pnv_homer_realize(DeviceState *dev, Error **errp)
{
PnvHomer *homer = PNV_HOMER(dev);
@@ -377,6 +440,7 @@ static void pnv_homer_register_types(void)
type_register_static(&pnv_homer_type_info);
type_register_static(&pnv_homer_power8_type_info);
type_register_static(&pnv_homer_power9_type_info);
+ type_register_static(&pnv_homer_power10_type_info);
}
type_init(pnv_homer_register_types);
--
2.34.1
^ permalink raw reply related [flat|nested] 89+ messages in thread* [PULL 63/87] ppc/psi: Add support for StoreEOI and 64k ESB pages (POWER10)
2022-03-02 11:06 [PULL 00/87] ppc queue Cédric Le Goater
` (61 preceding siblings ...)
2022-03-02 11:07 ` [PULL 62/87] ppc/pnv: Add a HOMER model to POWER10 Cédric Le Goater
@ 2022-03-02 11:07 ` Cédric Le Goater
2022-03-02 11:07 ` [PULL 64/87] ppc/xive2: Add support for notification injection on ESB pages Cédric Le Goater
` (24 subsequent siblings)
87 siblings, 0 replies; 89+ messages in thread
From: Cédric Le Goater @ 2022-03-02 11:07 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Daniel Henrique Barboza, Cédric Le Goater
POWER10 adds support for StoreEOI operation and 64K ESB pages on PSIHB
to be consistent with the other interrupt sources of the system.
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/ppc/pnv.c | 6 ++++++
hw/ppc/pnv_psi.c | 30 ++++++++++++++++++++++++------
2 files changed, 30 insertions(+), 6 deletions(-)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 10ad16c1c55c..0ac86e104fa0 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -1500,6 +1500,9 @@ static void pnv_chip_power9_realize(DeviceState *dev, Error **errp)
/* Processor Service Interface (PSI) Host Bridge */
object_property_set_int(OBJECT(&chip9->psi), "bar", PNV9_PSIHB_BASE(chip),
&error_fatal);
+ /* This is the only device with 4k ESB pages */
+ object_property_set_int(OBJECT(&chip9->psi), "shift", XIVE_ESB_4K,
+ &error_fatal);
if (!qdev_realize(DEVICE(&chip9->psi), NULL, errp)) {
return;
}
@@ -1704,6 +1707,9 @@ static void pnv_chip_power10_realize(DeviceState *dev, Error **errp)
/* Processor Service Interface (PSI) Host Bridge */
object_property_set_int(OBJECT(&chip10->psi), "bar",
PNV10_PSIHB_BASE(chip), &error_fatal);
+ /* PSI can now be configured to use 64k ESB pages on POWER10 */
+ object_property_set_int(OBJECT(&chip10->psi), "shift", XIVE_ESB_64K,
+ &error_fatal);
if (!qdev_realize(DEVICE(&chip10->psi), NULL, errp)) {
return;
}
diff --git a/hw/ppc/pnv_psi.c b/hw/ppc/pnv_psi.c
index cd9a2c5952a6..737486046d5a 100644
--- a/hw/ppc/pnv_psi.c
+++ b/hw/ppc/pnv_psi.c
@@ -601,7 +601,6 @@ static const TypeInfo pnv_psi_power8_info = {
#define PSIHB9_IRQ_METHOD PPC_BIT(0)
#define PSIHB9_IRQ_RESET PPC_BIT(1)
#define PSIHB9_ESB_CI_BASE 0x60
-#define PSIHB9_ESB_CI_64K PPC_BIT(1)
#define PSIHB9_ESB_CI_ADDR_MASK PPC_BITMASK(8, 47)
#define PSIHB9_ESB_CI_VALID PPC_BIT(63)
#define PSIHB9_ESB_NOTIF_ADDR 0x68
@@ -646,6 +645,14 @@ static const TypeInfo pnv_psi_power8_info = {
#define PSIHB9_IRQ_STAT_DIO PPC_BIT(12)
#define PSIHB9_IRQ_STAT_PSU PPC_BIT(13)
+/* P10 register extensions */
+
+#define PSIHB10_CR PSIHB9_CR
+#define PSIHB10_CR_STORE_EOI PPC_BIT(12)
+
+#define PSIHB10_ESB_CI_BASE PSIHB9_ESB_CI_BASE
+#define PSIHB10_ESB_CI_64K PPC_BIT(1)
+
static void pnv_psi_notify(XiveNotifier *xf, uint32_t srcno)
{
PnvPsi *psi = PNV_PSI(xf);
@@ -704,6 +711,13 @@ static void pnv_psi_p9_mmio_write(void *opaque, hwaddr addr,
switch (addr) {
case PSIHB9_CR:
+ if (val & PSIHB10_CR_STORE_EOI) {
+ psi9->source.esb_flags |= XIVE_SRC_STORE_EOI;
+ } else {
+ psi9->source.esb_flags &= ~XIVE_SRC_STORE_EOI;
+ }
+ break;
+
case PSIHB9_SEMR:
/* FSP stuff */
break;
@@ -715,15 +729,20 @@ static void pnv_psi_p9_mmio_write(void *opaque, hwaddr addr,
break;
case PSIHB9_ESB_CI_BASE:
+ if (val & PSIHB10_ESB_CI_64K) {
+ psi9->source.esb_shift = XIVE_ESB_64K;
+ } else {
+ psi9->source.esb_shift = XIVE_ESB_4K;
+ }
if (!(val & PSIHB9_ESB_CI_VALID)) {
if (psi->regs[reg] & PSIHB9_ESB_CI_VALID) {
memory_region_del_subregion(sysmem, &psi9->source.esb_mmio);
}
} else {
if (!(psi->regs[reg] & PSIHB9_ESB_CI_VALID)) {
- memory_region_add_subregion(sysmem,
- val & ~PSIHB9_ESB_CI_VALID,
- &psi9->source.esb_mmio);
+ hwaddr addr = val & ~(PSIHB9_ESB_CI_VALID | PSIHB10_ESB_CI_64K);
+ memory_region_add_subregion(sysmem, addr,
+ &psi9->source.esb_mmio);
}
}
psi->regs[reg] = val;
@@ -831,6 +850,7 @@ static void pnv_psi_power9_instance_init(Object *obj)
Pnv9Psi *psi = PNV9_PSI(obj);
object_initialize_child(obj, "source", &psi->source, TYPE_XIVE_SOURCE);
+ object_property_add_alias(obj, "shift", OBJECT(&psi->source), "shift");
}
static void pnv_psi_power9_realize(DeviceState *dev, Error **errp)
@@ -839,8 +859,6 @@ static void pnv_psi_power9_realize(DeviceState *dev, Error **errp)
XiveSource *xsrc = &PNV9_PSI(psi)->source;
int i;
- /* This is the only device with 4k ESB pages */
- object_property_set_int(OBJECT(xsrc), "shift", XIVE_ESB_4K, &error_fatal);
object_property_set_int(OBJECT(xsrc), "nr-irqs", PSIHB9_NUM_IRQS,
&error_fatal);
object_property_set_link(OBJECT(xsrc), "xive", OBJECT(psi), &error_abort);
--
2.34.1
^ permalink raw reply related [flat|nested] 89+ messages in thread* [PULL 64/87] ppc/xive2: Add support for notification injection on ESB pages
2022-03-02 11:06 [PULL 00/87] ppc queue Cédric Le Goater
` (62 preceding siblings ...)
2022-03-02 11:07 ` [PULL 63/87] ppc/psi: Add support for StoreEOI and 64k ESB pages (POWER10) Cédric Le Goater
@ 2022-03-02 11:07 ` Cédric Le Goater
2022-03-02 11:07 ` [PULL 65/87] ppc/xive: Add support for PQ state bits offload Cédric Le Goater
` (23 subsequent siblings)
87 siblings, 0 replies; 89+ messages in thread
From: Cédric Le Goater @ 2022-03-02 11:07 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Daniel Henrique Barboza, Cédric Le Goater
This is an internal offset used to inject triggers when the PQ state
bits are not controlled locally. Such as for LSIs when the PHB5 are
using the Address-Based Interrupt Trigger mode and on the END.
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
include/hw/ppc/xive.h | 1 +
hw/intc/xive.c | 9 +++++++++
hw/intc/xive2.c | 10 ++++++++++
3 files changed, 20 insertions(+)
diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h
index b8ab0bf7490f..875c7f639689 100644
--- a/include/hw/ppc/xive.h
+++ b/include/hw/ppc/xive.h
@@ -278,6 +278,7 @@ uint8_t xive_esb_set(uint8_t *pq, uint8_t value);
#define XIVE_ESB_STORE_EOI 0x400 /* Store */
#define XIVE_ESB_LOAD_EOI 0x000 /* Load */
#define XIVE_ESB_GET 0x800 /* Load */
+#define XIVE_ESB_INJECT 0x800 /* Store */
#define XIVE_ESB_SET_PQ_00 0xc00 /* Load */
#define XIVE_ESB_SET_PQ_01 0xd00 /* Load */
#define XIVE_ESB_SET_PQ_10 0xe00 /* Load */
diff --git a/hw/intc/xive.c b/hw/intc/xive.c
index f15f98588a71..0d98b9539cd9 100644
--- a/hw/intc/xive.c
+++ b/hw/intc/xive.c
@@ -1061,6 +1061,15 @@ static void xive_source_esb_write(void *opaque, hwaddr addr,
notify = xive_source_esb_eoi(xsrc, srcno);
break;
+ /*
+ * This is an internal offset used to inject triggers when the PQ
+ * state bits are not controlled locally. Such as for LSIs when
+ * under ABT mode.
+ */
+ case XIVE_ESB_INJECT ... XIVE_ESB_INJECT + 0x3FF:
+ notify = true;
+ break;
+
case XIVE_ESB_SET_PQ_00 ... XIVE_ESB_SET_PQ_00 + 0x0FF:
case XIVE_ESB_SET_PQ_01 ... XIVE_ESB_SET_PQ_01 + 0x0FF:
case XIVE_ESB_SET_PQ_10 ... XIVE_ESB_SET_PQ_10 + 0x0FF:
diff --git a/hw/intc/xive2.c b/hw/intc/xive2.c
index 8f278f3bf680..2836bbdc83fc 100644
--- a/hw/intc/xive2.c
+++ b/hw/intc/xive2.c
@@ -659,6 +659,16 @@ static void xive2_end_source_write(void *opaque, hwaddr addr,
notify = xive_esb_eoi(&pq);
break;
+ case XIVE_ESB_INJECT ... XIVE_ESB_INJECT + 0x3FF:
+ if (end_esmask == END2_W1_ESe) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "XIVE: END %x/%x can not EQ inject on ESe\n",
+ end_blk, end_idx);
+ return;
+ }
+ notify = true;
+ break;
+
default:
qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid END ESB write addr %d\n",
offset);
--
2.34.1
^ permalink raw reply related [flat|nested] 89+ messages in thread* [PULL 65/87] ppc/xive: Add support for PQ state bits offload
2022-03-02 11:06 [PULL 00/87] ppc queue Cédric Le Goater
` (63 preceding siblings ...)
2022-03-02 11:07 ` [PULL 64/87] ppc/xive2: Add support for notification injection on ESB pages Cédric Le Goater
@ 2022-03-02 11:07 ` Cédric Le Goater
2022-03-02 11:07 ` [PULL 66/87] ppc/pnv: Add support for PQ offload on PHB5 Cédric Le Goater
` (22 subsequent siblings)
87 siblings, 0 replies; 89+ messages in thread
From: Cédric Le Goater @ 2022-03-02 11:07 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Daniel Henrique Barboza, Cédric Le Goater
The trigger message coming from a HW source contains a special bit
informing the XIVE interrupt controller that the PQ bits have been
checked at the source or not. Depending on the value, the IC can
perform the check and the state transition locally using its own PQ
state bits.
The following changes add new accessors to the XiveRouter required to
query and update the PQ state bits. This only applies to the PowerNV
machine. sPAPR accessors are provided but the pSeries machine should
not be concerned by such complex configuration for the moment.
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
include/hw/ppc/xive.h | 8 +++++--
include/hw/ppc/xive2.h | 6 +++++-
hw/intc/pnv_xive.c | 37 +++++++++++++++++++++++++++++---
hw/intc/pnv_xive2.c | 37 +++++++++++++++++++++++++++++---
hw/intc/spapr_xive.c | 25 ++++++++++++++++++++++
hw/intc/xive.c | 48 ++++++++++++++++++++++++++++++++++++------
hw/intc/xive2.c | 42 +++++++++++++++++++++++++++++++++++-
hw/pci-host/pnv_phb4.c | 9 ++++++--
hw/ppc/pnv_psi.c | 8 +++++--
9 files changed, 199 insertions(+), 21 deletions(-)
diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h
index 875c7f639689..649b58a08f0c 100644
--- a/include/hw/ppc/xive.h
+++ b/include/hw/ppc/xive.h
@@ -160,7 +160,7 @@ DECLARE_CLASS_CHECKERS(XiveNotifierClass, XIVE_NOTIFIER,
struct XiveNotifierClass {
InterfaceClass parent;
- void (*notify)(XiveNotifier *xn, uint32_t lisn);
+ void (*notify)(XiveNotifier *xn, uint32_t lisn, bool pq_checked);
};
/*
@@ -386,6 +386,10 @@ struct XiveRouterClass {
/* XIVE table accessors */
int (*get_eas)(XiveRouter *xrtr, uint8_t eas_blk, uint32_t eas_idx,
XiveEAS *eas);
+ int (*get_pq)(XiveRouter *xrtr, uint8_t eas_blk, uint32_t eas_idx,
+ uint8_t *pq);
+ int (*set_pq)(XiveRouter *xrtr, uint8_t eas_blk, uint32_t eas_idx,
+ uint8_t *pq);
int (*get_end)(XiveRouter *xrtr, uint8_t end_blk, uint32_t end_idx,
XiveEND *end);
int (*write_end)(XiveRouter *xrtr, uint8_t end_blk, uint32_t end_idx,
@@ -407,7 +411,7 @@ int xive_router_get_nvt(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx,
XiveNVT *nvt);
int xive_router_write_nvt(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx,
XiveNVT *nvt, uint8_t word_number);
-void xive_router_notify(XiveNotifier *xn, uint32_t lisn);
+void xive_router_notify(XiveNotifier *xn, uint32_t lisn, bool pq_checked);
/*
* XIVE Presenter
diff --git a/include/hw/ppc/xive2.h b/include/hw/ppc/xive2.h
index 0897ddbd4874..eb255b6dd8f3 100644
--- a/include/hw/ppc/xive2.h
+++ b/include/hw/ppc/xive2.h
@@ -31,6 +31,10 @@ typedef struct Xive2RouterClass {
/* XIVE table accessors */
int (*get_eas)(Xive2Router *xrtr, uint8_t eas_blk, uint32_t eas_idx,
Xive2Eas *eas);
+ int (*get_pq)(Xive2Router *xrtr, uint8_t eas_blk, uint32_t eas_idx,
+ uint8_t *pq);
+ int (*set_pq)(Xive2Router *xrtr, uint8_t eas_blk, uint32_t eas_idx,
+ uint8_t *pq);
int (*get_end)(Xive2Router *xrtr, uint8_t end_blk, uint32_t end_idx,
Xive2End *end);
int (*write_end)(Xive2Router *xrtr, uint8_t end_blk, uint32_t end_idx,
@@ -53,7 +57,7 @@ int xive2_router_get_nvp(Xive2Router *xrtr, uint8_t nvp_blk, uint32_t nvp_idx,
int xive2_router_write_nvp(Xive2Router *xrtr, uint8_t nvp_blk, uint32_t nvp_idx,
Xive2Nvp *nvp, uint8_t word_number);
-void xive2_router_notify(XiveNotifier *xn, uint32_t lisn);
+void xive2_router_notify(XiveNotifier *xn, uint32_t lisn, bool pq_checked);
/*
* XIVE2 Presenter (POWER10)
diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c
index 621b20a03f5f..1ce1d7b07d63 100644
--- a/hw/intc/pnv_xive.c
+++ b/hw/intc/pnv_xive.c
@@ -403,6 +403,34 @@ static int pnv_xive_get_eas(XiveRouter *xrtr, uint8_t blk, uint32_t idx,
return pnv_xive_vst_read(xive, VST_TSEL_IVT, blk, idx, eas);
}
+static int pnv_xive_get_pq(XiveRouter *xrtr, uint8_t blk, uint32_t idx,
+ uint8_t *pq)
+{
+ PnvXive *xive = PNV_XIVE(xrtr);
+
+ if (pnv_xive_block_id(xive) != blk) {
+ xive_error(xive, "VST: EAS %x is remote !?", XIVE_EAS(blk, idx));
+ return -1;
+ }
+
+ *pq = xive_source_esb_get(&xive->ipi_source, idx);
+ return 0;
+}
+
+static int pnv_xive_set_pq(XiveRouter *xrtr, uint8_t blk, uint32_t idx,
+ uint8_t *pq)
+{
+ PnvXive *xive = PNV_XIVE(xrtr);
+
+ if (pnv_xive_block_id(xive) != blk) {
+ xive_error(xive, "VST: EAS %x is remote !?", XIVE_EAS(blk, idx));
+ return -1;
+ }
+
+ *pq = xive_source_esb_set(&xive->ipi_source, idx, *pq);
+ return 0;
+}
+
/*
* One bit per thread id. The first register PC_THREAD_EN_REG0 covers
* the first cores 0-15 (normal) of the chip or 0-7 (fused). The
@@ -499,12 +527,12 @@ static PnvXive *pnv_xive_tm_get_xive(PowerPCCPU *cpu)
* event notification to the Router. This is required on a multichip
* system.
*/
-static void pnv_xive_notify(XiveNotifier *xn, uint32_t srcno)
+static void pnv_xive_notify(XiveNotifier *xn, uint32_t srcno, bool pq_checked)
{
PnvXive *xive = PNV_XIVE(xn);
uint8_t blk = pnv_xive_block_id(xive);
- xive_router_notify(xn, XIVE_EAS(blk, srcno));
+ xive_router_notify(xn, XIVE_EAS(blk, srcno), pq_checked);
}
/*
@@ -1351,7 +1379,8 @@ static void pnv_xive_ic_hw_trigger(PnvXive *xive, hwaddr addr, uint64_t val)
blk = XIVE_EAS_BLOCK(val);
idx = XIVE_EAS_INDEX(val);
- xive_router_notify(XIVE_NOTIFIER(xive), XIVE_EAS(blk, idx));
+ xive_router_notify(XIVE_NOTIFIER(xive), XIVE_EAS(blk, idx),
+ !!(val & XIVE_TRIGGER_PQ));
}
static void pnv_xive_ic_notify_write(void *opaque, hwaddr addr, uint64_t val,
@@ -1971,6 +2000,8 @@ static void pnv_xive_class_init(ObjectClass *klass, void *data)
device_class_set_props(dc, pnv_xive_properties);
xrc->get_eas = pnv_xive_get_eas;
+ xrc->get_pq = pnv_xive_get_pq;
+ xrc->set_pq = pnv_xive_set_pq;
xrc->get_end = pnv_xive_get_end;
xrc->write_end = pnv_xive_write_end;
xrc->get_nvt = pnv_xive_get_nvt;
diff --git a/hw/intc/pnv_xive2.c b/hw/intc/pnv_xive2.c
index 35a7f7ae4dd8..1fa89c779287 100644
--- a/hw/intc/pnv_xive2.c
+++ b/hw/intc/pnv_xive2.c
@@ -285,6 +285,34 @@ static int pnv_xive2_vst_write(PnvXive2 *xive, uint32_t type, uint8_t blk,
return 0;
}
+static int pnv_xive2_get_pq(Xive2Router *xrtr, uint8_t blk, uint32_t idx,
+ uint8_t *pq)
+{
+ PnvXive2 *xive = PNV_XIVE2(xrtr);
+
+ if (pnv_xive2_block_id(xive) != blk) {
+ xive2_error(xive, "VST: EAS %x is remote !?", XIVE_EAS(blk, idx));
+ return -1;
+ }
+
+ *pq = xive_source_esb_get(&xive->ipi_source, idx);
+ return 0;
+}
+
+static int pnv_xive2_set_pq(Xive2Router *xrtr, uint8_t blk, uint32_t idx,
+ uint8_t *pq)
+{
+ PnvXive2 *xive = PNV_XIVE2(xrtr);
+
+ if (pnv_xive2_block_id(xive) != blk) {
+ xive2_error(xive, "VST: EAS %x is remote !?", XIVE_EAS(blk, idx));
+ return -1;
+ }
+
+ *pq = xive_source_esb_set(&xive->ipi_source, idx, *pq);
+ return 0;
+}
+
static int pnv_xive2_get_end(Xive2Router *xrtr, uint8_t blk, uint32_t idx,
Xive2End *end)
{
@@ -487,12 +515,12 @@ static PnvXive2 *pnv_xive2_tm_get_xive(PowerPCCPU *cpu)
* source interrupt number before forwarding the source event
* notification to the Router. This is required on a multichip system.
*/
-static void pnv_xive2_notify(XiveNotifier *xn, uint32_t srcno)
+static void pnv_xive2_notify(XiveNotifier *xn, uint32_t srcno, bool pq_checked)
{
PnvXive2 *xive = PNV_XIVE2(xn);
uint8_t blk = pnv_xive2_block_id(xive);
- xive2_router_notify(xn, XIVE_EAS(blk, srcno));
+ xive2_router_notify(xn, XIVE_EAS(blk, srcno), pq_checked);
}
/*
@@ -1381,7 +1409,8 @@ static void pnv_xive2_ic_hw_trigger(PnvXive2 *xive, hwaddr addr,
blk = XIVE_EAS_BLOCK(val);
idx = XIVE_EAS_INDEX(val);
- xive2_router_notify(XIVE_NOTIFIER(xive), XIVE_EAS(blk, idx));
+ xive2_router_notify(XIVE_NOTIFIER(xive), XIVE_EAS(blk, idx),
+ !!(val & XIVE_TRIGGER_PQ));
}
static void pnv_xive2_ic_notify_write(void *opaque, hwaddr offset,
@@ -1880,6 +1909,8 @@ static void pnv_xive2_class_init(ObjectClass *klass, void *data)
device_class_set_props(dc, pnv_xive2_properties);
xrc->get_eas = pnv_xive2_get_eas;
+ xrc->get_pq = pnv_xive2_get_pq;
+ xrc->set_pq = pnv_xive2_set_pq;
xrc->get_end = pnv_xive2_get_end;
xrc->write_end = pnv_xive2_write_end;
xrc->get_nvp = pnv_xive2_get_nvp;
diff --git a/hw/intc/spapr_xive.c b/hw/intc/spapr_xive.c
index eae95c716f14..dc641cc604bf 100644
--- a/hw/intc/spapr_xive.c
+++ b/hw/intc/spapr_xive.c
@@ -480,6 +480,29 @@ static uint8_t spapr_xive_get_block_id(XiveRouter *xrtr)
return SPAPR_XIVE_BLOCK_ID;
}
+static int spapr_xive_get_pq(XiveRouter *xrtr, uint8_t blk, uint32_t idx,
+ uint8_t *pq)
+{
+ SpaprXive *xive = SPAPR_XIVE(xrtr);
+
+ assert(SPAPR_XIVE_BLOCK_ID == blk);
+
+ *pq = xive_source_esb_get(&xive->source, idx);
+ return 0;
+}
+
+static int spapr_xive_set_pq(XiveRouter *xrtr, uint8_t blk, uint32_t idx,
+ uint8_t *pq)
+{
+ SpaprXive *xive = SPAPR_XIVE(xrtr);
+
+ assert(SPAPR_XIVE_BLOCK_ID == blk);
+
+ *pq = xive_source_esb_set(&xive->source, idx, *pq);
+ return 0;
+}
+
+
static const VMStateDescription vmstate_spapr_xive_end = {
.name = TYPE_SPAPR_XIVE "/end",
.version_id = 1,
@@ -788,6 +811,8 @@ static void spapr_xive_class_init(ObjectClass *klass, void *data)
dc->vmsd = &vmstate_spapr_xive;
xrc->get_eas = spapr_xive_get_eas;
+ xrc->get_pq = spapr_xive_get_pq;
+ xrc->set_pq = spapr_xive_set_pq;
xrc->get_end = spapr_xive_get_end;
xrc->write_end = spapr_xive_write_end;
xrc->get_nvt = spapr_xive_get_nvt;
diff --git a/hw/intc/xive.c b/hw/intc/xive.c
index 0d98b9539cd9..deb0db21e093 100644
--- a/hw/intc/xive.c
+++ b/hw/intc/xive.c
@@ -938,7 +938,7 @@ static void xive_source_notify(XiveSource *xsrc, int srcno)
XiveNotifierClass *xnc = XIVE_NOTIFIER_GET_CLASS(xsrc->xive);
if (xnc->notify) {
- xnc->notify(xsrc->xive, srcno);
+ xnc->notify(xsrc->xive, srcno, true);
}
}
@@ -1370,6 +1370,24 @@ int xive_router_get_eas(XiveRouter *xrtr, uint8_t eas_blk, uint32_t eas_idx,
return xrc->get_eas(xrtr, eas_blk, eas_idx, eas);
}
+static
+int xive_router_get_pq(XiveRouter *xrtr, uint8_t eas_blk, uint32_t eas_idx,
+ uint8_t *pq)
+{
+ XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr);
+
+ return xrc->get_pq(xrtr, eas_blk, eas_idx, pq);
+}
+
+static
+int xive_router_set_pq(XiveRouter *xrtr, uint8_t eas_blk, uint32_t eas_idx,
+ uint8_t *pq)
+{
+ XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr);
+
+ return xrc->set_pq(xrtr, eas_blk, eas_idx, pq);
+}
+
int xive_router_get_end(XiveRouter *xrtr, uint8_t end_blk, uint32_t end_idx,
XiveEND *end)
{
@@ -1721,7 +1739,7 @@ do_escalation:
xive_get_field32(END_W5_ESC_END_DATA, end.w5));
}
-void xive_router_notify(XiveNotifier *xn, uint32_t lisn)
+void xive_router_notify(XiveNotifier *xn, uint32_t lisn, bool pq_checked)
{
XiveRouter *xrtr = XIVE_ROUTER(xn);
uint8_t eas_blk = XIVE_EAS_BLOCK(lisn);
@@ -1734,11 +1752,27 @@ void xive_router_notify(XiveNotifier *xn, uint32_t lisn)
return;
}
- /*
- * The IVRE checks the State Bit Cache at this point. We skip the
- * SBC lookup because the state bits of the sources are modeled
- * internally in QEMU.
- */
+ if (!pq_checked) {
+ bool notify;
+ uint8_t pq;
+
+ /* PQ cache lookup */
+ if (xive_router_get_pq(xrtr, eas_blk, eas_idx, &pq)) {
+ /* Set FIR */
+ g_assert_not_reached();
+ }
+
+ notify = xive_esb_trigger(&pq);
+
+ if (xive_router_set_pq(xrtr, eas_blk, eas_idx, &pq)) {
+ /* Set FIR */
+ g_assert_not_reached();
+ }
+
+ if (!notify) {
+ return;
+ }
+ }
if (!xive_eas_is_valid(&eas)) {
qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid LISN %x\n", lisn);
diff --git a/hw/intc/xive2.c b/hw/intc/xive2.c
index 2836bbdc83fc..3720e704227d 100644
--- a/hw/intc/xive2.c
+++ b/hw/intc/xive2.c
@@ -171,6 +171,24 @@ int xive2_router_get_eas(Xive2Router *xrtr, uint8_t eas_blk, uint32_t eas_idx,
return xrc->get_eas(xrtr, eas_blk, eas_idx, eas);
}
+static
+int xive2_router_get_pq(Xive2Router *xrtr, uint8_t eas_blk, uint32_t eas_idx,
+ uint8_t *pq)
+{
+ Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr);
+
+ return xrc->get_pq(xrtr, eas_blk, eas_idx, pq);
+}
+
+static
+int xive2_router_set_pq(Xive2Router *xrtr, uint8_t eas_blk, uint32_t eas_idx,
+ uint8_t *pq)
+{
+ Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr);
+
+ return xrc->set_pq(xrtr, eas_blk, eas_idx, pq);
+}
+
int xive2_router_get_end(Xive2Router *xrtr, uint8_t end_blk, uint32_t end_idx,
Xive2End *end)
{
@@ -480,7 +498,7 @@ do_escalation:
xive_get_field32(END2_W5_ESC_END_DATA, end.w5));
}
-void xive2_router_notify(XiveNotifier *xn, uint32_t lisn)
+void xive2_router_notify(XiveNotifier *xn, uint32_t lisn, bool pq_checked)
{
Xive2Router *xrtr = XIVE2_ROUTER(xn);
uint8_t eas_blk = XIVE_EAS_BLOCK(lisn);
@@ -493,6 +511,28 @@ void xive2_router_notify(XiveNotifier *xn, uint32_t lisn)
return;
}
+ if (!pq_checked) {
+ bool notify;
+ uint8_t pq;
+
+ /* PQ cache lookup */
+ if (xive2_router_get_pq(xrtr, eas_blk, eas_idx, &pq)) {
+ /* Set FIR */
+ g_assert_not_reached();
+ }
+
+ notify = xive_esb_trigger(&pq);
+
+ if (xive2_router_set_pq(xrtr, eas_blk, eas_idx, &pq)) {
+ /* Set FIR */
+ g_assert_not_reached();
+ }
+
+ if (!notify) {
+ return;
+ }
+ }
+
if (!xive2_eas_is_valid(&eas)) {
qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN %x\n", lisn);
return;
diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c
index 5344a6d4a693..58498feace48 100644
--- a/hw/pci-host/pnv_phb4.c
+++ b/hw/pci-host/pnv_phb4.c
@@ -1660,14 +1660,19 @@ static const char *pnv_phb4_root_bus_path(PCIHostState *host_bridge,
return phb->bus_path;
}
-static void pnv_phb4_xive_notify(XiveNotifier *xf, uint32_t srcno)
+static void pnv_phb4_xive_notify(XiveNotifier *xf, uint32_t srcno,
+ bool pq_checked)
{
PnvPHB4 *phb = PNV_PHB4(xf);
uint64_t notif_port = phb->regs[PHB_INT_NOTIFY_ADDR >> 3];
uint32_t offset = phb->regs[PHB_INT_NOTIFY_INDEX >> 3];
- uint64_t data = XIVE_TRIGGER_PQ | offset | srcno;
+ uint64_t data = offset | srcno;
MemTxResult result;
+ if (pq_checked) {
+ data |= XIVE_TRIGGER_PQ;
+ }
+
trace_pnv_phb4_xive_notify(notif_port, data);
address_space_stq_be(&address_space_memory, notif_port, data,
diff --git a/hw/ppc/pnv_psi.c b/hw/ppc/pnv_psi.c
index 737486046d5a..466fb7979887 100644
--- a/hw/ppc/pnv_psi.c
+++ b/hw/ppc/pnv_psi.c
@@ -653,7 +653,7 @@ static const TypeInfo pnv_psi_power8_info = {
#define PSIHB10_ESB_CI_BASE PSIHB9_ESB_CI_BASE
#define PSIHB10_ESB_CI_64K PPC_BIT(1)
-static void pnv_psi_notify(XiveNotifier *xf, uint32_t srcno)
+static void pnv_psi_notify(XiveNotifier *xf, uint32_t srcno, bool pq_checked)
{
PnvPsi *psi = PNV_PSI(xf);
uint64_t notif_port = psi->regs[PSIHB_REG(PSIHB9_ESB_NOTIF_ADDR)];
@@ -662,9 +662,13 @@ static void pnv_psi_notify(XiveNotifier *xf, uint32_t srcno)
uint32_t offset =
(psi->regs[PSIHB_REG(PSIHB9_IVT_OFFSET)] >> PSIHB9_IVT_OFF_SHIFT);
- uint64_t data = XIVE_TRIGGER_PQ | offset | srcno;
+ uint64_t data = offset | srcno;
MemTxResult result;
+ if (pq_checked) {
+ data |= XIVE_TRIGGER_PQ;
+ }
+
if (!valid) {
return;
}
--
2.34.1
^ permalink raw reply related [flat|nested] 89+ messages in thread* [PULL 66/87] ppc/pnv: Add support for PQ offload on PHB5
2022-03-02 11:06 [PULL 00/87] ppc queue Cédric Le Goater
` (64 preceding siblings ...)
2022-03-02 11:07 ` [PULL 65/87] ppc/xive: Add support for PQ state bits offload Cédric Le Goater
@ 2022-03-02 11:07 ` Cédric Le Goater
2022-03-02 11:07 ` [PULL 67/87] ppc/pnv: Add support for PHB5 "Address-based trigger" mode Cédric Le Goater
` (21 subsequent siblings)
87 siblings, 0 replies; 89+ messages in thread
From: Cédric Le Goater @ 2022-03-02 11:07 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Daniel Henrique Barboza, Cédric Le Goater
The PQ_disable configuration bit disables the check done on the PQ
state bits when processing new MSI interrupts. When bit 9 is enabled,
the PHB forwards any MSI trigger to the XIVE interrupt controller
without checking the PQ state bits. The XIVE IC knows from the trigger
message that the PQ bits have not been checked and performs the check
locally.
This configuration bit only applies to MSIs and LSIs are still checked
on the PHB to handle the assertion level.
PQ_disable enablement is a requirement for StoreEOI.
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
include/hw/pci-host/pnv_phb4_regs.h | 1 +
include/hw/ppc/xive.h | 1 +
hw/intc/xive.c | 22 +++++++++++++++++++++-
hw/pci-host/pnv_phb4.c | 9 +++++++++
4 files changed, 32 insertions(+), 1 deletion(-)
diff --git a/include/hw/pci-host/pnv_phb4_regs.h b/include/hw/pci-host/pnv_phb4_regs.h
index 55df2c3e5ece..64f326b7158e 100644
--- a/include/hw/pci-host/pnv_phb4_regs.h
+++ b/include/hw/pci-host/pnv_phb4_regs.h
@@ -225,6 +225,7 @@
/* Fundamental register set B */
#define PHB_VERSION 0x800
#define PHB_CTRLR 0x810
+#define PHB_CTRLR_IRQ_PQ_DISABLE PPC_BIT(9) /* P10 */
#define PHB_CTRLR_IRQ_PGSZ_64K PPC_BIT(11)
#define PHB_CTRLR_IRQ_STORE_EOI PPC_BIT(12)
#define PHB_CTRLR_MMIO_RD_STRICT PPC_BIT(13)
diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h
index 649b58a08f0c..126e4e2c3a17 100644
--- a/include/hw/ppc/xive.h
+++ b/include/hw/ppc/xive.h
@@ -176,6 +176,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(XiveSource, XIVE_SOURCE)
*/
#define XIVE_SRC_H_INT_ESB 0x1 /* ESB managed with hcall H_INT_ESB */
#define XIVE_SRC_STORE_EOI 0x2 /* Store EOI supported */
+#define XIVE_SRC_PQ_DISABLE 0x4 /* Disable check on the PQ state bits */
struct XiveSource {
DeviceState parent;
diff --git a/hw/intc/xive.c b/hw/intc/xive.c
index deb0db21e093..b8e4c7294d59 100644
--- a/hw/intc/xive.c
+++ b/hw/intc/xive.c
@@ -886,6 +886,16 @@ static bool xive_source_lsi_trigger(XiveSource *xsrc, uint32_t srcno)
}
}
+/*
+ * Sources can be configured with PQ offloading in which case the check
+ * on the PQ state bits of MSIs is disabled
+ */
+static bool xive_source_esb_disabled(XiveSource *xsrc, uint32_t srcno)
+{
+ return (xsrc->esb_flags & XIVE_SRC_PQ_DISABLE) &&
+ !xive_source_irq_is_lsi(xsrc, srcno);
+}
+
/*
* Returns whether the event notification should be forwarded.
*/
@@ -895,6 +905,10 @@ static bool xive_source_esb_trigger(XiveSource *xsrc, uint32_t srcno)
assert(srcno < xsrc->nr_irqs);
+ if (xive_source_esb_disabled(xsrc, srcno)) {
+ return true;
+ }
+
ret = xive_esb_trigger(&xsrc->status[srcno]);
if (xive_source_irq_is_lsi(xsrc, srcno) &&
@@ -915,6 +929,11 @@ static bool xive_source_esb_eoi(XiveSource *xsrc, uint32_t srcno)
assert(srcno < xsrc->nr_irqs);
+ if (xive_source_esb_disabled(xsrc, srcno)) {
+ qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid EOI for IRQ %d\n", srcno);
+ return false;
+ }
+
ret = xive_esb_eoi(&xsrc->status[srcno]);
/*
@@ -936,9 +955,10 @@ static bool xive_source_esb_eoi(XiveSource *xsrc, uint32_t srcno)
static void xive_source_notify(XiveSource *xsrc, int srcno)
{
XiveNotifierClass *xnc = XIVE_NOTIFIER_GET_CLASS(xsrc->xive);
+ bool pq_checked = !xive_source_esb_disabled(xsrc, srcno);
if (xnc->notify) {
- xnc->notify(xsrc->xive, srcno, true);
+ xnc->notify(xsrc->xive, srcno, pq_checked);
}
}
diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c
index 58498feace48..0b407ac69ba6 100644
--- a/hw/pci-host/pnv_phb4.c
+++ b/hw/pci-host/pnv_phb4.c
@@ -485,6 +485,15 @@ static void pnv_phb4_update_xsrc(PnvPHB4 *phb)
flags = 0;
}
+ /*
+ * When the PQ disable configuration bit is set, the check on the
+ * PQ state bits is disabled on the PHB side (for MSI only) and it
+ * is performed on the IC side instead.
+ */
+ if (phb->regs[PHB_CTRLR >> 3] & PHB_CTRLR_IRQ_PQ_DISABLE) {
+ flags |= XIVE_SRC_PQ_DISABLE;
+ }
+
phb->xsrc.esb_shift = shift;
phb->xsrc.esb_flags = flags;
--
2.34.1
^ permalink raw reply related [flat|nested] 89+ messages in thread* [PULL 67/87] ppc/pnv: Add support for PHB5 "Address-based trigger" mode
2022-03-02 11:06 [PULL 00/87] ppc queue Cédric Le Goater
` (65 preceding siblings ...)
2022-03-02 11:07 ` [PULL 66/87] ppc/pnv: Add support for PQ offload on PHB5 Cédric Le Goater
@ 2022-03-02 11:07 ` Cédric Le Goater
2022-03-02 11:07 ` [PULL 68/87] pnv/xive2: Introduce new capability bits Cédric Le Goater
` (20 subsequent siblings)
87 siblings, 0 replies; 89+ messages in thread
From: Cédric Le Goater @ 2022-03-02 11:07 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Daniel Henrique Barboza, Cédric Le Goater
When the Address-Based Interrupt Trigger mode is activated, the PHB
maps the interrupt source number into the interrupt command address.
The PHB directly triggers the IC ESB page of the interrupt number and
not the notify page of the IC anymore.
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
include/hw/pci-host/pnv_phb4_regs.h | 2 +
hw/pci-host/pnv_phb4.c | 73 ++++++++++++++++++++++++++---
hw/pci-host/trace-events | 2 +
3 files changed, 71 insertions(+), 6 deletions(-)
diff --git a/include/hw/pci-host/pnv_phb4_regs.h b/include/hw/pci-host/pnv_phb4_regs.h
index 64f326b7158e..4a0d3b28efb3 100644
--- a/include/hw/pci-host/pnv_phb4_regs.h
+++ b/include/hw/pci-host/pnv_phb4_regs.h
@@ -220,12 +220,14 @@
#define PHB_PAPR_ERR_INJ_MASK_MMIO PPC_BITMASK(16, 63)
#define PHB_ETU_ERR_SUMMARY 0x2c8
#define PHB_INT_NOTIFY_ADDR 0x300
+#define PHB_INT_NOTIFY_ADDR_64K PPC_BIT(1) /* P10 */
#define PHB_INT_NOTIFY_INDEX 0x308
/* Fundamental register set B */
#define PHB_VERSION 0x800
#define PHB_CTRLR 0x810
#define PHB_CTRLR_IRQ_PQ_DISABLE PPC_BIT(9) /* P10 */
+#define PHB_CTRLR_IRQ_ABT_MODE PPC_BIT(10) /* P10 */
#define PHB_CTRLR_IRQ_PGSZ_64K PPC_BIT(11)
#define PHB_CTRLR_IRQ_STORE_EOI PPC_BIT(12)
#define PHB_CTRLR_MMIO_RD_STRICT PPC_BIT(13)
diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c
index 0b407ac69ba6..b5b384e9ee4f 100644
--- a/hw/pci-host/pnv_phb4.c
+++ b/hw/pci-host/pnv_phb4.c
@@ -1669,10 +1669,54 @@ static const char *pnv_phb4_root_bus_path(PCIHostState *host_bridge,
return phb->bus_path;
}
-static void pnv_phb4_xive_notify(XiveNotifier *xf, uint32_t srcno,
- bool pq_checked)
+/*
+ * Address base trigger mode (POWER10)
+ *
+ * Trigger directly the IC ESB page
+ */
+static void pnv_phb4_xive_notify_abt(PnvPHB4 *phb, uint32_t srcno,
+ bool pq_checked)
+{
+ uint64_t notif_port = phb->regs[PHB_INT_NOTIFY_ADDR >> 3];
+ uint64_t data = 0; /* trigger data : don't care */
+ hwaddr addr;
+ MemTxResult result;
+ int esb_shift;
+
+ if (notif_port & PHB_INT_NOTIFY_ADDR_64K) {
+ esb_shift = 16;
+ } else {
+ esb_shift = 12;
+ }
+
+ /* Compute the address of the IC ESB management page */
+ addr = (notif_port & ~PHB_INT_NOTIFY_ADDR_64K);
+ addr |= (1ull << (esb_shift + 1)) * srcno;
+ addr |= (1ull << esb_shift);
+
+ /*
+ * When the PQ state bits are checked on the PHB, the associated
+ * PQ state bits on the IC should be ignored. Use the unconditional
+ * trigger offset to inject a trigger on the IC. This is always
+ * the case for LSIs
+ */
+ if (pq_checked) {
+ addr |= XIVE_ESB_INJECT;
+ }
+
+ trace_pnv_phb4_xive_notify_ic(addr, data);
+
+ address_space_stq_be(&address_space_memory, addr, data,
+ MEMTXATTRS_UNSPECIFIED, &result);
+ if (result != MEMTX_OK) {
+ phb_error(phb, "trigger failed @%"HWADDR_PRIx "\n", addr);
+ return;
+ }
+}
+
+static void pnv_phb4_xive_notify_ic(PnvPHB4 *phb, uint32_t srcno,
+ bool pq_checked)
{
- PnvPHB4 *phb = PNV_PHB4(xf);
uint64_t notif_port = phb->regs[PHB_INT_NOTIFY_ADDR >> 3];
uint32_t offset = phb->regs[PHB_INT_NOTIFY_INDEX >> 3];
uint64_t data = offset | srcno;
@@ -1682,7 +1726,7 @@ static void pnv_phb4_xive_notify(XiveNotifier *xf, uint32_t srcno,
data |= XIVE_TRIGGER_PQ;
}
- trace_pnv_phb4_xive_notify(notif_port, data);
+ trace_pnv_phb4_xive_notify_ic(notif_port, data);
address_space_stq_be(&address_space_memory, notif_port, data,
MEMTXATTRS_UNSPECIFIED, &result);
@@ -1692,6 +1736,18 @@ static void pnv_phb4_xive_notify(XiveNotifier *xf, uint32_t srcno,
}
}
+static void pnv_phb4_xive_notify(XiveNotifier *xf, uint32_t srcno,
+ bool pq_checked)
+{
+ PnvPHB4 *phb = PNV_PHB4(xf);
+
+ if (phb->regs[PHB_CTRLR >> 3] & PHB_CTRLR_IRQ_ABT_MODE) {
+ pnv_phb4_xive_notify_abt(phb, srcno, pq_checked);
+ } else {
+ pnv_phb4_xive_notify_ic(phb, srcno, pq_checked);
+ }
+}
+
static Property pnv_phb4_properties[] = {
DEFINE_PROP_UINT32("index", PnvPHB4, phb_id, 0),
DEFINE_PROP_UINT32("chip-id", PnvPHB4, chip_id, 0),
@@ -1858,10 +1914,15 @@ type_init(pnv_phb4_register_types);
void pnv_phb4_pic_print_info(PnvPHB4 *phb, Monitor *mon)
{
+ uint64_t notif_port =
+ phb->regs[PHB_INT_NOTIFY_ADDR >> 3] & ~PHB_INT_NOTIFY_ADDR_64K;
uint32_t offset = phb->regs[PHB_INT_NOTIFY_INDEX >> 3];
+ bool abt = !!(phb->regs[PHB_CTRLR >> 3] & PHB_CTRLR_IRQ_ABT_MODE);
- monitor_printf(mon, "PHB4[%x:%x] Source %08x .. %08x\n",
+ monitor_printf(mon, "PHB4[%x:%x] Source %08x .. %08x %s @%"HWADDR_PRIx"\n",
phb->chip_id, phb->phb_id,
- offset, offset + phb->xsrc.nr_irqs - 1);
+ offset, offset + phb->xsrc.nr_irqs - 1,
+ abt ? "ABT" : "",
+ notif_port);
xive_source_pic_print_info(&phb->xsrc, 0, mon);
}
diff --git a/hw/pci-host/trace-events b/hw/pci-host/trace-events
index 630e9fcc5e77..6e5d8d335525 100644
--- a/hw/pci-host/trace-events
+++ b/hw/pci-host/trace-events
@@ -32,3 +32,5 @@ unin_read(uint64_t addr, uint64_t value) "addr=0x%" PRIx64 " val=0x%"PRIx64
# pnv_phb4.c
pnv_phb4_xive_notify(uint64_t notif_port, uint64_t data) "notif=@0x%"PRIx64" data=0x%"PRIx64
+pnv_phb4_xive_notify_ic(uint64_t addr, uint64_t data) "addr=@0x%"PRIx64" data=0x%"PRIx64
+pnv_phb4_xive_notify_abt(uint64_t notif_port, uint64_t data) "notif=@0x%"PRIx64" data=0x%"PRIx64
--
2.34.1
^ permalink raw reply related [flat|nested] 89+ messages in thread* [PULL 68/87] pnv/xive2: Introduce new capability bits
2022-03-02 11:06 [PULL 00/87] ppc queue Cédric Le Goater
` (66 preceding siblings ...)
2022-03-02 11:07 ` [PULL 67/87] ppc/pnv: Add support for PHB5 "Address-based trigger" mode Cédric Le Goater
@ 2022-03-02 11:07 ` Cédric Le Goater
2022-03-02 11:07 ` [PULL 69/87] ppc/pnv: add XIVE Gen2 TIMA support Cédric Le Goater
` (19 subsequent siblings)
87 siblings, 0 replies; 89+ messages in thread
From: Cédric Le Goater @ 2022-03-02 11:07 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Daniel Henrique Barboza, Cédric Le Goater
These bits control the availability of interrupt features : StoreEOI,
PHB PQ_disable, PHB Address-Based Trigger and the overall XIVE
exploitation mode. These bits can be set at early boot time of the
system to activate/deactivate a feature for testing purposes. The
default value should be '1'.
The 'XIVE exploitation mode' bit is a software bit that skiboot could
use to disable the XIVE OS interface and propose a P8 style XICS
interface instead. There are no plans for that for the moment.
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/intc/pnv_xive2_regs.h | 5 +++++
hw/intc/pnv_xive2.c | 4 ++--
2 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/hw/intc/pnv_xive2_regs.h b/hw/intc/pnv_xive2_regs.h
index d45d17cedcca..a46e5133b560 100644
--- a/hw/intc/pnv_xive2_regs.h
+++ b/hw/intc/pnv_xive2_regs.h
@@ -31,6 +31,11 @@
#define CQ_XIVE_CAP_VP_INT_PRIO_8 3
#define CQ_XIVE_CAP_BLOCK_ID_WIDTH PPC_BITMASK(12, 13)
+#define CQ_XIVE_CAP_PHB_PQ_DISABLE PPC_BIT(56)
+#define CQ_XIVE_CAP_PHB_ABT PPC_BIT(57)
+#define CQ_XIVE_CAP_EXPLOITATION_MODE PPC_BIT(58)
+#define CQ_XIVE_CAP_STORE_EOI PPC_BIT(59)
+
/* XIVE2 Configuration */
#define X_CQ_XIVE_CFG 0x03
#define CQ_XIVE_CFG 0x018
diff --git a/hw/intc/pnv_xive2.c b/hw/intc/pnv_xive2.c
index 1fa89c779287..e22049424f37 100644
--- a/hw/intc/pnv_xive2.c
+++ b/hw/intc/pnv_xive2.c
@@ -1709,9 +1709,9 @@ static const MemoryRegionOps pnv_xive2_nvpg_ops = {
};
/*
- * POWER10 default capabilities: 0x2000120076f00000
+ * POWER10 default capabilities: 0x2000120076f000FC
*/
-#define PNV_XIVE2_CAPABILITIES 0x2000120076f00000
+#define PNV_XIVE2_CAPABILITIES 0x2000120076f000FC
/*
* POWER10 default configuration: 0x0030000033000000
--
2.34.1
^ permalink raw reply related [flat|nested] 89+ messages in thread* [PULL 69/87] ppc/pnv: add XIVE Gen2 TIMA support
2022-03-02 11:06 [PULL 00/87] ppc queue Cédric Le Goater
` (67 preceding siblings ...)
2022-03-02 11:07 ` [PULL 68/87] pnv/xive2: Introduce new capability bits Cédric Le Goater
@ 2022-03-02 11:07 ` Cédric Le Goater
2022-03-02 11:07 ` [PULL 70/87] pnv/xive2: Add support XIVE2 P9-compat mode (or Gen1) Cédric Le Goater
` (18 subsequent siblings)
87 siblings, 0 replies; 89+ messages in thread
From: Cédric Le Goater @ 2022-03-02 11:07 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Daniel Henrique Barboza, Cédric Le Goater
Only the CAM line updates done by the hypervisor are specific to
POWER10. Instead of duplicating the TM ops table, we handle these
commands locally under the PowerNV XIVE2 model.
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
include/hw/ppc/xive2.h | 8 ++++
hw/intc/pnv_xive2.c | 27 +++++++++++-
hw/intc/xive2.c | 95 ++++++++++++++++++++++++++++++++++++++++++
3 files changed, 128 insertions(+), 2 deletions(-)
diff --git a/include/hw/ppc/xive2.h b/include/hw/ppc/xive2.h
index eb255b6dd8f3..c8c4505b51e0 100644
--- a/include/hw/ppc/xive2.h
+++ b/include/hw/ppc/xive2.h
@@ -87,5 +87,13 @@ typedef struct Xive2EndSource {
Xive2Router *xrtr;
} Xive2EndSource;
+/*
+ * XIVE2 Thread Interrupt Management Area (POWER10)
+ */
+
+void xive2_tm_push_os_ctx(XivePresenter *xptr, XiveTCTX *tctx, hwaddr offset,
+ uint64_t value, unsigned size);
+uint64_t xive2_tm_pull_os_ctx(XivePresenter *xptr, XiveTCTX *tctx,
+ hwaddr offset, unsigned size);
#endif /* PPC_XIVE2_H */
diff --git a/hw/intc/pnv_xive2.c b/hw/intc/pnv_xive2.c
index e22049424f37..012b238fd037 100644
--- a/hw/intc/pnv_xive2.c
+++ b/hw/intc/pnv_xive2.c
@@ -1611,15 +1611,32 @@ static const MemoryRegionOps pnv_xive2_ic_tm_indirect_ops = {
* TIMA ops
*/
+/*
+ * Special TIMA offsets to handle accesses in a POWER10 way.
+ *
+ * Only the CAM line updates done by the hypervisor should be handled
+ * specifically.
+ */
+#define HV_PAGE_OFFSET (XIVE_TM_HV_PAGE << TM_SHIFT)
+#define HV_PUSH_OS_CTX_OFFSET (HV_PAGE_OFFSET | (TM_QW1_OS + TM_WORD2))
+#define HV_PULL_OS_CTX_OFFSET (HV_PAGE_OFFSET | TM_SPC_PULL_OS_CTX)
+
static void pnv_xive2_tm_write(void *opaque, hwaddr offset,
uint64_t value, unsigned size)
{
PowerPCCPU *cpu = POWERPC_CPU(current_cpu);
PnvXive2 *xive = pnv_xive2_tm_get_xive(cpu);
XiveTCTX *tctx = XIVE_TCTX(pnv_cpu_state(cpu)->intc);
+ XivePresenter *xptr = XIVE_PRESENTER(xive);
+
+ /* TODO: should we switch the TM ops table instead ? */
+ if (offset == HV_PUSH_OS_CTX_OFFSET) {
+ xive2_tm_push_os_ctx(xptr, tctx, offset, value, size);
+ return;
+ }
/* Other TM ops are the same as XIVE1 */
- xive_tctx_tm_write(XIVE_PRESENTER(xive), tctx, offset, value, size);
+ xive_tctx_tm_write(xptr, tctx, offset, value, size);
}
static uint64_t pnv_xive2_tm_read(void *opaque, hwaddr offset, unsigned size)
@@ -1627,9 +1644,15 @@ static uint64_t pnv_xive2_tm_read(void *opaque, hwaddr offset, unsigned size)
PowerPCCPU *cpu = POWERPC_CPU(current_cpu);
PnvXive2 *xive = pnv_xive2_tm_get_xive(cpu);
XiveTCTX *tctx = XIVE_TCTX(pnv_cpu_state(cpu)->intc);
+ XivePresenter *xptr = XIVE_PRESENTER(xive);
+
+ /* TODO: should we switch the TM ops table instead ? */
+ if (offset == HV_PULL_OS_CTX_OFFSET) {
+ return xive2_tm_pull_os_ctx(xptr, tctx, offset, size);
+ }
/* Other TM ops are the same as XIVE1 */
- return xive_tctx_tm_read(XIVE_PRESENTER(xive), tctx, offset, size);
+ return xive_tctx_tm_read(xptr, tctx, offset, size);
}
static const MemoryRegionOps pnv_xive2_tm_ops = {
diff --git a/hw/intc/xive2.c b/hw/intc/xive2.c
index 3720e704227d..048b98dbbe90 100644
--- a/hw/intc/xive2.c
+++ b/hw/intc/xive2.c
@@ -159,6 +159,101 @@ static void xive2_end_enqueue(Xive2End *end, uint32_t data)
}
end->w1 = xive_set_field32(END2_W1_PAGE_OFF, end->w1, qindex);
}
+
+/*
+ * XIVE Thread Interrupt Management Area (TIMA) - Gen2 mode
+ */
+
+static void xive2_os_cam_decode(uint32_t cam, uint8_t *nvp_blk,
+ uint32_t *nvp_idx, bool *vo)
+{
+ *nvp_blk = xive2_nvp_blk(cam);
+ *nvp_idx = xive2_nvp_idx(cam);
+ *vo = !!(cam & TM2_QW1W2_VO);
+}
+
+uint64_t xive2_tm_pull_os_ctx(XivePresenter *xptr, XiveTCTX *tctx,
+ hwaddr offset, unsigned size)
+{
+ uint32_t qw1w2 = xive_tctx_word2(&tctx->regs[TM_QW1_OS]);
+ uint32_t qw1w2_new;
+ uint32_t cam = be32_to_cpu(qw1w2);
+ uint8_t nvp_blk;
+ uint32_t nvp_idx;
+ bool vo;
+
+ xive2_os_cam_decode(cam, &nvp_blk, &nvp_idx, &vo);
+
+ if (!vo) {
+ qemu_log_mask(LOG_GUEST_ERROR, "XIVE: pulling invalid NVP %x/%x !?\n",
+ nvp_blk, nvp_idx);
+ }
+
+ /* Invalidate CAM line */
+ qw1w2_new = xive_set_field32(TM2_QW1W2_VO, qw1w2, 0);
+ memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &qw1w2_new, 4);
+
+ return qw1w2;
+}
+
+static void xive2_tctx_need_resend(Xive2Router *xrtr, XiveTCTX *tctx,
+ uint8_t nvp_blk, uint32_t nvp_idx)
+{
+ Xive2Nvp nvp;
+ uint8_t ipb;
+ uint8_t cppr = 0;
+
+ /*
+ * Grab the associated thread interrupt context registers in the
+ * associated NVP
+ */
+ if (xive2_router_get_nvp(xrtr, nvp_blk, nvp_idx, &nvp)) {
+ qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No NVP %x/%x\n",
+ nvp_blk, nvp_idx);
+ return;
+ }
+
+ if (!xive2_nvp_is_valid(&nvp)) {
+ qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid NVP %x/%x\n",
+ nvp_blk, nvp_idx);
+ return;
+ }
+
+ ipb = xive_get_field32(NVP2_W2_IPB, nvp.w2);
+ if (ipb) {
+ nvp.w2 = xive_set_field32(NVP2_W2_IPB, nvp.w2, 0);
+ xive2_router_write_nvp(xrtr, nvp_blk, nvp_idx, &nvp, 2);
+ }
+
+ /* An IPB or CPPR change can trigger a resend */
+ if (ipb || cppr) {
+ xive_tctx_ipb_update(tctx, TM_QW1_OS, ipb);
+ }
+}
+
+/*
+ * Updating the OS CAM line can trigger a resend of interrupt
+ */
+void xive2_tm_push_os_ctx(XivePresenter *xptr, XiveTCTX *tctx,
+ hwaddr offset, uint64_t value, unsigned size)
+{
+ uint32_t cam = value;
+ uint32_t qw1w2 = cpu_to_be32(cam);
+ uint8_t nvp_blk;
+ uint32_t nvp_idx;
+ bool vo;
+
+ xive2_os_cam_decode(cam, &nvp_blk, &nvp_idx, &vo);
+
+ /* First update the thead context */
+ memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &qw1w2, 4);
+
+ /* Check the interrupt pending bits */
+ if (vo) {
+ xive2_tctx_need_resend(XIVE2_ROUTER(xptr), tctx, nvp_blk, nvp_idx);
+ }
+}
+
/*
* XIVE Router (aka. Virtualization Controller or IVRE)
*/
--
2.34.1
^ permalink raw reply related [flat|nested] 89+ messages in thread* [PULL 70/87] pnv/xive2: Add support XIVE2 P9-compat mode (or Gen1)
2022-03-02 11:06 [PULL 00/87] ppc queue Cédric Le Goater
` (68 preceding siblings ...)
2022-03-02 11:07 ` [PULL 69/87] ppc/pnv: add XIVE Gen2 TIMA support Cédric Le Goater
@ 2022-03-02 11:07 ` Cédric Le Goater
2022-03-02 11:07 ` [PULL 71/87] xive2: Add a get_config() handler for the router configuration Cédric Le Goater
` (17 subsequent siblings)
87 siblings, 0 replies; 89+ messages in thread
From: Cédric Le Goater @ 2022-03-02 11:07 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Daniel Henrique Barboza, Cédric Le Goater
The thread interrupt management area (TIMA) is a set of pages mapped
in the Hypervisor and in the guest OS address space giving access to
the interrupt thread context registers for interrupt management, ACK,
EOI, CPPR, etc.
XIVE2 changes slightly the TIMA layout with extra bits for the new
features, larger CAM lines and the controller provides configuration
switches for backward compatibility. This is called the XIVE2
P9-compat mode, of Gen1 TIMA. It impacts the layout of the TIMA and
the availability of the internal features associated with it,
Automatic Save & Restore for instance. Using a P9 layout also means
setting the controller in such a mode at init time.
As the OPAL driver initializes the XIVE2 controller with a XIVE2/P10
TIMA directly, the XIVE2 model only has a simple support for the
compat mode in the OS TIMA.
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/intc/pnv_xive2_regs.h | 6 ++++++
hw/intc/pnv_xive2.c | 22 +++++++++++++++++-----
2 files changed, 23 insertions(+), 5 deletions(-)
diff --git a/hw/intc/pnv_xive2_regs.h b/hw/intc/pnv_xive2_regs.h
index a46e5133b560..d261766cf5fb 100644
--- a/hw/intc/pnv_xive2_regs.h
+++ b/hw/intc/pnv_xive2_regs.h
@@ -60,6 +60,12 @@
#define CQ_XIVE_CFG_HYP_HARD_BLKID_OVERRIDE PPC_BIT(16)
#define CQ_XIVE_CFG_HYP_HARD_BLOCK_ID PPC_BITMASK(17, 23)
+#define CQ_XIVE_CFG_GEN1_TIMA_OS PPC_BIT(24)
+#define CQ_XIVE_CFG_GEN1_TIMA_HYP PPC_BIT(25)
+#define CQ_XIVE_CFG_GEN1_TIMA_HYP_BLK0 PPC_BIT(26) /* 0 if bit[25]=0 */
+#define CQ_XIVE_CFG_GEN1_TIMA_CROWD_DIS PPC_BIT(27) /* 0 if bit[25]=0 */
+#define CQ_XIVE_CFG_GEN1_END_ESX PPC_BIT(28)
+
/* Interrupt Controller Base Address Register - 512 pages (32M) */
#define X_CQ_IC_BAR 0x08
#define CQ_IC_BAR 0x040
diff --git a/hw/intc/pnv_xive2.c b/hw/intc/pnv_xive2.c
index 012b238fd037..5df378dde4b6 100644
--- a/hw/intc/pnv_xive2.c
+++ b/hw/intc/pnv_xive2.c
@@ -445,6 +445,8 @@ static int pnv_xive2_match_nvt(XivePresenter *xptr, uint8_t format,
PnvChip *chip = xive->chip;
int count = 0;
int i, j;
+ bool gen1_tima_os =
+ xive->cq_regs[CQ_XIVE_CFG >> 3] & CQ_XIVE_CFG_GEN1_TIMA_OS;
for (i = 0; i < chip->nr_cores; i++) {
PnvCore *pc = chip->cores[i];
@@ -461,9 +463,15 @@ static int pnv_xive2_match_nvt(XivePresenter *xptr, uint8_t format,
tctx = XIVE_TCTX(pnv_cpu_state(cpu)->intc);
- ring = xive2_presenter_tctx_match(xptr, tctx, format, nvt_blk,
- nvt_idx, cam_ignore,
- logic_serv);
+ if (gen1_tima_os) {
+ ring = xive_presenter_tctx_match(xptr, tctx, format, nvt_blk,
+ nvt_idx, cam_ignore,
+ logic_serv);
+ } else {
+ ring = xive2_presenter_tctx_match(xptr, tctx, format, nvt_blk,
+ nvt_idx, cam_ignore,
+ logic_serv);
+ }
/*
* Save the context and follow on to catch duplicates,
@@ -1628,9 +1636,11 @@ static void pnv_xive2_tm_write(void *opaque, hwaddr offset,
PnvXive2 *xive = pnv_xive2_tm_get_xive(cpu);
XiveTCTX *tctx = XIVE_TCTX(pnv_cpu_state(cpu)->intc);
XivePresenter *xptr = XIVE_PRESENTER(xive);
+ bool gen1_tima_os =
+ xive->cq_regs[CQ_XIVE_CFG >> 3] & CQ_XIVE_CFG_GEN1_TIMA_OS;
/* TODO: should we switch the TM ops table instead ? */
- if (offset == HV_PUSH_OS_CTX_OFFSET) {
+ if (!gen1_tima_os && offset == HV_PUSH_OS_CTX_OFFSET) {
xive2_tm_push_os_ctx(xptr, tctx, offset, value, size);
return;
}
@@ -1645,9 +1655,11 @@ static uint64_t pnv_xive2_tm_read(void *opaque, hwaddr offset, unsigned size)
PnvXive2 *xive = pnv_xive2_tm_get_xive(cpu);
XiveTCTX *tctx = XIVE_TCTX(pnv_cpu_state(cpu)->intc);
XivePresenter *xptr = XIVE_PRESENTER(xive);
+ bool gen1_tima_os =
+ xive->cq_regs[CQ_XIVE_CFG >> 3] & CQ_XIVE_CFG_GEN1_TIMA_OS;
/* TODO: should we switch the TM ops table instead ? */
- if (offset == HV_PULL_OS_CTX_OFFSET) {
+ if (!gen1_tima_os && offset == HV_PULL_OS_CTX_OFFSET) {
return xive2_tm_pull_os_ctx(xptr, tctx, offset, size);
}
--
2.34.1
^ permalink raw reply related [flat|nested] 89+ messages in thread* [PULL 71/87] xive2: Add a get_config() handler for the router configuration
2022-03-02 11:06 [PULL 00/87] ppc queue Cédric Le Goater
` (69 preceding siblings ...)
2022-03-02 11:07 ` [PULL 70/87] pnv/xive2: Add support XIVE2 P9-compat mode (or Gen1) Cédric Le Goater
@ 2022-03-02 11:07 ` Cédric Le Goater
2022-03-02 11:07 ` [PULL 72/87] pnv/xive2: Add support for automatic save&restore Cédric Le Goater
` (16 subsequent siblings)
87 siblings, 0 replies; 89+ messages in thread
From: Cédric Le Goater @ 2022-03-02 11:07 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Daniel Henrique Barboza, Cédric Le Goater
Add GEN1 config even if we don't use it yet in the core framework.
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
include/hw/ppc/xive2.h | 8 ++++++++
hw/intc/pnv_xive2.c | 13 +++++++++++++
hw/intc/xive2.c | 7 +++++++
3 files changed, 28 insertions(+)
diff --git a/include/hw/ppc/xive2.h b/include/hw/ppc/xive2.h
index c8c4505b51e0..a598393b65dc 100644
--- a/include/hw/ppc/xive2.h
+++ b/include/hw/ppc/xive2.h
@@ -25,6 +25,12 @@ typedef struct Xive2Router {
#define TYPE_XIVE2_ROUTER "xive2-router"
OBJECT_DECLARE_TYPE(Xive2Router, Xive2RouterClass, XIVE2_ROUTER);
+/*
+ * Configuration flags
+ */
+
+#define XIVE2_GEN1_TIMA_OS 0x00000001
+
typedef struct Xive2RouterClass {
SysBusDeviceClass parent;
@@ -44,6 +50,7 @@ typedef struct Xive2RouterClass {
int (*write_nvp)(Xive2Router *xrtr, uint8_t nvp_blk, uint32_t nvp_idx,
Xive2Nvp *nvp, uint8_t word_number);
uint8_t (*get_block_id)(Xive2Router *xrtr);
+ uint32_t (*get_config)(Xive2Router *xrtr);
} Xive2RouterClass;
int xive2_router_get_eas(Xive2Router *xrtr, uint8_t eas_blk, uint32_t eas_idx,
@@ -56,6 +63,7 @@ int xive2_router_get_nvp(Xive2Router *xrtr, uint8_t nvp_blk, uint32_t nvp_idx,
Xive2Nvp *nvp);
int xive2_router_write_nvp(Xive2Router *xrtr, uint8_t nvp_blk, uint32_t nvp_idx,
Xive2Nvp *nvp, uint8_t word_number);
+uint32_t xive2_router_get_config(Xive2Router *xrtr);
void xive2_router_notify(XiveNotifier *xn, uint32_t lisn, bool pq_checked);
diff --git a/hw/intc/pnv_xive2.c b/hw/intc/pnv_xive2.c
index 5df378dde4b6..963f6ad2da8e 100644
--- a/hw/intc/pnv_xive2.c
+++ b/hw/intc/pnv_xive2.c
@@ -426,6 +426,18 @@ static int pnv_xive2_get_eas(Xive2Router *xrtr, uint8_t blk, uint32_t idx,
return pnv_xive2_vst_read(xive, VST_EAS, blk, idx, eas);
}
+static uint32_t pnv_xive2_get_config(Xive2Router *xrtr)
+{
+ PnvXive2 *xive = PNV_XIVE2(xrtr);
+ uint32_t cfg = 0;
+
+ if (xive->cq_regs[CQ_XIVE_CFG >> 3] & CQ_XIVE_CFG_GEN1_TIMA_OS) {
+ cfg |= XIVE2_GEN1_TIMA_OS;
+ }
+
+ return cfg;
+}
+
static bool pnv_xive2_is_cpu_enabled(PnvXive2 *xive, PowerPCCPU *cpu)
{
int pir = ppc_cpu_pir(cpu);
@@ -1950,6 +1962,7 @@ static void pnv_xive2_class_init(ObjectClass *klass, void *data)
xrc->write_end = pnv_xive2_write_end;
xrc->get_nvp = pnv_xive2_get_nvp;
xrc->write_nvp = pnv_xive2_write_nvp;
+ xrc->get_config = pnv_xive2_get_config;
xrc->get_block_id = pnv_xive2_get_block_id;
xnc->notify = pnv_xive2_notify;
diff --git a/hw/intc/xive2.c b/hw/intc/xive2.c
index 048b98dbbe90..c45422542459 100644
--- a/hw/intc/xive2.c
+++ b/hw/intc/xive2.c
@@ -20,6 +20,13 @@
#include "hw/ppc/xive2.h"
#include "hw/ppc/xive2_regs.h"
+uint32_t xive2_router_get_config(Xive2Router *xrtr)
+{
+ Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr);
+
+ return xrc->get_config(xrtr);
+}
+
void xive2_eas_pic_print_info(Xive2Eas *eas, uint32_t lisn, Monitor *mon)
{
if (!xive2_eas_is_valid(eas)) {
--
2.34.1
^ permalink raw reply related [flat|nested] 89+ messages in thread* [PULL 72/87] pnv/xive2: Add support for automatic save&restore
2022-03-02 11:06 [PULL 00/87] ppc queue Cédric Le Goater
` (70 preceding siblings ...)
2022-03-02 11:07 ` [PULL 71/87] xive2: Add a get_config() handler for the router configuration Cédric Le Goater
@ 2022-03-02 11:07 ` Cédric Le Goater
2022-03-02 11:07 ` [PULL 73/87] pnv/xive2: Add support for 8bits thread id Cédric Le Goater
` (15 subsequent siblings)
87 siblings, 0 replies; 89+ messages in thread
From: Cédric Le Goater @ 2022-03-02 11:07 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Daniel Henrique Barboza, Cédric Le Goater
The XIVE interrupt controller on P10 can automatically save and
restore the state of the interrupt registers under the internal NVP
structure representing the VCPU. This saves a costly store/load in
guest entries and exits.
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/intc/pnv_xive2_regs.h | 3 +
include/hw/ppc/xive2.h | 1 +
include/hw/ppc/xive2_regs.h | 12 ++++
hw/intc/pnv_xive2.c | 18 +++++-
hw/intc/xive2.c | 126 ++++++++++++++++++++++++++++++++++--
5 files changed, 154 insertions(+), 6 deletions(-)
diff --git a/hw/intc/pnv_xive2_regs.h b/hw/intc/pnv_xive2_regs.h
index d261766cf5fb..0c096e4adb62 100644
--- a/hw/intc/pnv_xive2_regs.h
+++ b/hw/intc/pnv_xive2_regs.h
@@ -30,6 +30,7 @@
#define CQ_XIVE_CAP_VP_INT_PRIO_4_8 2
#define CQ_XIVE_CAP_VP_INT_PRIO_8 3
#define CQ_XIVE_CAP_BLOCK_ID_WIDTH PPC_BITMASK(12, 13)
+#define CQ_XIVE_CAP_VP_SAVE_RESTORE PPC_BIT(38)
#define CQ_XIVE_CAP_PHB_PQ_DISABLE PPC_BIT(56)
#define CQ_XIVE_CAP_PHB_ABT PPC_BIT(57)
@@ -65,6 +66,8 @@
#define CQ_XIVE_CFG_GEN1_TIMA_HYP_BLK0 PPC_BIT(26) /* 0 if bit[25]=0 */
#define CQ_XIVE_CFG_GEN1_TIMA_CROWD_DIS PPC_BIT(27) /* 0 if bit[25]=0 */
#define CQ_XIVE_CFG_GEN1_END_ESX PPC_BIT(28)
+#define CQ_XIVE_CFG_EN_VP_SAVE_RESTORE PPC_BIT(38) /* 0 if bit[25]=1 */
+#define CQ_XIVE_CFG_EN_VP_SAVE_REST_STRICT PPC_BIT(39) /* 0 if bit[25]=1 */
/* Interrupt Controller Base Address Register - 512 pages (32M) */
#define X_CQ_IC_BAR 0x08
diff --git a/include/hw/ppc/xive2.h b/include/hw/ppc/xive2.h
index a598393b65dc..296a2d949498 100644
--- a/include/hw/ppc/xive2.h
+++ b/include/hw/ppc/xive2.h
@@ -30,6 +30,7 @@ OBJECT_DECLARE_TYPE(Xive2Router, Xive2RouterClass, XIVE2_ROUTER);
*/
#define XIVE2_GEN1_TIMA_OS 0x00000001
+#define XIVE2_VP_SAVE_RESTORE 0x00000002
typedef struct Xive2RouterClass {
SysBusDeviceClass parent;
diff --git a/include/hw/ppc/xive2_regs.h b/include/hw/ppc/xive2_regs.h
index b6d36204e6b9..14605bd458f8 100644
--- a/include/hw/ppc/xive2_regs.h
+++ b/include/hw/ppc/xive2_regs.h
@@ -20,10 +20,13 @@
#define TM2_QW0W2_VU PPC_BIT32(0)
#define TM2_QW0W2_LOGIC_SERV PPC_BITMASK32(4, 31)
#define TM2_QW1W2_VO PPC_BIT32(0)
+#define TM2_QW1W2_HO PPC_BIT32(1)
#define TM2_QW1W2_OS_CAM PPC_BITMASK32(4, 31)
#define TM2_QW2W2_VP PPC_BIT32(0)
+#define TM2_QW2W2_HP PPC_BIT32(1)
#define TM2_QW2W2_POOL_CAM PPC_BITMASK32(4, 31)
#define TM2_QW3W2_VT PPC_BIT32(0)
+#define TM2_QW3W2_HT PPC_BIT32(1)
#define TM2_QW3W2_LP PPC_BIT32(6)
#define TM2_QW3W2_LE PPC_BIT32(7)
@@ -137,10 +140,17 @@ void xive2_end_eas_pic_print_info(Xive2End *end, uint32_t end_idx,
typedef struct Xive2Nvp {
uint32_t w0;
#define NVP2_W0_VALID PPC_BIT32(0)
+#define NVP2_W0_HW PPC_BIT32(7)
#define NVP2_W0_ESC_END PPC_BIT32(25) /* 'N' bit 0:ESB 1:END */
uint32_t w1;
+#define NVP2_W1_CO PPC_BIT32(13)
+#define NVP2_W1_CO_PRIV PPC_BITMASK32(14, 15)
+#define NVP2_W1_CO_THRID_VALID PPC_BIT32(16)
+#define NVP2_W1_CO_THRID PPC_BITMASK32(17, 31)
uint32_t w2;
+#define NVP2_W2_CPPR PPC_BITMASK32(0, 7)
#define NVP2_W2_IPB PPC_BITMASK32(8, 15)
+#define NVP2_W2_LSMFB PPC_BITMASK32(16, 23)
uint32_t w3;
uint32_t w4;
#define NVP2_W4_ESC_ESB_BLOCK PPC_BITMASK32(0, 3) /* N:0 */
@@ -156,6 +166,8 @@ typedef struct Xive2Nvp {
} Xive2Nvp;
#define xive2_nvp_is_valid(nvp) (be32_to_cpu((nvp)->w0) & NVP2_W0_VALID)
+#define xive2_nvp_is_hw(nvp) (be32_to_cpu((nvp)->w0) & NVP2_W0_HW)
+#define xive2_nvp_is_co(nvp) (be32_to_cpu((nvp)->w1) & NVP2_W1_CO)
/*
* The VP number space in a block is defined by the END2_W6_VP_OFFSET
diff --git a/hw/intc/pnv_xive2.c b/hw/intc/pnv_xive2.c
index 963f6ad2da8e..b51571c6034f 100644
--- a/hw/intc/pnv_xive2.c
+++ b/hw/intc/pnv_xive2.c
@@ -435,6 +435,10 @@ static uint32_t pnv_xive2_get_config(Xive2Router *xrtr)
cfg |= XIVE2_GEN1_TIMA_OS;
}
+ if (xive->cq_regs[CQ_XIVE_CFG >> 3] & CQ_XIVE_CFG_EN_VP_SAVE_RESTORE) {
+ cfg |= XIVE2_VP_SAVE_RESTORE;
+ }
+
return cfg;
}
@@ -2000,9 +2004,21 @@ static void xive2_nvp_pic_print_info(Xive2Nvp *nvp, uint32_t nvp_idx,
return;
}
- monitor_printf(mon, " %08x end:%02x/%04x IPB:%02x\n",
+ monitor_printf(mon, " %08x end:%02x/%04x IPB:%02x",
nvp_idx, eq_blk, eq_idx,
xive_get_field32(NVP2_W2_IPB, nvp->w2));
+ /*
+ * When the NVP is HW controlled, more fields are updated
+ */
+ if (xive2_nvp_is_hw(nvp)) {
+ monitor_printf(mon, " CPPR:%02x",
+ xive_get_field32(NVP2_W2_CPPR, nvp->w2));
+ if (xive2_nvp_is_co(nvp)) {
+ monitor_printf(mon, " CO:%04x",
+ xive_get_field32(NVP2_W1_CO_THRID, nvp->w1));
+ }
+ }
+ monitor_printf(mon, "\n");
}
/*
diff --git a/hw/intc/xive2.c b/hw/intc/xive2.c
index c45422542459..fd9cfebd782d 100644
--- a/hw/intc/xive2.c
+++ b/hw/intc/xive2.c
@@ -169,27 +169,92 @@ static void xive2_end_enqueue(Xive2End *end, uint32_t data)
/*
* XIVE Thread Interrupt Management Area (TIMA) - Gen2 mode
+ *
+ * TIMA Gen2 VP “save & restore” (S&R) indicated by H bit next to V bit
+ *
+ * - if a context is enabled with the H bit set, the VP context
+ * information is retrieved from the NVP structure (“check out”)
+ * and stored back on a context pull (“check in”), the SW receives
+ * the same context pull information as on P9
+ *
+ * - the H bit cannot be changed while the V bit is set, i.e. a
+ * context cannot be set up in the TIMA and then be “pushed” into
+ * the NVP by changing the H bit while the context is enabled
*/
+static void xive2_tctx_save_os_ctx(Xive2Router *xrtr, XiveTCTX *tctx,
+ uint8_t nvp_blk, uint32_t nvp_idx)
+{
+ CPUPPCState *env = &POWERPC_CPU(tctx->cs)->env;
+ uint32_t pir = env->spr_cb[SPR_PIR].default_value;
+ Xive2Nvp nvp;
+ uint8_t *regs = &tctx->regs[TM_QW1_OS];
+
+ if (xive2_router_get_nvp(xrtr, nvp_blk, nvp_idx, &nvp)) {
+ qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No NVP %x/%x\n",
+ nvp_blk, nvp_idx);
+ return;
+ }
+
+ if (!xive2_nvp_is_valid(&nvp)) {
+ qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid NVP %x/%x\n",
+ nvp_blk, nvp_idx);
+ return;
+ }
+
+ if (!xive2_nvp_is_hw(&nvp)) {
+ qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVP %x/%x is not HW owned\n",
+ nvp_blk, nvp_idx);
+ return;
+ }
+
+ if (!xive2_nvp_is_co(&nvp)) {
+ qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVP %x/%x is not checkout\n",
+ nvp_blk, nvp_idx);
+ return;
+ }
+
+ if (xive_get_field32(NVP2_W1_CO_THRID_VALID, nvp.w1) &&
+ xive_get_field32(NVP2_W1_CO_THRID, nvp.w1) != pir) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "XIVE: NVP %x/%x invalid checkout Thread %x\n",
+ nvp_blk, nvp_idx, pir);
+ return;
+ }
+
+ nvp.w2 = xive_set_field32(NVP2_W2_IPB, nvp.w2, regs[TM_IPB]);
+ nvp.w2 = xive_set_field32(NVP2_W2_CPPR, nvp.w2, regs[TM_CPPR]);
+ nvp.w2 = xive_set_field32(NVP2_W2_LSMFB, nvp.w2, regs[TM_LSMFB]);
+ xive2_router_write_nvp(xrtr, nvp_blk, nvp_idx, &nvp, 2);
+
+ nvp.w1 = xive_set_field32(NVP2_W1_CO, nvp.w1, 0);
+ /* NVP2_W1_CO_THRID_VALID only set once */
+ nvp.w1 = xive_set_field32(NVP2_W1_CO_THRID, nvp.w1, 0xFFFF);
+ xive2_router_write_nvp(xrtr, nvp_blk, nvp_idx, &nvp, 1);
+}
+
static void xive2_os_cam_decode(uint32_t cam, uint8_t *nvp_blk,
- uint32_t *nvp_idx, bool *vo)
+ uint32_t *nvp_idx, bool *vo, bool *ho)
{
*nvp_blk = xive2_nvp_blk(cam);
*nvp_idx = xive2_nvp_idx(cam);
*vo = !!(cam & TM2_QW1W2_VO);
+ *ho = !!(cam & TM2_QW1W2_HO);
}
uint64_t xive2_tm_pull_os_ctx(XivePresenter *xptr, XiveTCTX *tctx,
hwaddr offset, unsigned size)
{
+ Xive2Router *xrtr = XIVE2_ROUTER(xptr);
uint32_t qw1w2 = xive_tctx_word2(&tctx->regs[TM_QW1_OS]);
uint32_t qw1w2_new;
uint32_t cam = be32_to_cpu(qw1w2);
uint8_t nvp_blk;
uint32_t nvp_idx;
bool vo;
+ bool do_save;
- xive2_os_cam_decode(cam, &nvp_blk, &nvp_idx, &vo);
+ xive2_os_cam_decode(cam, &nvp_blk, &nvp_idx, &vo, &do_save);
if (!vo) {
qemu_log_mask(LOG_GUEST_ERROR, "XIVE: pulling invalid NVP %x/%x !?\n",
@@ -200,11 +265,54 @@ uint64_t xive2_tm_pull_os_ctx(XivePresenter *xptr, XiveTCTX *tctx,
qw1w2_new = xive_set_field32(TM2_QW1W2_VO, qw1w2, 0);
memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &qw1w2_new, 4);
+ if (xive2_router_get_config(xrtr) & XIVE2_VP_SAVE_RESTORE && do_save) {
+ xive2_tctx_save_os_ctx(xrtr, tctx, nvp_blk, nvp_idx);
+ }
+
return qw1w2;
}
+static uint8_t xive2_tctx_restore_os_ctx(Xive2Router *xrtr, XiveTCTX *tctx,
+ uint8_t nvp_blk, uint32_t nvp_idx,
+ Xive2Nvp *nvp)
+{
+ CPUPPCState *env = &POWERPC_CPU(tctx->cs)->env;
+ uint32_t pir = env->spr_cb[SPR_PIR].default_value;
+ uint8_t cppr;
+
+ if (!xive2_nvp_is_hw(nvp)) {
+ qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVP %x/%x is not HW owned\n",
+ nvp_blk, nvp_idx);
+ return 0;
+ }
+
+ cppr = xive_get_field32(NVP2_W2_CPPR, nvp->w2);
+ nvp->w2 = xive_set_field32(NVP2_W2_CPPR, nvp->w2, 0);
+ xive2_router_write_nvp(xrtr, nvp_blk, nvp_idx, nvp, 2);
+
+ tctx->regs[TM_QW1_OS + TM_CPPR] = cppr;
+ /* we don't model LSMFB */
+
+ nvp->w1 = xive_set_field32(NVP2_W1_CO, nvp->w1, 1);
+ nvp->w1 = xive_set_field32(NVP2_W1_CO_THRID_VALID, nvp->w1, 1);
+ nvp->w1 = xive_set_field32(NVP2_W1_CO_THRID, nvp->w1, pir);
+
+ /*
+ * Checkout privilege: 0:OS, 1:Pool, 2:Hard
+ *
+ * TODO: we only support OS push/pull
+ */
+ nvp->w1 = xive_set_field32(NVP2_W1_CO_PRIV, nvp->w1, 0);
+
+ xive2_router_write_nvp(xrtr, nvp_blk, nvp_idx, nvp, 1);
+
+ /* return restored CPPR to generate a CPU exception if needed */
+ return cppr;
+}
+
static void xive2_tctx_need_resend(Xive2Router *xrtr, XiveTCTX *tctx,
- uint8_t nvp_blk, uint32_t nvp_idx)
+ uint8_t nvp_blk, uint32_t nvp_idx,
+ bool do_restore)
{
Xive2Nvp nvp;
uint8_t ipb;
@@ -226,6 +334,12 @@ static void xive2_tctx_need_resend(Xive2Router *xrtr, XiveTCTX *tctx,
return;
}
+ /* Automatically restore thread context registers */
+ if (xive2_router_get_config(xrtr) & XIVE2_VP_SAVE_RESTORE &&
+ do_restore) {
+ cppr = xive2_tctx_restore_os_ctx(xrtr, tctx, nvp_blk, nvp_idx, &nvp);
+ }
+
ipb = xive_get_field32(NVP2_W2_IPB, nvp.w2);
if (ipb) {
nvp.w2 = xive_set_field32(NVP2_W2_IPB, nvp.w2, 0);
@@ -249,15 +363,17 @@ void xive2_tm_push_os_ctx(XivePresenter *xptr, XiveTCTX *tctx,
uint8_t nvp_blk;
uint32_t nvp_idx;
bool vo;
+ bool do_restore;
- xive2_os_cam_decode(cam, &nvp_blk, &nvp_idx, &vo);
+ xive2_os_cam_decode(cam, &nvp_blk, &nvp_idx, &vo, &do_restore);
/* First update the thead context */
memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &qw1w2, 4);
/* Check the interrupt pending bits */
if (vo) {
- xive2_tctx_need_resend(XIVE2_ROUTER(xptr), tctx, nvp_blk, nvp_idx);
+ xive2_tctx_need_resend(XIVE2_ROUTER(xptr), tctx, nvp_blk, nvp_idx,
+ do_restore);
}
}
--
2.34.1
^ permalink raw reply related [flat|nested] 89+ messages in thread* [PULL 73/87] pnv/xive2: Add support for 8bits thread id
2022-03-02 11:06 [PULL 00/87] ppc queue Cédric Le Goater
` (71 preceding siblings ...)
2022-03-02 11:07 ` [PULL 72/87] pnv/xive2: Add support for automatic save&restore Cédric Le Goater
@ 2022-03-02 11:07 ` Cédric Le Goater
2022-03-02 11:07 ` [PULL 74/87] hw/ppc/spapr.c: use g_autofree in spapr_dt_chosen() Cédric Le Goater
` (14 subsequent siblings)
87 siblings, 0 replies; 89+ messages in thread
From: Cédric Le Goater @ 2022-03-02 11:07 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Daniel Henrique Barboza, Cédric Le Goater
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
include/hw/ppc/xive2.h | 1 +
hw/intc/pnv_xive2.c | 5 +++++
hw/intc/xive2.c | 3 ++-
3 files changed, 8 insertions(+), 1 deletion(-)
diff --git a/include/hw/ppc/xive2.h b/include/hw/ppc/xive2.h
index 296a2d949498..e9e3ea135ea6 100644
--- a/include/hw/ppc/xive2.h
+++ b/include/hw/ppc/xive2.h
@@ -31,6 +31,7 @@ OBJECT_DECLARE_TYPE(Xive2Router, Xive2RouterClass, XIVE2_ROUTER);
#define XIVE2_GEN1_TIMA_OS 0x00000001
#define XIVE2_VP_SAVE_RESTORE 0x00000002
+#define XIVE2_THREADID_8BITS 0x00000004
typedef struct Xive2RouterClass {
SysBusDeviceClass parent;
diff --git a/hw/intc/pnv_xive2.c b/hw/intc/pnv_xive2.c
index b51571c6034f..87303b40641b 100644
--- a/hw/intc/pnv_xive2.c
+++ b/hw/intc/pnv_xive2.c
@@ -439,6 +439,11 @@ static uint32_t pnv_xive2_get_config(Xive2Router *xrtr)
cfg |= XIVE2_VP_SAVE_RESTORE;
}
+ if (GETFIELD(CQ_XIVE_CFG_HYP_HARD_RANGE,
+ xive->cq_regs[CQ_XIVE_CFG >> 3]) == CQ_XIVE_CFG_THREADID_8BITS) {
+ cfg |= XIVE2_THREADID_8BITS;
+ }
+
return cfg;
}
diff --git a/hw/intc/xive2.c b/hw/intc/xive2.c
index fd9cfebd782d..b6452f14784b 100644
--- a/hw/intc/xive2.c
+++ b/hw/intc/xive2.c
@@ -459,7 +459,8 @@ static uint32_t xive2_tctx_hw_cam_line(XivePresenter *xptr, XiveTCTX *tctx)
CPUPPCState *env = &POWERPC_CPU(tctx->cs)->env;
uint32_t pir = env->spr_cb[SPR_PIR].default_value;
uint8_t blk = xive2_router_get_block_id(xrtr);
- uint8_t tid_shift = 7;
+ uint8_t tid_shift =
+ xive2_router_get_config(xrtr) & XIVE2_THREADID_8BITS ? 8 : 7;
uint8_t tid_mask = (1 << tid_shift) - 1;
return xive2_nvp_cam_line(blk, 1 << tid_shift | (pir & tid_mask));
--
2.34.1
^ permalink raw reply related [flat|nested] 89+ messages in thread* [PULL 74/87] hw/ppc/spapr.c: use g_autofree in spapr_dt_chosen()
2022-03-02 11:06 [PULL 00/87] ppc queue Cédric Le Goater
` (72 preceding siblings ...)
2022-03-02 11:07 ` [PULL 73/87] pnv/xive2: Add support for 8bits thread id Cédric Le Goater
@ 2022-03-02 11:07 ` Cédric Le Goater
2022-03-02 11:07 ` [PULL 75/87] hw/ppc/spapr.c: fail early if no firmware found in machine_init() Cédric Le Goater
` (13 subsequent siblings)
87 siblings, 0 replies; 89+ messages in thread
From: Cédric Le Goater @ 2022-03-02 11:07 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Cédric Le Goater, Daniel Henrique Barboza,
Philippe Mathieu-Daudé, David Gibson
From: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20220228175004.8862-2-danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/ppc/spapr.c | 7 ++-----
1 file changed, 2 insertions(+), 5 deletions(-)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index f0b75b22bb61..c74543ace324 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -1018,9 +1018,9 @@ static void spapr_dt_chosen(SpaprMachineState *spapr, void *fdt, bool reset)
if (reset) {
const char *boot_device = spapr->boot_device;
- char *stdout_path = spapr_vio_stdout_path(spapr->vio_bus);
+ g_autofree char *stdout_path = spapr_vio_stdout_path(spapr->vio_bus);
size_t cb = 0;
- char *bootlist = get_boot_devices_list(&cb);
+ g_autofree char *bootlist = get_boot_devices_list(&cb);
if (machine->kernel_cmdline && machine->kernel_cmdline[0]) {
_FDT(fdt_setprop_string(fdt, chosen, "bootargs",
@@ -1087,9 +1087,6 @@ static void spapr_dt_chosen(SpaprMachineState *spapr, void *fdt, bool reset)
}
spapr_dt_ov5_platform_support(spapr, fdt, chosen);
-
- g_free(stdout_path);
- g_free(bootlist);
}
_FDT(spapr_dt_ovec(fdt, chosen, spapr->ov5_cas, "ibm,architecture-vec-5"));
--
2.34.1
^ permalink raw reply related [flat|nested] 89+ messages in thread* [PULL 75/87] hw/ppc/spapr.c: fail early if no firmware found in machine_init()
2022-03-02 11:06 [PULL 00/87] ppc queue Cédric Le Goater
` (73 preceding siblings ...)
2022-03-02 11:07 ` [PULL 74/87] hw/ppc/spapr.c: use g_autofree in spapr_dt_chosen() Cédric Le Goater
@ 2022-03-02 11:07 ` Cédric Le Goater
2022-03-02 11:07 ` [PULL 76/87] hw/ppc/spapr_caps.c: use g_autofree in spapr_cap_set_string() Cédric Le Goater
` (12 subsequent siblings)
87 siblings, 0 replies; 89+ messages in thread
From: Cédric Le Goater @ 2022-03-02 11:07 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Cédric Le Goater, Daniel Henrique Barboza,
Philippe Mathieu-Daudé, David Gibson
From: Daniel Henrique Barboza <danielhb413@gmail.com>
The firmware check consists on a file search (qemu_find_file) and load
it via load_imag_targphys(). This validation is not dependent on any
other machine state but it currently being done at the end of
spapr_machine_init(). This means that we can do a lot of stuff and end
up failing at the end for something that we can verify right out of the
gate.
Move this validation to the start of spapr_machine_init() to fail
earlier. While we're at it, use g_autofree in the 'filename' pointer.
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20220228175004.8862-3-danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/ppc/spapr.c | 24 +++++++++++-------------
1 file changed, 11 insertions(+), 13 deletions(-)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index c74543ace324..4cc204f90dfe 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -2707,15 +2707,25 @@ static void spapr_machine_init(MachineState *machine)
MachineClass *mc = MACHINE_GET_CLASS(machine);
const char *bios_default = spapr->vof ? FW_FILE_NAME_VOF : FW_FILE_NAME;
const char *bios_name = machine->firmware ?: bios_default;
+ g_autofree char *filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
const char *kernel_filename = machine->kernel_filename;
const char *initrd_filename = machine->initrd_filename;
PCIHostState *phb;
int i;
MemoryRegion *sysmem = get_system_memory();
long load_limit, fw_size;
- char *filename;
Error *resize_hpt_err = NULL;
+ if (!filename) {
+ error_report("Could not find LPAR firmware '%s'", bios_name);
+ exit(1);
+ }
+ fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE);
+ if (fw_size <= 0) {
+ error_report("Could not load LPAR firmware '%s'", filename);
+ exit(1);
+ }
+
/*
* if Secure VM (PEF) support is configured, then initialize it
*/
@@ -2996,18 +3006,6 @@ static void spapr_machine_init(MachineState *machine)
}
}
- filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
- if (!filename) {
- error_report("Could not find LPAR firmware '%s'", bios_name);
- exit(1);
- }
- fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE);
- if (fw_size <= 0) {
- error_report("Could not load LPAR firmware '%s'", filename);
- exit(1);
- }
- g_free(filename);
-
/* FIXME: Should register things through the MachineState's qdev
* interface, this is a legacy from the sPAPREnvironment structure
* which predated MachineState but had a similar function */
--
2.34.1
^ permalink raw reply related [flat|nested] 89+ messages in thread* [PULL 76/87] hw/ppc/spapr_caps.c: use g_autofree in spapr_cap_set_string()
2022-03-02 11:06 [PULL 00/87] ppc queue Cédric Le Goater
` (74 preceding siblings ...)
2022-03-02 11:07 ` [PULL 75/87] hw/ppc/spapr.c: fail early if no firmware found in machine_init() Cédric Le Goater
@ 2022-03-02 11:07 ` Cédric Le Goater
2022-03-02 11:07 ` [PULL 77/87] hw/ppc/spapr_caps.c: use g_autofree in spapr_cap_get_string() Cédric Le Goater
` (11 subsequent siblings)
87 siblings, 0 replies; 89+ messages in thread
From: Cédric Le Goater @ 2022-03-02 11:07 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Daniel Henrique Barboza,
Philippe Mathieu-Daudé, Cédric Le Goater
From: Daniel Henrique Barboza <danielhb413@gmail.com>
And get rid of the 'out' label since it's now unused.
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20220228175004.8862-4-danielhb413@gmail.com>
[ clg: Fixed typo in commit log ]
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/ppc/spapr_caps.c | 8 +++-----
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/hw/ppc/spapr_caps.c b/hw/ppc/spapr_caps.c
index 616743127164..aab313ffb13e 100644
--- a/hw/ppc/spapr_caps.c
+++ b/hw/ppc/spapr_caps.c
@@ -120,7 +120,7 @@ static void spapr_cap_set_string(Object *obj, Visitor *v, const char *name,
SpaprCapabilityInfo *cap = opaque;
SpaprMachineState *spapr = SPAPR_MACHINE(obj);
uint8_t i;
- char *val;
+ g_autofree char *val = NULL;
if (!visit_type_str(v, name, &val, errp)) {
return;
@@ -128,20 +128,18 @@ static void spapr_cap_set_string(Object *obj, Visitor *v, const char *name,
if (!strcmp(val, "?")) {
error_setg(errp, "%s", cap->possible->help);
- goto out;
+ return;
}
for (i = 0; i < cap->possible->num; i++) {
if (!strcasecmp(val, cap->possible->vals[i])) {
spapr->cmd_line_caps[cap->index] = true;
spapr->eff.caps[cap->index] = i;
- goto out;
+ return;
}
}
error_setg(errp, "Invalid capability mode \"%s\" for cap-%s", val,
cap->name);
-out:
- g_free(val);
}
static void spapr_cap_get_pagesize(Object *obj, Visitor *v, const char *name,
--
2.34.1
^ permalink raw reply related [flat|nested] 89+ messages in thread* [PULL 77/87] hw/ppc/spapr_caps.c: use g_autofree in spapr_cap_get_string()
2022-03-02 11:06 [PULL 00/87] ppc queue Cédric Le Goater
` (75 preceding siblings ...)
2022-03-02 11:07 ` [PULL 76/87] hw/ppc/spapr_caps.c: use g_autofree in spapr_cap_set_string() Cédric Le Goater
@ 2022-03-02 11:07 ` Cédric Le Goater
2022-03-02 11:07 ` [PULL 78/87] hw/ppc/spapr_caps.c: use g_autofree in spapr_caps_add_properties() Cédric Le Goater
` (10 subsequent siblings)
87 siblings, 0 replies; 89+ messages in thread
From: Cédric Le Goater @ 2022-03-02 11:07 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Cédric Le Goater, Daniel Henrique Barboza,
Philippe Mathieu-Daudé, David Gibson
From: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20220228175004.8862-5-danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/ppc/spapr_caps.c | 7 +++----
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/hw/ppc/spapr_caps.c b/hw/ppc/spapr_caps.c
index aab313ffb13e..2773f9db9e10 100644
--- a/hw/ppc/spapr_caps.c
+++ b/hw/ppc/spapr_caps.c
@@ -95,12 +95,12 @@ static void spapr_cap_set_bool(Object *obj, Visitor *v, const char *name,
}
-static void spapr_cap_get_string(Object *obj, Visitor *v, const char *name,
- void *opaque, Error **errp)
+static void spapr_cap_get_string(Object *obj, Visitor *v, const char *name,
+ void *opaque, Error **errp)
{
SpaprCapabilityInfo *cap = opaque;
SpaprMachineState *spapr = SPAPR_MACHINE(obj);
- char *val = NULL;
+ g_autofree char *val = NULL;
uint8_t value = spapr_get_cap(spapr, cap->index);
if (value >= cap->possible->num) {
@@ -111,7 +111,6 @@ static void spapr_cap_get_string(Object *obj, Visitor *v, const char *name,
val = g_strdup(cap->possible->vals[value]);
visit_type_str(v, name, &val, errp);
- g_free(val);
}
static void spapr_cap_set_string(Object *obj, Visitor *v, const char *name,
--
2.34.1
^ permalink raw reply related [flat|nested] 89+ messages in thread* [PULL 78/87] hw/ppc/spapr_caps.c: use g_autofree in spapr_caps_add_properties()
2022-03-02 11:06 [PULL 00/87] ppc queue Cédric Le Goater
` (76 preceding siblings ...)
2022-03-02 11:07 ` [PULL 77/87] hw/ppc/spapr_caps.c: use g_autofree in spapr_cap_get_string() Cédric Le Goater
@ 2022-03-02 11:07 ` Cédric Le Goater
2022-03-02 11:07 ` [PULL 79/87] hw/ppc/spapr_drc.c: use g_auto in spapr_dt_drc() Cédric Le Goater
` (9 subsequent siblings)
87 siblings, 0 replies; 89+ messages in thread
From: Cédric Le Goater @ 2022-03-02 11:07 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Cédric Le Goater, Daniel Henrique Barboza,
Philippe Mathieu-Daudé, David Gibson
From: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20220228175004.8862-6-danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/ppc/spapr_caps.c | 7 ++-----
1 file changed, 2 insertions(+), 5 deletions(-)
diff --git a/hw/ppc/spapr_caps.c b/hw/ppc/spapr_caps.c
index 2773f9db9e10..655ab856a01b 100644
--- a/hw/ppc/spapr_caps.c
+++ b/hw/ppc/spapr_caps.c
@@ -930,16 +930,13 @@ void spapr_caps_add_properties(SpaprMachineClass *smc)
for (i = 0; i < ARRAY_SIZE(capability_table); i++) {
SpaprCapabilityInfo *cap = &capability_table[i];
- char *name = g_strdup_printf("cap-%s", cap->name);
- char *desc;
+ g_autofree char *name = g_strdup_printf("cap-%s", cap->name);
+ g_autofree char *desc = g_strdup_printf("%s", cap->description);
object_class_property_add(klass, name, cap->type,
cap->get, cap->set,
NULL, cap);
- desc = g_strdup_printf("%s", cap->description);
object_class_property_set_description(klass, name, desc);
- g_free(name);
- g_free(desc);
}
}
--
2.34.1
^ permalink raw reply related [flat|nested] 89+ messages in thread* [PULL 79/87] hw/ppc/spapr_drc.c: use g_auto in spapr_dt_drc()
2022-03-02 11:06 [PULL 00/87] ppc queue Cédric Le Goater
` (77 preceding siblings ...)
2022-03-02 11:07 ` [PULL 78/87] hw/ppc/spapr_caps.c: use g_autofree in spapr_caps_add_properties() Cédric Le Goater
@ 2022-03-02 11:07 ` Cédric Le Goater
2022-03-02 11:07 ` [PULL 80/87] hw/ppc/spapr_drc.c: use g_autofree in drc_realize() Cédric Le Goater
` (8 subsequent siblings)
87 siblings, 0 replies; 89+ messages in thread
From: Cédric Le Goater @ 2022-03-02 11:07 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Daniel Henrique Barboza,
Philippe Mathieu-Daudé, Cédric Le Goater
From: Daniel Henrique Barboza <danielhb413@gmail.com>
Use g_autoptr() with GArray* and GString* pointers to avoid calling
g_free() and the need for the 'out' label.
'drc_name' can also be g_autofreed to avoid a g_free() call at the end
of the while() loop.
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20220228175004.8862-7-danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/ppc/spapr_drc.c | 30 ++++++++++++------------------
1 file changed, 12 insertions(+), 18 deletions(-)
diff --git a/hw/ppc/spapr_drc.c b/hw/ppc/spapr_drc.c
index f8ac0a10df18..0ba84063aa26 100644
--- a/hw/ppc/spapr_drc.c
+++ b/hw/ppc/spapr_drc.c
@@ -841,8 +841,14 @@ int spapr_dt_drc(void *fdt, int offset, Object *owner, uint32_t drc_type_mask)
ObjectProperty *prop;
ObjectPropertyIterator iter;
uint32_t drc_count = 0;
- GArray *drc_indexes, *drc_power_domains;
- GString *drc_names, *drc_types;
+ g_autoptr(GArray) drc_indexes = g_array_new(false, true,
+ sizeof(uint32_t));
+ g_autoptr(GArray) drc_power_domains = g_array_new(false, true,
+ sizeof(uint32_t));
+ g_autoptr(GString) drc_names = g_string_set_size(g_string_new(NULL),
+ sizeof(uint32_t));
+ g_autoptr(GString) drc_types = g_string_set_size(g_string_new(NULL),
+ sizeof(uint32_t));
int ret;
/*
@@ -857,12 +863,8 @@ int spapr_dt_drc(void *fdt, int offset, Object *owner, uint32_t drc_type_mask)
* reserve the space now and set the offsets accordingly so we
* can fill them in later.
*/
- drc_indexes = g_array_new(false, true, sizeof(uint32_t));
drc_indexes = g_array_set_size(drc_indexes, 1);
- drc_power_domains = g_array_new(false, true, sizeof(uint32_t));
drc_power_domains = g_array_set_size(drc_power_domains, 1);
- drc_names = g_string_set_size(g_string_new(NULL), sizeof(uint32_t));
- drc_types = g_string_set_size(g_string_new(NULL), sizeof(uint32_t));
/* aliases for all DRConnector objects will be rooted in QOM
* composition tree at DRC_CONTAINER_PATH
@@ -874,7 +876,7 @@ int spapr_dt_drc(void *fdt, int offset, Object *owner, uint32_t drc_type_mask)
Object *obj;
SpaprDrc *drc;
SpaprDrcClass *drck;
- char *drc_name = NULL;
+ g_autofree char *drc_name = NULL;
uint32_t drc_index, drc_power_domain;
if (!strstart(prop->type, "link<", NULL)) {
@@ -908,7 +910,6 @@ int spapr_dt_drc(void *fdt, int offset, Object *owner, uint32_t drc_type_mask)
drc_name = spapr_drc_name(drc);
drc_names = g_string_append(drc_names, drc_name);
drc_names = g_string_insert_len(drc_names, -1, "\0", 1);
- g_free(drc_name);
/* ibm,drc-types */
drc_types = g_string_append(drc_types, drck->typename);
@@ -928,7 +929,7 @@ int spapr_dt_drc(void *fdt, int offset, Object *owner, uint32_t drc_type_mask)
drc_indexes->len * sizeof(uint32_t));
if (ret) {
error_report("Couldn't create ibm,drc-indexes property");
- goto out;
+ return ret;
}
ret = fdt_setprop(fdt, offset, "ibm,drc-power-domains",
@@ -936,29 +937,22 @@ int spapr_dt_drc(void *fdt, int offset, Object *owner, uint32_t drc_type_mask)
drc_power_domains->len * sizeof(uint32_t));
if (ret) {
error_report("Couldn't finalize ibm,drc-power-domains property");
- goto out;
+ return ret;
}
ret = fdt_setprop(fdt, offset, "ibm,drc-names",
drc_names->str, drc_names->len);
if (ret) {
error_report("Couldn't finalize ibm,drc-names property");
- goto out;
+ return ret;
}
ret = fdt_setprop(fdt, offset, "ibm,drc-types",
drc_types->str, drc_types->len);
if (ret) {
error_report("Couldn't finalize ibm,drc-types property");
- goto out;
}
-out:
- g_array_free(drc_indexes, true);
- g_array_free(drc_power_domains, true);
- g_string_free(drc_names, true);
- g_string_free(drc_types, true);
-
return ret;
}
--
2.34.1
^ permalink raw reply related [flat|nested] 89+ messages in thread* [PULL 80/87] hw/ppc/spapr_drc.c: use g_autofree in drc_realize()
2022-03-02 11:06 [PULL 00/87] ppc queue Cédric Le Goater
` (78 preceding siblings ...)
2022-03-02 11:07 ` [PULL 79/87] hw/ppc/spapr_drc.c: use g_auto in spapr_dt_drc() Cédric Le Goater
@ 2022-03-02 11:07 ` Cédric Le Goater
2022-03-02 11:07 ` [PULL 81/87] hw/ppc/spapr_drc.c: use g_autofree in drc_unrealize() Cédric Le Goater
` (7 subsequent siblings)
87 siblings, 0 replies; 89+ messages in thread
From: Cédric Le Goater @ 2022-03-02 11:07 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Daniel Henrique Barboza,
Philippe Mathieu-Daudé, Cédric Le Goater
From: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20220228175004.8862-8-danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/ppc/spapr_drc.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/hw/ppc/spapr_drc.c b/hw/ppc/spapr_drc.c
index 0ba84063aa26..251201fab3d8 100644
--- a/hw/ppc/spapr_drc.c
+++ b/hw/ppc/spapr_drc.c
@@ -519,8 +519,8 @@ static const VMStateDescription vmstate_spapr_drc = {
static void drc_realize(DeviceState *d, Error **errp)
{
SpaprDrc *drc = SPAPR_DR_CONNECTOR(d);
+ g_autofree gchar *link_name = g_strdup_printf("%x", spapr_drc_index(drc));
Object *root_container;
- gchar *link_name;
const char *child_name;
trace_spapr_drc_realize(spapr_drc_index(drc));
@@ -532,12 +532,10 @@ static void drc_realize(DeviceState *d, Error **errp)
* existing in the composition tree
*/
root_container = container_get(object_get_root(), DRC_CONTAINER_PATH);
- link_name = g_strdup_printf("%x", spapr_drc_index(drc));
child_name = object_get_canonical_path_component(OBJECT(drc));
trace_spapr_drc_realize_child(spapr_drc_index(drc), child_name);
object_property_add_alias(root_container, link_name,
drc->owner, child_name);
- g_free(link_name);
vmstate_register(VMSTATE_IF(drc), spapr_drc_index(drc), &vmstate_spapr_drc,
drc);
trace_spapr_drc_realize_complete(spapr_drc_index(drc));
--
2.34.1
^ permalink raw reply related [flat|nested] 89+ messages in thread* [PULL 81/87] hw/ppc/spapr_drc.c: use g_autofree in drc_unrealize()
2022-03-02 11:06 [PULL 00/87] ppc queue Cédric Le Goater
` (79 preceding siblings ...)
2022-03-02 11:07 ` [PULL 80/87] hw/ppc/spapr_drc.c: use g_autofree in drc_realize() Cédric Le Goater
@ 2022-03-02 11:07 ` Cédric Le Goater
2022-03-02 11:07 ` [PULL 82/87] hw/ppc/spapr_drc.c: use g_autofree in spapr_dr_connector_new() Cédric Le Goater
` (6 subsequent siblings)
87 siblings, 0 replies; 89+ messages in thread
From: Cédric Le Goater @ 2022-03-02 11:07 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Daniel Henrique Barboza,
Philippe Mathieu-Daudé, Cédric Le Goater
From: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20220228175004.8862-9-danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/ppc/spapr_drc.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/hw/ppc/spapr_drc.c b/hw/ppc/spapr_drc.c
index 251201fab3d8..b2a365baf148 100644
--- a/hw/ppc/spapr_drc.c
+++ b/hw/ppc/spapr_drc.c
@@ -544,15 +544,13 @@ static void drc_realize(DeviceState *d, Error **errp)
static void drc_unrealize(DeviceState *d)
{
SpaprDrc *drc = SPAPR_DR_CONNECTOR(d);
+ g_autofree gchar *name = g_strdup_printf("%x", spapr_drc_index(drc));
Object *root_container;
- gchar *name;
trace_spapr_drc_unrealize(spapr_drc_index(drc));
vmstate_unregister(VMSTATE_IF(drc), &vmstate_spapr_drc, drc);
root_container = container_get(object_get_root(), DRC_CONTAINER_PATH);
- name = g_strdup_printf("%x", spapr_drc_index(drc));
object_property_del(root_container, name);
- g_free(name);
}
SpaprDrc *spapr_dr_connector_new(Object *owner, const char *type,
--
2.34.1
^ permalink raw reply related [flat|nested] 89+ messages in thread* [PULL 82/87] hw/ppc/spapr_drc.c: use g_autofree in spapr_dr_connector_new()
2022-03-02 11:06 [PULL 00/87] ppc queue Cédric Le Goater
` (80 preceding siblings ...)
2022-03-02 11:07 ` [PULL 81/87] hw/ppc/spapr_drc.c: use g_autofree in drc_unrealize() Cédric Le Goater
@ 2022-03-02 11:07 ` Cédric Le Goater
2022-03-02 11:07 ` [PULL 83/87] hw/ppc/spapr_drc.c: use g_autofree in spapr_drc_by_index() Cédric Le Goater
` (5 subsequent siblings)
87 siblings, 0 replies; 89+ messages in thread
From: Cédric Le Goater @ 2022-03-02 11:07 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Daniel Henrique Barboza,
Philippe Mathieu-Daudé, Cédric Le Goater
From: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20220228175004.8862-10-danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/ppc/spapr_drc.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/hw/ppc/spapr_drc.c b/hw/ppc/spapr_drc.c
index b2a365baf148..ac4067625ee9 100644
--- a/hw/ppc/spapr_drc.c
+++ b/hw/ppc/spapr_drc.c
@@ -557,7 +557,7 @@ SpaprDrc *spapr_dr_connector_new(Object *owner, const char *type,
uint32_t id)
{
SpaprDrc *drc = SPAPR_DR_CONNECTOR(object_new(type));
- char *prop_name;
+ g_autofree char *prop_name = NULL;
drc->id = id;
drc->owner = owner;
@@ -566,7 +566,6 @@ SpaprDrc *spapr_dr_connector_new(Object *owner, const char *type,
object_property_add_child(owner, prop_name, OBJECT(drc));
object_unref(OBJECT(drc));
qdev_realize(DEVICE(drc), NULL, NULL);
- g_free(prop_name);
return drc;
}
--
2.34.1
^ permalink raw reply related [flat|nested] 89+ messages in thread* [PULL 83/87] hw/ppc/spapr_drc.c: use g_autofree in spapr_drc_by_index()
2022-03-02 11:06 [PULL 00/87] ppc queue Cédric Le Goater
` (81 preceding siblings ...)
2022-03-02 11:07 ` [PULL 82/87] hw/ppc/spapr_drc.c: use g_autofree in spapr_dr_connector_new() Cédric Le Goater
@ 2022-03-02 11:07 ` Cédric Le Goater
2022-03-02 11:08 ` [PULL 84/87] hw/ppc/spapr_numa.c: simplify spapr_numa_write_assoc_lookup_arrays() Cédric Le Goater
` (4 subsequent siblings)
87 siblings, 0 replies; 89+ messages in thread
From: Cédric Le Goater @ 2022-03-02 11:07 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Daniel Henrique Barboza,
Philippe Mathieu-Daudé, Cédric Le Goater
From: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20220228175004.8862-11-danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/ppc/spapr_drc.c | 6 ++----
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/hw/ppc/spapr_drc.c b/hw/ppc/spapr_drc.c
index ac4067625ee9..76bc5d42a050 100644
--- a/hw/ppc/spapr_drc.c
+++ b/hw/ppc/spapr_drc.c
@@ -798,11 +798,9 @@ static const TypeInfo spapr_drc_pmem_info = {
SpaprDrc *spapr_drc_by_index(uint32_t index)
{
Object *obj;
- gchar *name;
-
- name = g_strdup_printf("%s/%x", DRC_CONTAINER_PATH, index);
+ g_autofree gchar *name = g_strdup_printf("%s/%x", DRC_CONTAINER_PATH,
+ index);
obj = object_resolve_path(name, NULL);
- g_free(name);
return !obj ? NULL : SPAPR_DR_CONNECTOR(obj);
}
--
2.34.1
^ permalink raw reply related [flat|nested] 89+ messages in thread* [PULL 84/87] hw/ppc/spapr_numa.c: simplify spapr_numa_write_assoc_lookup_arrays()
2022-03-02 11:06 [PULL 00/87] ppc queue Cédric Le Goater
` (82 preceding siblings ...)
2022-03-02 11:07 ` [PULL 83/87] hw/ppc/spapr_drc.c: use g_autofree in spapr_drc_by_index() Cédric Le Goater
@ 2022-03-02 11:08 ` Cédric Le Goater
2022-03-02 11:08 ` [PULL 85/87] spapr_pci_nvlink2.c: use g_autofree in spapr_phb_nvgpu_ram_populate_dt() Cédric Le Goater
` (3 subsequent siblings)
87 siblings, 0 replies; 89+ messages in thread
From: Cédric Le Goater @ 2022-03-02 11:08 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Daniel Henrique Barboza,
Philippe Mathieu-Daudé, Cédric Le Goater
From: Daniel Henrique Barboza <danielhb413@gmail.com>
We can get the job done in spapr_numa_write_assoc_lookup_arrays() a bit
cleaner:
- 'cur_index = int_buf = g_malloc0(..)' is doing a g_malloc0() in the
'int_buf' pointer and making 'cur_index' point to 'int_buf' all in a
single line. No problem with that, but splitting into 2 lines is clearer
to follow
- use g_autofree in 'int_buf' to avoid a g_free() call later on
- 'buf_len' is only being used to store the size of 'int_buf' malloc.
Remove the var and just use the value in g_malloc0() directly
- remove the 'ret' var and just return the result of fdt_setprop()
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20220228175004.8862-12-danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/ppc/spapr_numa.c | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/hw/ppc/spapr_numa.c b/hw/ppc/spapr_numa.c
index e9ef7e764696..4f93bdefec64 100644
--- a/hw/ppc/spapr_numa.c
+++ b/hw/ppc/spapr_numa.c
@@ -431,12 +431,14 @@ int spapr_numa_write_assoc_lookup_arrays(SpaprMachineState *spapr, void *fdt,
int max_distance_ref_points = get_max_dist_ref_points(spapr);
int nb_numa_nodes = machine->numa_state->num_nodes;
int nr_nodes = nb_numa_nodes ? nb_numa_nodes : 1;
- uint32_t *int_buf, *cur_index, buf_len;
- int ret, i;
+ g_autofree uint32_t *int_buf = NULL;
+ uint32_t *cur_index;
+ int i;
/* ibm,associativity-lookup-arrays */
- buf_len = (nr_nodes * max_distance_ref_points + 2) * sizeof(uint32_t);
- cur_index = int_buf = g_malloc0(buf_len);
+ int_buf = g_malloc0((nr_nodes * max_distance_ref_points + 2) *
+ sizeof(uint32_t));
+ cur_index = int_buf;
int_buf[0] = cpu_to_be32(nr_nodes);
/* Number of entries per associativity list */
int_buf[1] = cpu_to_be32(max_distance_ref_points);
@@ -451,11 +453,9 @@ int spapr_numa_write_assoc_lookup_arrays(SpaprMachineState *spapr, void *fdt,
sizeof(uint32_t) * max_distance_ref_points);
cur_index += max_distance_ref_points;
}
- ret = fdt_setprop(fdt, offset, "ibm,associativity-lookup-arrays", int_buf,
- (cur_index - int_buf) * sizeof(uint32_t));
- g_free(int_buf);
- return ret;
+ return fdt_setprop(fdt, offset, "ibm,associativity-lookup-arrays",
+ int_buf, (cur_index - int_buf) * sizeof(uint32_t));
}
static void spapr_numa_FORM1_write_rtas_dt(SpaprMachineState *spapr,
--
2.34.1
^ permalink raw reply related [flat|nested] 89+ messages in thread* [PULL 85/87] spapr_pci_nvlink2.c: use g_autofree in spapr_phb_nvgpu_ram_populate_dt()
2022-03-02 11:06 [PULL 00/87] ppc queue Cédric Le Goater
` (83 preceding siblings ...)
2022-03-02 11:08 ` [PULL 84/87] hw/ppc/spapr_numa.c: simplify spapr_numa_write_assoc_lookup_arrays() Cédric Le Goater
@ 2022-03-02 11:08 ` Cédric Le Goater
2022-03-02 11:08 ` [PULL 86/87] hw/ppc/spapr_rtas.c: use g_autofree in rtas_ibm_get_system_parameter() Cédric Le Goater
` (2 subsequent siblings)
87 siblings, 0 replies; 89+ messages in thread
From: Cédric Le Goater @ 2022-03-02 11:08 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Daniel Henrique Barboza,
Philippe Mathieu-Daudé, Cédric Le Goater
From: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20220228175004.8862-13-danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/ppc/spapr_pci_nvlink2.c | 10 ++++------
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/hw/ppc/spapr_pci_nvlink2.c b/hw/ppc/spapr_pci_nvlink2.c
index 7fb0cf4d0443..4678c79235f6 100644
--- a/hw/ppc/spapr_pci_nvlink2.c
+++ b/hw/ppc/spapr_pci_nvlink2.c
@@ -320,7 +320,7 @@ void spapr_phb_nvgpu_populate_dt(SpaprPhbState *sphb, void *fdt, int bus_off,
void spapr_phb_nvgpu_ram_populate_dt(SpaprPhbState *sphb, void *fdt)
{
int i, j, linkidx, npuoff;
- char *npuname;
+ g_autofree char *npuname = NULL;
if (!sphb->nvgpus) {
return;
@@ -333,11 +333,10 @@ void spapr_phb_nvgpu_ram_populate_dt(SpaprPhbState *sphb, void *fdt)
_FDT(fdt_setprop_cell(fdt, npuoff, "#size-cells", 0));
/* Advertise NPU as POWER9 so the guest can enable NPU2 contexts */
_FDT((fdt_setprop_string(fdt, npuoff, "compatible", "ibm,power9-npu")));
- g_free(npuname);
for (i = 0, linkidx = 0; i < sphb->nvgpus->num; ++i) {
for (j = 0; j < sphb->nvgpus->slots[i].linknum; ++j) {
- char *linkname = g_strdup_printf("link@%d", linkidx);
+ g_autofree char *linkname = g_strdup_printf("link@%d", linkidx);
int off = fdt_add_subnode(fdt, npuoff, linkname);
_FDT(off);
@@ -347,7 +346,6 @@ void spapr_phb_nvgpu_ram_populate_dt(SpaprPhbState *sphb, void *fdt)
_FDT((fdt_setprop_cell(fdt, off, "phandle",
PHANDLE_NVLINK(sphb, i, j))));
_FDT((fdt_setprop_cell(fdt, off, "ibm,npu-link-index", linkidx)));
- g_free(linkname);
++linkidx;
}
}
@@ -360,7 +358,8 @@ void spapr_phb_nvgpu_ram_populate_dt(SpaprPhbState *sphb, void *fdt)
&error_abort);
uint64_t size = object_property_get_uint(nv_mrobj, "size", NULL);
uint64_t mem_reg[2] = { cpu_to_be64(nvslot->gpa), cpu_to_be64(size) };
- char *mem_name = g_strdup_printf("memory@%"PRIx64, nvslot->gpa);
+ g_autofree char *mem_name = g_strdup_printf("memory@%"PRIx64,
+ nvslot->gpa);
int off = fdt_add_subnode(fdt, 0, mem_name);
_FDT(off);
@@ -378,7 +377,6 @@ void spapr_phb_nvgpu_ram_populate_dt(SpaprPhbState *sphb, void *fdt)
sizeof(mem_reg))));
_FDT((fdt_setprop_cell(fdt, off, "phandle",
PHANDLE_GPURAM(sphb, i))));
- g_free(mem_name);
}
}
--
2.34.1
^ permalink raw reply related [flat|nested] 89+ messages in thread* [PULL 86/87] hw/ppc/spapr_rtas.c: use g_autofree in rtas_ibm_get_system_parameter()
2022-03-02 11:06 [PULL 00/87] ppc queue Cédric Le Goater
` (84 preceding siblings ...)
2022-03-02 11:08 ` [PULL 85/87] spapr_pci_nvlink2.c: use g_autofree in spapr_phb_nvgpu_ram_populate_dt() Cédric Le Goater
@ 2022-03-02 11:08 ` Cédric Le Goater
2022-03-02 11:08 ` [PULL 87/87] hw/ppc/spapr_vio.c: use g_autofree in spapr_dt_vdevice() Cédric Le Goater
2022-03-02 16:58 ` [PULL 00/87] ppc queue Peter Maydell
87 siblings, 0 replies; 89+ messages in thread
From: Cédric Le Goater @ 2022-03-02 11:08 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Daniel Henrique Barboza,
Philippe Mathieu-Daudé, Cédric Le Goater
From: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20220228175004.8862-14-danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/ppc/spapr_rtas.c | 25 ++++++++++++-------------
1 file changed, 12 insertions(+), 13 deletions(-)
diff --git a/hw/ppc/spapr_rtas.c b/hw/ppc/spapr_rtas.c
index b476382ae6f5..d7c04237feb9 100644
--- a/hw/ppc/spapr_rtas.c
+++ b/hw/ppc/spapr_rtas.c
@@ -279,30 +279,29 @@ static void rtas_ibm_get_system_parameter(PowerPCCPU *cpu,
switch (parameter) {
case RTAS_SYSPARM_SPLPAR_CHARACTERISTICS: {
- char *param_val = g_strdup_printf("MaxEntCap=%d,"
- "DesMem=%" PRIu64 ","
- "DesProcs=%d,"
- "MaxPlatProcs=%d",
- ms->smp.max_cpus,
- ms->ram_size / MiB,
- ms->smp.cpus,
- ms->smp.max_cpus);
+ g_autofree char *param_val = g_strdup_printf("MaxEntCap=%d,"
+ "DesMem=%" PRIu64 ","
+ "DesProcs=%d,"
+ "MaxPlatProcs=%d",
+ ms->smp.max_cpus,
+ ms->ram_size / MiB,
+ ms->smp.cpus,
+ ms->smp.max_cpus);
if (pcc->n_host_threads > 0) {
- char *hostthr_val, *old = param_val;
-
/*
* Add HostThrs property. This property is not present in PAPR but
* is expected by some guests to communicate the number of physical
* host threads per core on the system so that they can scale
* information which varies based on the thread configuration.
*/
- hostthr_val = g_strdup_printf(",HostThrs=%d", pcc->n_host_threads);
+ g_autofree char *hostthr_val = g_strdup_printf(",HostThrs=%d",
+ pcc->n_host_threads);
+ char *old = param_val;
+
param_val = g_strconcat(param_val, hostthr_val, NULL);
- g_free(hostthr_val);
g_free(old);
}
ret = sysparm_st(buffer, length, param_val, strlen(param_val) + 1);
- g_free(param_val);
break;
}
case RTAS_SYSPARM_DIAGNOSTICS_RUN_MODE: {
--
2.34.1
^ permalink raw reply related [flat|nested] 89+ messages in thread* [PULL 87/87] hw/ppc/spapr_vio.c: use g_autofree in spapr_dt_vdevice()
2022-03-02 11:06 [PULL 00/87] ppc queue Cédric Le Goater
` (85 preceding siblings ...)
2022-03-02 11:08 ` [PULL 86/87] hw/ppc/spapr_rtas.c: use g_autofree in rtas_ibm_get_system_parameter() Cédric Le Goater
@ 2022-03-02 11:08 ` Cédric Le Goater
2022-03-02 16:58 ` [PULL 00/87] ppc queue Peter Maydell
87 siblings, 0 replies; 89+ messages in thread
From: Cédric Le Goater @ 2022-03-02 11:08 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Daniel Henrique Barboza,
Philippe Mathieu-Daudé, Cédric Le Goater
From: Daniel Henrique Barboza <danielhb413@gmail.com>
And return the result of g_strdup_printf() directly instead of using the
'path' var.
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20220228175004.8862-15-danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/ppc/spapr_vio.c | 6 ++----
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/hw/ppc/spapr_vio.c b/hw/ppc/spapr_vio.c
index b975ed29cadb..9d4fec2c04d8 100644
--- a/hw/ppc/spapr_vio.c
+++ b/hw/ppc/spapr_vio.c
@@ -726,7 +726,7 @@ void spapr_dt_vdevice(SpaprVioBus *bus, void *fdt)
gchar *spapr_vio_stdout_path(SpaprVioBus *bus)
{
SpaprVioDevice *dev;
- char *name, *path;
+ g_autofree char *name = NULL;
dev = spapr_vty_get_default(bus);
if (!dev) {
@@ -734,8 +734,6 @@ gchar *spapr_vio_stdout_path(SpaprVioBus *bus)
}
name = spapr_vio_get_dev_name(DEVICE(dev));
- path = g_strdup_printf("/vdevice/%s", name);
- g_free(name);
- return path;
+ return g_strdup_printf("/vdevice/%s", name);
}
--
2.34.1
^ permalink raw reply related [flat|nested] 89+ messages in thread* Re: [PULL 00/87] ppc queue
2022-03-02 11:06 [PULL 00/87] ppc queue Cédric Le Goater
` (86 preceding siblings ...)
2022-03-02 11:08 ` [PULL 87/87] hw/ppc/spapr_vio.c: use g_autofree in spapr_dt_vdevice() Cédric Le Goater
@ 2022-03-02 16:58 ` Peter Maydell
87 siblings, 0 replies; 89+ messages in thread
From: Peter Maydell @ 2022-03-02 16:58 UTC (permalink / raw)
To: Cédric Le Goater; +Cc: qemu-ppc, qemu-devel
On Wed, 2 Mar 2022 at 11:08, Cédric Le Goater <clg@kaod.org> wrote:
>
> The following changes since commit 09591fcf6eb3157ab9c50a9fbbef5f8a567fb49f:
>
> Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20220228' into staging (2022-03-01 15:55:31 +0000)
>
> are available in the Git repository at:
>
> https://github.com/legoater/qemu/ tags/pull-ppc-20220302
>
> for you to fetch changes up to 169518430562b454a1531610d2711c6b920929f6:
>
> hw/ppc/spapr_vio.c: use g_autofree in spapr_dt_vdevice() (2022-03-02 06:51:40 +0100)
>
> ----------------------------------------------------------------
> ppc-7.0 queue
>
> * ppc/pnv fixes
> * PMU EBB support
> * target/ppc: PowerISA Vector/VSX instruction batch
> * ppc/pnv: Extension of the powernv10 machine with XIVE2 ans PHB5 models
> * spapr allocation cleanups
>
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/7.0
for any user-visible changes.
-- PMM
^ permalink raw reply [flat|nested] 89+ messages in thread