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envelope-from=prvs=05403f1d5=alistair.francis@opensource.wdc.com; helo=esa6.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Alistair Francis The following changes since commit 64ada298b98a51eb2512607f6e6180cb330c47= b1: Merge remote-tracking branch 'remotes/legoater/tags/pull-ppc-20220302' = into staging (2022-03-02 12:38:46 +0000) are available in the Git repository at: git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20220303 for you to fetch changes up to 6b1accefd4876ea5475d55454c7d5b52c02cb73c: target/riscv: expose zfinx, zdinx, zhinx{min} properties (2022-03-03 13= :14:50 +1000) ---------------------------------------------------------------- Fifth RISC-V PR for QEMU 7.0 * Fixup checks for ext_zb[abcs] * Add AIA support for virt machine * Increase maximum number of CPUs in virt machine * Fixup OpenTitan SPI address * Add support for zfinx, zdinx and zhinx{min} extensions ---------------------------------------------------------------- Anup Patel (5): hw/riscv: virt: Add optional AIA APLIC support to virt machine hw/intc: Add RISC-V AIA IMSIC device emulation hw/riscv: virt: Add optional AIA IMSIC support to virt machine docs/system: riscv: Document AIA options for virt machine hw/riscv: virt: Increase maximum number of allowed CPUs Philipp Tomsich (1): target/riscv: fix inverted checks for ext_zb[abcs] Weiwei Li (6): target/riscv: add cfg properties for zfinx, zdinx and zhinx{min} target/riscv: hardwire mstatus.FS to zero when enable zfinx target/riscv: add support for zfinx target/riscv: add support for zdinx target/riscv: add support for zhinx/zhinxmin target/riscv: expose zfinx, zdinx, zhinx{min} properties Wilfred Mallawa (1): hw: riscv: opentitan: fixup SPI addresses docs/system/riscv/virt.rst | 16 + include/hw/intc/riscv_imsic.h | 68 +++ include/hw/riscv/opentitan.h | 4 +- include/hw/riscv/virt.h | 41 +- target/riscv/cpu.h | 4 + target/riscv/helper.h | 4 +- target/riscv/internals.h | 32 +- hw/intc/riscv_imsic.c | 448 +++++++++++++++++++ hw/riscv/opentitan.c | 12 +- hw/riscv/virt.c | 698 ++++++++++++++++++++++++= +----- target/riscv/cpu.c | 17 + target/riscv/cpu_helper.c | 6 +- target/riscv/csr.c | 25 +- target/riscv/fpu_helper.c | 178 ++++---- target/riscv/translate.c | 149 ++++++- target/riscv/insn_trans/trans_rvb.c.inc | 8 +- target/riscv/insn_trans/trans_rvd.c.inc | 285 ++++++++---- target/riscv/insn_trans/trans_rvf.c.inc | 314 ++++++++++---- target/riscv/insn_trans/trans_rvzfh.c.inc | 332 ++++++++++---- hw/intc/Kconfig | 3 + hw/intc/meson.build | 1 + hw/riscv/Kconfig | 2 + 22 files changed, 2146 insertions(+), 501 deletions(-) create mode 100644 include/hw/intc/riscv_imsic.h create mode 100644 hw/intc/riscv_imsic.c