From: Alistair Francis <alistair.francis@opensource.wdc.com>
To: qemu-devel@nongnu.org
Cc: alistair23@gmail.com, Weiwei Li <liweiwei@iscas.ac.cn>,
ardxwe <ardxwe@gmail.com>,
Junqiang Wang <wangjunqiang@iscas.ac.cn>,
Alistair Francis <alistair.francis@wdc.com>
Subject: [PULL 09/13] target/riscv: hardwire mstatus.FS to zero when enable zfinx
Date: Thu, 3 Mar 2022 15:28:00 +1000 [thread overview]
Message-ID: <20220303052804.529967-10-alistair.francis@opensource.wdc.com> (raw)
In-Reply-To: <20220303052804.529967-1-alistair.francis@opensource.wdc.com>
From: Weiwei Li <liweiwei@iscas.ac.cn>
Co-authored-by: ardxwe <ardxwe@gmail.com>
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220211043920.28981-3-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_helper.c | 6 +++++-
target/riscv/csr.c | 25 ++++++++++++++++++++-----
target/riscv/translate.c | 4 ++++
3 files changed, 29 insertions(+), 6 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 746335bfd6..1c60fb2e80 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -466,9 +466,13 @@ bool riscv_cpu_vector_enabled(CPURISCVState *env)
void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env)
{
- uint64_t mstatus_mask = MSTATUS_MXR | MSTATUS_SUM | MSTATUS_FS |
+ uint64_t mstatus_mask = MSTATUS_MXR | MSTATUS_SUM |
MSTATUS_SPP | MSTATUS_SPIE | MSTATUS_SIE |
MSTATUS64_UXL | MSTATUS_VS;
+
+ if (riscv_has_ext(env, RVF)) {
+ mstatus_mask |= MSTATUS_FS;
+ }
bool current_virt = riscv_cpu_virt_enabled(env);
g_assert(riscv_has_ext(env, RVH));
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index a938760a3f..aea82dff4a 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -39,7 +39,8 @@ void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops)
static RISCVException fs(CPURISCVState *env, int csrno)
{
#if !defined(CONFIG_USER_ONLY)
- if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
+ if (!env->debugger && !riscv_cpu_fp_enabled(env) &&
+ !RISCV_CPU(env_cpu(env))->cfg.ext_zfinx) {
return RISCV_EXCP_ILLEGAL_INST;
}
#endif
@@ -302,7 +303,9 @@ static RISCVException write_fflags(CPURISCVState *env, int csrno,
target_ulong val)
{
#if !defined(CONFIG_USER_ONLY)
- env->mstatus |= MSTATUS_FS;
+ if (riscv_has_ext(env, RVF)) {
+ env->mstatus |= MSTATUS_FS;
+ }
#endif
riscv_cpu_set_fflags(env, val & (FSR_AEXC >> FSR_AEXC_SHIFT));
return RISCV_EXCP_NONE;
@@ -319,7 +322,9 @@ static RISCVException write_frm(CPURISCVState *env, int csrno,
target_ulong val)
{
#if !defined(CONFIG_USER_ONLY)
- env->mstatus |= MSTATUS_FS;
+ if (riscv_has_ext(env, RVF)) {
+ env->mstatus |= MSTATUS_FS;
+ }
#endif
env->frm = val & (FSR_RD >> FSR_RD_SHIFT);
return RISCV_EXCP_NONE;
@@ -337,7 +342,9 @@ static RISCVException write_fcsr(CPURISCVState *env, int csrno,
target_ulong val)
{
#if !defined(CONFIG_USER_ONLY)
- env->mstatus |= MSTATUS_FS;
+ if (riscv_has_ext(env, RVF)) {
+ env->mstatus |= MSTATUS_FS;
+ }
#endif
env->frm = (val & FSR_RD) >> FSR_RD_SHIFT;
riscv_cpu_set_fflags(env, (val & FSR_AEXC) >> FSR_AEXC_SHIFT);
@@ -653,10 +660,14 @@ static RISCVException write_mstatus(CPURISCVState *env, int csrno,
tlb_flush(env_cpu(env));
}
mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE |
- MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM |
+ MSTATUS_SPP | MSTATUS_MPRV | MSTATUS_SUM |
MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR |
MSTATUS_TW | MSTATUS_VS;
+ if (riscv_has_ext(env, RVF)) {
+ mask |= MSTATUS_FS;
+ }
+
if (xl != MXL_RV32 || env->debugger) {
/*
* RV32: MPV and GVA are not in mstatus. The current plan is to
@@ -788,6 +799,10 @@ static RISCVException write_misa(CPURISCVState *env, int csrno,
return RISCV_EXCP_NONE;
}
+ if (!(val & RVF)) {
+ env->mstatus &= ~MSTATUS_FS;
+ }
+
/* flush translation cache */
tb_flush(env_cpu(env));
env->misa_ext = val;
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 84dbfa6340..c7232de326 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -426,6 +426,10 @@ static void mark_fs_dirty(DisasContext *ctx)
{
TCGv tmp;
+ if (!has_ext(ctx, RVF)) {
+ return;
+ }
+
if (ctx->mstatus_fs != MSTATUS_FS) {
/* Remember the state change for the rest of the TB. */
ctx->mstatus_fs = MSTATUS_FS;
--
2.35.1
next prev parent reply other threads:[~2022-03-03 5:37 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-03-03 5:27 [PULL 00/13] riscv-to-apply queue Alistair Francis
2022-03-03 5:27 ` [PULL 01/13] target/riscv: fix inverted checks for ext_zb[abcs] Alistair Francis
2022-03-03 5:27 ` [PULL 02/13] hw/riscv: virt: Add optional AIA APLIC support to virt machine Alistair Francis
2022-03-03 5:27 ` [PULL 03/13] hw/intc: Add RISC-V AIA IMSIC device emulation Alistair Francis
2022-03-03 5:27 ` [PULL 04/13] hw/riscv: virt: Add optional AIA IMSIC support to virt machine Alistair Francis
2022-03-03 5:27 ` [PULL 05/13] docs/system: riscv: Document AIA options for " Alistair Francis
2022-03-03 5:27 ` [PULL 06/13] hw/riscv: virt: Increase maximum number of allowed CPUs Alistair Francis
2022-03-03 5:27 ` [PULL 07/13] hw: riscv: opentitan: fixup SPI addresses Alistair Francis
2022-03-03 5:27 ` [PULL 08/13] target/riscv: add cfg properties for zfinx, zdinx and zhinx{min} Alistair Francis
2022-03-03 5:28 ` Alistair Francis [this message]
2022-03-03 5:28 ` [PULL 10/13] target/riscv: add support for zfinx Alistair Francis
2022-03-03 5:28 ` [PULL 11/13] target/riscv: add support for zdinx Alistair Francis
2022-03-03 5:28 ` [PULL 12/13] target/riscv: add support for zhinx/zhinxmin Alistair Francis
2022-03-03 5:28 ` [PULL 13/13] target/riscv: expose zfinx, zdinx, zhinx{min} properties Alistair Francis
2022-03-04 10:31 ` [PULL 00/13] riscv-to-apply queue Peter Maydell
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