From: Alistair Francis <alistair.francis@opensource.wdc.com>
To: qemu-devel@nongnu.org
Cc: alistair23@gmail.com, Philipp Tomsich <philipp.tomsich@vrull.eu>,
Alistair Francis <alistair.francis@wdc.com>
Subject: [PULL 01/13] target/riscv: fix inverted checks for ext_zb[abcs]
Date: Thu, 3 Mar 2022 15:27:52 +1000 [thread overview]
Message-ID: <20220303052804.529967-2-alistair.francis@opensource.wdc.com> (raw)
In-Reply-To: <20220303052804.529967-1-alistair.francis@opensource.wdc.com>
From: Philipp Tomsich <philipp.tomsich@vrull.eu>
While changing to the use of cfg_ptr, the conditions for REQUIRE_ZB[ABCS]
inadvertently became inverted and slipped through the initial testing (which
used RV64GC_XVentanaCondOps as a target).
This fixes the regression.
Tested against SPEC2017 w/ GCC 12 (prerelease) for RV64GC_zba_zbb_zbc_zbs.
Fixes: f2a32bec8f0da99 ("target/riscv: access cfg structure through DisasContext")
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220203153946.2676353-1-philipp.tomsich@vrull.eu>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/insn_trans/trans_rvb.c.inc | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc
index f9bd3b7ec4..e8519a6d69 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -19,25 +19,25 @@
*/
#define REQUIRE_ZBA(ctx) do { \
- if (ctx->cfg_ptr->ext_zba) { \
+ if (!ctx->cfg_ptr->ext_zba) { \
return false; \
} \
} while (0)
#define REQUIRE_ZBB(ctx) do { \
- if (ctx->cfg_ptr->ext_zbb) { \
+ if (!ctx->cfg_ptr->ext_zbb) { \
return false; \
} \
} while (0)
#define REQUIRE_ZBC(ctx) do { \
- if (ctx->cfg_ptr->ext_zbc) { \
+ if (!ctx->cfg_ptr->ext_zbc) { \
return false; \
} \
} while (0)
#define REQUIRE_ZBS(ctx) do { \
- if (ctx->cfg_ptr->ext_zbs) { \
+ if (!ctx->cfg_ptr->ext_zbs) { \
return false; \
} \
} while (0)
--
2.35.1
next prev parent reply other threads:[~2022-03-03 5:31 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-03-03 5:27 [PULL 00/13] riscv-to-apply queue Alistair Francis
2022-03-03 5:27 ` Alistair Francis [this message]
2022-03-03 5:27 ` [PULL 02/13] hw/riscv: virt: Add optional AIA APLIC support to virt machine Alistair Francis
2022-03-03 5:27 ` [PULL 03/13] hw/intc: Add RISC-V AIA IMSIC device emulation Alistair Francis
2022-03-03 5:27 ` [PULL 04/13] hw/riscv: virt: Add optional AIA IMSIC support to virt machine Alistair Francis
2022-03-03 5:27 ` [PULL 05/13] docs/system: riscv: Document AIA options for " Alistair Francis
2022-03-03 5:27 ` [PULL 06/13] hw/riscv: virt: Increase maximum number of allowed CPUs Alistair Francis
2022-03-03 5:27 ` [PULL 07/13] hw: riscv: opentitan: fixup SPI addresses Alistair Francis
2022-03-03 5:27 ` [PULL 08/13] target/riscv: add cfg properties for zfinx, zdinx and zhinx{min} Alistair Francis
2022-03-03 5:28 ` [PULL 09/13] target/riscv: hardwire mstatus.FS to zero when enable zfinx Alistair Francis
2022-03-03 5:28 ` [PULL 10/13] target/riscv: add support for zfinx Alistair Francis
2022-03-03 5:28 ` [PULL 11/13] target/riscv: add support for zdinx Alistair Francis
2022-03-03 5:28 ` [PULL 12/13] target/riscv: add support for zhinx/zhinxmin Alistair Francis
2022-03-03 5:28 ` [PULL 13/13] target/riscv: expose zfinx, zdinx, zhinx{min} properties Alistair Francis
2022-03-04 10:31 ` [PULL 00/13] riscv-to-apply queue Peter Maydell
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