From: Alistair Francis <alistair.francis@opensource.wdc.com>
To: qemu-devel@nongnu.org
Cc: alistair23@gmail.com, Anup Patel <anup.patel@wdc.com>,
Anup Patel <anup@brainfault.org>,
Alistair Francis <alistair.francis@wdc.com>,
Frank Chang <frank.chang@sifive.com>
Subject: [PULL 05/13] docs/system: riscv: Document AIA options for virt machine
Date: Thu, 3 Mar 2022 15:27:56 +1000 [thread overview]
Message-ID: <20220303052804.529967-6-alistair.francis@opensource.wdc.com> (raw)
In-Reply-To: <20220303052804.529967-1-alistair.francis@opensource.wdc.com>
From: Anup Patel <anup.patel@wdc.com>
We have two new machine options "aia" and "aia-guests" available
for the RISC-V virt machine so let's document these options.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-Id: <20220220085526.808674-5-anup@brainfault.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
docs/system/riscv/virt.rst | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/docs/system/riscv/virt.rst b/docs/system/riscv/virt.rst
index 08ce3c4177..1272b6659e 100644
--- a/docs/system/riscv/virt.rst
+++ b/docs/system/riscv/virt.rst
@@ -63,6 +63,22 @@ The following machine-specific options are supported:
When this option is "on", ACLINT devices will be emulated instead of
SiFive CLINT. When not specified, this option is assumed to be "off".
+- aia=[none|aplic|aplic-imsic]
+
+ This option allows selecting interrupt controller defined by the AIA
+ (advanced interrupt architecture) specification. The "aia=aplic" selects
+ APLIC (advanced platform level interrupt controller) to handle wired
+ interrupts whereas the "aia=aplic-imsic" selects APLIC and IMSIC (incoming
+ message signaled interrupt controller) to handle both wired interrupts and
+ MSIs. When not specified, this option is assumed to be "none" which selects
+ SiFive PLIC to handle wired interrupts.
+
+- aia-guests=nnn
+
+ The number of per-HART VS-level AIA IMSIC pages to be emulated for a guest
+ having AIA IMSIC (i.e. "aia=aplic-imsic" selected). When not specified,
+ the default number of per-HART VS-level AIA IMSIC pages is 0.
+
Running Linux kernel
--------------------
--
2.35.1
next prev parent reply other threads:[~2022-03-03 5:33 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-03-03 5:27 [PULL 00/13] riscv-to-apply queue Alistair Francis
2022-03-03 5:27 ` [PULL 01/13] target/riscv: fix inverted checks for ext_zb[abcs] Alistair Francis
2022-03-03 5:27 ` [PULL 02/13] hw/riscv: virt: Add optional AIA APLIC support to virt machine Alistair Francis
2022-03-03 5:27 ` [PULL 03/13] hw/intc: Add RISC-V AIA IMSIC device emulation Alistair Francis
2022-03-03 5:27 ` [PULL 04/13] hw/riscv: virt: Add optional AIA IMSIC support to virt machine Alistair Francis
2022-03-03 5:27 ` Alistair Francis [this message]
2022-03-03 5:27 ` [PULL 06/13] hw/riscv: virt: Increase maximum number of allowed CPUs Alistair Francis
2022-03-03 5:27 ` [PULL 07/13] hw: riscv: opentitan: fixup SPI addresses Alistair Francis
2022-03-03 5:27 ` [PULL 08/13] target/riscv: add cfg properties for zfinx, zdinx and zhinx{min} Alistair Francis
2022-03-03 5:28 ` [PULL 09/13] target/riscv: hardwire mstatus.FS to zero when enable zfinx Alistair Francis
2022-03-03 5:28 ` [PULL 10/13] target/riscv: add support for zfinx Alistair Francis
2022-03-03 5:28 ` [PULL 11/13] target/riscv: add support for zdinx Alistair Francis
2022-03-03 5:28 ` [PULL 12/13] target/riscv: add support for zhinx/zhinxmin Alistair Francis
2022-03-03 5:28 ` [PULL 13/13] target/riscv: expose zfinx, zdinx, zhinx{min} properties Alistair Francis
2022-03-04 10:31 ` [PULL 00/13] riscv-to-apply queue Peter Maydell
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