qemu-devel.nongnu.org archive mirror
 help / color / mirror / Atom feed
From: Alistair Francis <alistair.francis@opensource.wdc.com>
To: qemu-devel@nongnu.org
Cc: alistair23@gmail.com, Anup Patel <anup.patel@wdc.com>,
	Anup Patel <anup@brainfault.org>,
	Alistair Francis <alistair.francis@wdc.com>,
	Frank Chang <frank.chang@sifive.com>
Subject: [PULL 06/13] hw/riscv: virt: Increase maximum number of allowed CPUs
Date: Thu,  3 Mar 2022 15:27:57 +1000	[thread overview]
Message-ID: <20220303052804.529967-7-alistair.francis@opensource.wdc.com> (raw)
In-Reply-To: <20220303052804.529967-1-alistair.francis@opensource.wdc.com>

From: Anup Patel <anup.patel@wdc.com>

To facilitate software development of RISC-V systems with large number
of HARTs, we increase the maximum number of allowed CPUs to 512 (2^9).

We also add a detailed source level comments about limit defines which
impact the physical address space utilization.

Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Message-Id: <20220220085526.808674-6-anup@brainfault.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 include/hw/riscv/virt.h |  2 +-
 hw/riscv/virt.c         | 10 ++++++++++
 2 files changed, 11 insertions(+), 1 deletion(-)

diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
index d248d0dfa0..78b058ec86 100644
--- a/include/hw/riscv/virt.h
+++ b/include/hw/riscv/virt.h
@@ -24,7 +24,7 @@
 #include "hw/block/flash.h"
 #include "qom/object.h"
 
-#define VIRT_CPUS_MAX_BITS             3
+#define VIRT_CPUS_MAX_BITS             9
 #define VIRT_CPUS_MAX                  (1 << VIRT_CPUS_MAX_BITS)
 #define VIRT_SOCKETS_MAX_BITS          2
 #define VIRT_SOCKETS_MAX               (1 << VIRT_SOCKETS_MAX_BITS)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 94fbf63ec8..da50cbed43 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -45,6 +45,16 @@
 #include "hw/pci-host/gpex.h"
 #include "hw/display/ramfb.h"
 
+/*
+ * The virt machine physical address space used by some of the devices
+ * namely ACLINT, PLIC, APLIC, and IMSIC depend on number of Sockets,
+ * number of CPUs, and number of IMSIC guest files.
+ *
+ * Various limits defined by VIRT_SOCKETS_MAX_BITS, VIRT_CPUS_MAX_BITS,
+ * and VIRT_IRQCHIP_MAX_GUESTS_BITS are tuned for maximum utilization
+ * of virt machine physical address space.
+ */
+
 #define VIRT_IMSIC_GROUP_MAX_SIZE      (1U << IMSIC_MMIO_GROUP_MIN_SHIFT)
 #if VIRT_IMSIC_GROUP_MAX_SIZE < \
     IMSIC_GROUP_SIZE(VIRT_CPUS_MAX_BITS, VIRT_IRQCHIP_MAX_GUESTS_BITS)
-- 
2.35.1



  parent reply	other threads:[~2022-03-03  5:37 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-03-03  5:27 [PULL 00/13] riscv-to-apply queue Alistair Francis
2022-03-03  5:27 ` [PULL 01/13] target/riscv: fix inverted checks for ext_zb[abcs] Alistair Francis
2022-03-03  5:27 ` [PULL 02/13] hw/riscv: virt: Add optional AIA APLIC support to virt machine Alistair Francis
2022-03-03  5:27 ` [PULL 03/13] hw/intc: Add RISC-V AIA IMSIC device emulation Alistair Francis
2022-03-03  5:27 ` [PULL 04/13] hw/riscv: virt: Add optional AIA IMSIC support to virt machine Alistair Francis
2022-03-03  5:27 ` [PULL 05/13] docs/system: riscv: Document AIA options for " Alistair Francis
2022-03-03  5:27 ` Alistair Francis [this message]
2022-03-03  5:27 ` [PULL 07/13] hw: riscv: opentitan: fixup SPI addresses Alistair Francis
2022-03-03  5:27 ` [PULL 08/13] target/riscv: add cfg properties for zfinx, zdinx and zhinx{min} Alistair Francis
2022-03-03  5:28 ` [PULL 09/13] target/riscv: hardwire mstatus.FS to zero when enable zfinx Alistair Francis
2022-03-03  5:28 ` [PULL 10/13] target/riscv: add support for zfinx Alistair Francis
2022-03-03  5:28 ` [PULL 11/13] target/riscv: add support for zdinx Alistair Francis
2022-03-03  5:28 ` [PULL 12/13] target/riscv: add support for zhinx/zhinxmin Alistair Francis
2022-03-03  5:28 ` [PULL 13/13] target/riscv: expose zfinx, zdinx, zhinx{min} properties Alistair Francis
2022-03-04 10:31 ` [PULL 00/13] riscv-to-apply queue Peter Maydell

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20220303052804.529967-7-alistair.francis@opensource.wdc.com \
    --to=alistair.francis@opensource.wdc.com \
    --cc=alistair.francis@wdc.com \
    --cc=alistair23@gmail.com \
    --cc=anup.patel@wdc.com \
    --cc=anup@brainfault.org \
    --cc=frank.chang@sifive.com \
    --cc=qemu-devel@nongnu.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).