From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: "WANG Xuerui" <git@xen0n.name>,
peter.maydell@linaro.org,
"Alistair Francis" <alistair.francis@wdc.com>,
"Alex Bennée" <alex.bennee@linaro.org>,
"Philippe Mathieu-Daudé" <f4bug@amsat.org>
Subject: [PULL 22/30] tcg: Add TCG_TARGET_SIGNED_ADDR32
Date: Thu, 3 Mar 2022 10:59:36 -1000 [thread overview]
Message-ID: <20220303205944.469445-23-richard.henderson@linaro.org> (raw)
In-Reply-To: <20220303205944.469445-1-richard.henderson@linaro.org>
Define as 0 for all tcg hosts. Put this in a separate header,
because we'll want this in places that do not ordinarily have
access to all of tcg/tcg.h.
Reviewed-by: WANG Xuerui <git@xen0n.name>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/aarch64/tcg-target-sa32.h | 1 +
tcg/arm/tcg-target-sa32.h | 1 +
tcg/i386/tcg-target-sa32.h | 1 +
tcg/loongarch64/tcg-target-sa32.h | 1 +
tcg/mips/tcg-target-sa32.h | 1 +
tcg/ppc/tcg-target-sa32.h | 1 +
tcg/riscv/tcg-target-sa32.h | 1 +
tcg/s390x/tcg-target-sa32.h | 1 +
tcg/sparc/tcg-target-sa32.h | 1 +
tcg/tci/tcg-target-sa32.h | 1 +
tcg/tcg.c | 4 ++++
11 files changed, 14 insertions(+)
create mode 100644 tcg/aarch64/tcg-target-sa32.h
create mode 100644 tcg/arm/tcg-target-sa32.h
create mode 100644 tcg/i386/tcg-target-sa32.h
create mode 100644 tcg/loongarch64/tcg-target-sa32.h
create mode 100644 tcg/mips/tcg-target-sa32.h
create mode 100644 tcg/ppc/tcg-target-sa32.h
create mode 100644 tcg/riscv/tcg-target-sa32.h
create mode 100644 tcg/s390x/tcg-target-sa32.h
create mode 100644 tcg/sparc/tcg-target-sa32.h
create mode 100644 tcg/tci/tcg-target-sa32.h
diff --git a/tcg/aarch64/tcg-target-sa32.h b/tcg/aarch64/tcg-target-sa32.h
new file mode 100644
index 0000000000..cb185b1526
--- /dev/null
+++ b/tcg/aarch64/tcg-target-sa32.h
@@ -0,0 +1 @@
+#define TCG_TARGET_SIGNED_ADDR32 0
diff --git a/tcg/arm/tcg-target-sa32.h b/tcg/arm/tcg-target-sa32.h
new file mode 100644
index 0000000000..cb185b1526
--- /dev/null
+++ b/tcg/arm/tcg-target-sa32.h
@@ -0,0 +1 @@
+#define TCG_TARGET_SIGNED_ADDR32 0
diff --git a/tcg/i386/tcg-target-sa32.h b/tcg/i386/tcg-target-sa32.h
new file mode 100644
index 0000000000..cb185b1526
--- /dev/null
+++ b/tcg/i386/tcg-target-sa32.h
@@ -0,0 +1 @@
+#define TCG_TARGET_SIGNED_ADDR32 0
diff --git a/tcg/loongarch64/tcg-target-sa32.h b/tcg/loongarch64/tcg-target-sa32.h
new file mode 100644
index 0000000000..cb185b1526
--- /dev/null
+++ b/tcg/loongarch64/tcg-target-sa32.h
@@ -0,0 +1 @@
+#define TCG_TARGET_SIGNED_ADDR32 0
diff --git a/tcg/mips/tcg-target-sa32.h b/tcg/mips/tcg-target-sa32.h
new file mode 100644
index 0000000000..cb185b1526
--- /dev/null
+++ b/tcg/mips/tcg-target-sa32.h
@@ -0,0 +1 @@
+#define TCG_TARGET_SIGNED_ADDR32 0
diff --git a/tcg/ppc/tcg-target-sa32.h b/tcg/ppc/tcg-target-sa32.h
new file mode 100644
index 0000000000..cb185b1526
--- /dev/null
+++ b/tcg/ppc/tcg-target-sa32.h
@@ -0,0 +1 @@
+#define TCG_TARGET_SIGNED_ADDR32 0
diff --git a/tcg/riscv/tcg-target-sa32.h b/tcg/riscv/tcg-target-sa32.h
new file mode 100644
index 0000000000..cb185b1526
--- /dev/null
+++ b/tcg/riscv/tcg-target-sa32.h
@@ -0,0 +1 @@
+#define TCG_TARGET_SIGNED_ADDR32 0
diff --git a/tcg/s390x/tcg-target-sa32.h b/tcg/s390x/tcg-target-sa32.h
new file mode 100644
index 0000000000..cb185b1526
--- /dev/null
+++ b/tcg/s390x/tcg-target-sa32.h
@@ -0,0 +1 @@
+#define TCG_TARGET_SIGNED_ADDR32 0
diff --git a/tcg/sparc/tcg-target-sa32.h b/tcg/sparc/tcg-target-sa32.h
new file mode 100644
index 0000000000..cb185b1526
--- /dev/null
+++ b/tcg/sparc/tcg-target-sa32.h
@@ -0,0 +1 @@
+#define TCG_TARGET_SIGNED_ADDR32 0
diff --git a/tcg/tci/tcg-target-sa32.h b/tcg/tci/tcg-target-sa32.h
new file mode 100644
index 0000000000..cb185b1526
--- /dev/null
+++ b/tcg/tci/tcg-target-sa32.h
@@ -0,0 +1 @@
+#define TCG_TARGET_SIGNED_ADDR32 0
diff --git a/tcg/tcg.c b/tcg/tcg.c
index 33a97eabdb..8c131293fe 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -61,6 +61,10 @@
#include "exec/log.h"
#include "tcg/tcg-ldst.h"
#include "tcg-internal.h"
+#include "tcg-target-sa32.h"
+
+/* Sanity check for TCG_TARGET_SIGNED_ADDR32. */
+QEMU_BUILD_BUG_ON(TCG_TARGET_REG_BITS == 32 && TCG_TARGET_SIGNED_ADDR32);
#ifdef CONFIG_TCG_INTERPRETER
#include <ffi.h>
--
2.25.1
next prev parent reply other threads:[~2022-03-03 21:24 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-03-03 20:59 [PULL 00/30] tcg patch queue Richard Henderson
2022-03-03 20:59 ` [PULL 01/30] tcg/optimize: only read val after const check Richard Henderson
2022-03-03 20:59 ` [PULL 02/30] tcg: Set MAX_OPC_PARAM_IARGS to 7 Richard Henderson
2022-03-03 20:59 ` [PULL 03/30] tcg: Add opcodes for vector nand, nor, eqv Richard Henderson
2022-03-03 20:59 ` [PULL 04/30] tcg/ppc: Implement vector NAND, NOR, EQV Richard Henderson
2022-03-03 20:59 ` [PULL 05/30] tcg/s390x: " Richard Henderson
2022-03-03 20:59 ` [PULL 06/30] tcg/i386: Detect AVX512 Richard Henderson
2022-03-03 20:59 ` [PULL 07/30] tcg/i386: Add tcg_out_evex_opc Richard Henderson
2022-03-03 20:59 ` [PULL 08/30] tcg/i386: Use tcg_can_emit_vec_op in expand_vec_cmp_noinv Richard Henderson
2022-03-03 20:59 ` [PULL 09/30] tcg/i386: Implement avx512 variable shifts Richard Henderson
2022-03-03 20:59 ` [PULL 10/30] tcg/i386: Implement avx512 scalar shift Richard Henderson
2022-03-03 20:59 ` [PULL 11/30] tcg/i386: Implement avx512 immediate sari shift Richard Henderson
2022-03-03 20:59 ` [PULL 12/30] tcg/i386: Implement avx512 immediate rotate Richard Henderson
2022-03-03 20:59 ` [PULL 13/30] tcg/i386: Implement avx512 variable rotate Richard Henderson
2022-03-03 20:59 ` [PULL 14/30] tcg/i386: Support avx512vbmi2 vector shift-double instructions Richard Henderson
2022-03-03 20:59 ` [PULL 15/30] tcg/i386: Expand vector word rotate as avx512vbmi2 shift-double Richard Henderson
2022-03-03 20:59 ` [PULL 16/30] tcg/i386: Remove rotls_vec from tcg_target_op_def Richard Henderson
2022-03-03 20:59 ` [PULL 17/30] tcg/i386: Expand scalar rotate with avx512 insns Richard Henderson
2022-03-03 20:59 ` [PULL 18/30] tcg/i386: Implement avx512 min/max/abs Richard Henderson
2022-03-03 20:59 ` [PULL 19/30] tcg/i386: Implement avx512 multiply Richard Henderson
2022-03-03 20:59 ` [PULL 20/30] tcg/i386: Implement more logical operations for avx512 Richard Henderson
2022-03-03 20:59 ` [PULL 21/30] tcg/i386: Implement bitsel " Richard Henderson
2022-03-03 20:59 ` Richard Henderson [this message]
2022-03-03 20:59 ` [PULL 23/30] accel/tcg: Split out g2h_tlbe Richard Henderson
2022-03-03 20:59 ` [PULL 24/30] accel/tcg: Support TCG_TARGET_SIGNED_ADDR32 for softmmu Richard Henderson
2022-03-03 20:59 ` [PULL 25/30] accel/tcg: Add guest_base_signed_addr32 for user-only Richard Henderson
2022-03-03 20:59 ` [PULL 26/30] linux-user: Support TCG_TARGET_SIGNED_ADDR32 Richard Henderson
2022-03-03 20:59 ` [PULL 27/30] tcg/aarch64: " Richard Henderson
2022-03-03 20:59 ` [PULL 28/30] tcg/mips: " Richard Henderson
2022-03-03 20:59 ` [PULL 29/30] tcg/riscv: " Richard Henderson
2022-03-03 20:59 ` [PULL 30/30] tcg/loongarch64: " Richard Henderson
2022-03-04 15:22 ` [PULL 00/30] tcg patch queue Peter Maydell
2022-03-04 18:47 ` Richard Henderson
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