* [PULL 01/30] tcg/optimize: only read val after const check
2022-03-03 20:59 [PULL 00/30] tcg patch queue Richard Henderson
@ 2022-03-03 20:59 ` Richard Henderson
2022-03-03 20:59 ` [PULL 02/30] tcg: Set MAX_OPC_PARAM_IARGS to 7 Richard Henderson
` (29 subsequent siblings)
30 siblings, 0 replies; 33+ messages in thread
From: Richard Henderson @ 2022-03-03 20:59 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Alex Bennée, Philippe Mathieu-Daudé
From: Alex Bennée <alex.bennee@linaro.org>
valgrind pointed out that arg_info()->val can be undefined which will
be the case if the arguments are not constant. The ordering of the
checks will have ensured we never relied on an undefined value but for
the sake of completeness re-order the code to be clear.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20220209112142.3367525-1-alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/optimize.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/tcg/optimize.c b/tcg/optimize.c
index e573000951..06213fd434 100644
--- a/tcg/optimize.c
+++ b/tcg/optimize.c
@@ -552,10 +552,10 @@ static bool do_constant_folding_cond_eq(TCGCond c)
static int do_constant_folding_cond(TCGType type, TCGArg x,
TCGArg y, TCGCond c)
{
- uint64_t xv = arg_info(x)->val;
- uint64_t yv = arg_info(y)->val;
-
if (arg_is_const(x) && arg_is_const(y)) {
+ uint64_t xv = arg_info(x)->val;
+ uint64_t yv = arg_info(y)->val;
+
switch (type) {
case TCG_TYPE_I32:
return do_constant_folding_cond_32(xv, yv, c);
@@ -567,7 +567,7 @@ static int do_constant_folding_cond(TCGType type, TCGArg x,
}
} else if (args_are_copies(x, y)) {
return do_constant_folding_cond_eq(c);
- } else if (arg_is_const(y) && yv == 0) {
+ } else if (arg_is_const(y) && arg_info(y)->val == 0) {
switch (c) {
case TCG_COND_LTU:
return 0;
--
2.25.1
^ permalink raw reply related [flat|nested] 33+ messages in thread* [PULL 02/30] tcg: Set MAX_OPC_PARAM_IARGS to 7
2022-03-03 20:59 [PULL 00/30] tcg patch queue Richard Henderson
2022-03-03 20:59 ` [PULL 01/30] tcg/optimize: only read val after const check Richard Henderson
@ 2022-03-03 20:59 ` Richard Henderson
2022-03-03 20:59 ` [PULL 03/30] tcg: Add opcodes for vector nand, nor, eqv Richard Henderson
` (28 subsequent siblings)
30 siblings, 0 replies; 33+ messages in thread
From: Richard Henderson @ 2022-03-03 20:59 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Taylor Simpson, Ziqiao Kong
From: Ziqiao Kong <ziqiaokong@gmail.com>
The last entry of DEF_HELPERS_FLAGS_n is DEF_HELPER_FLAGS_7 and
thus the MAX_OPC_PARAM_IARGS should be 7.
Reviewed-by: Taylor Simpson <tsimpson@quicinc.com>
Signed-off-by: Ziqiao Kong <ziqiaokong@gmail.com>
Message-Id: <20220227113127.414533-2-ziqiaokong@gmail.com>
Fixes: e6cadf49c3d ("tcg: Add support for a helper with 7 arguments")
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/tcg/tcg.h | 2 +-
tcg/tci/tcg-target.c.inc | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h
index 42f5b500ed..939041103e 100644
--- a/include/tcg/tcg.h
+++ b/include/tcg/tcg.h
@@ -43,7 +43,7 @@
#else
#define MAX_OPC_PARAM_PER_ARG 1
#endif
-#define MAX_OPC_PARAM_IARGS 6
+#define MAX_OPC_PARAM_IARGS 7
#define MAX_OPC_PARAM_OARGS 1
#define MAX_OPC_PARAM_ARGS (MAX_OPC_PARAM_IARGS + MAX_OPC_PARAM_OARGS)
diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc
index 9ff1fa0832..98337c567a 100644
--- a/tcg/tci/tcg-target.c.inc
+++ b/tcg/tci/tcg-target.c.inc
@@ -197,7 +197,7 @@ static const int tcg_target_reg_alloc_order[] = {
TCG_REG_R0,
};
-#if MAX_OPC_PARAM_IARGS != 6
+#if MAX_OPC_PARAM_IARGS != 7
# error Fix needed, number of supported input arguments changed!
#endif
--
2.25.1
^ permalink raw reply related [flat|nested] 33+ messages in thread* [PULL 03/30] tcg: Add opcodes for vector nand, nor, eqv
2022-03-03 20:59 [PULL 00/30] tcg patch queue Richard Henderson
2022-03-03 20:59 ` [PULL 01/30] tcg/optimize: only read val after const check Richard Henderson
2022-03-03 20:59 ` [PULL 02/30] tcg: Set MAX_OPC_PARAM_IARGS to 7 Richard Henderson
@ 2022-03-03 20:59 ` Richard Henderson
2022-03-03 20:59 ` [PULL 04/30] tcg/ppc: Implement vector NAND, NOR, EQV Richard Henderson
` (27 subsequent siblings)
30 siblings, 0 replies; 33+ messages in thread
From: Richard Henderson @ 2022-03-03 20:59 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Alex Bennée, Philippe Mathieu-Daudé
We've had placeholders for these opcodes for a while,
and should have support on ppc, s390x and avx512 hosts.
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/tcg/tcg-opc.h | 3 +++
include/tcg/tcg.h | 3 +++
tcg/aarch64/tcg-target.h | 3 +++
tcg/arm/tcg-target.h | 3 +++
tcg/i386/tcg-target.h | 3 +++
tcg/ppc/tcg-target.h | 3 +++
tcg/s390x/tcg-target.h | 3 +++
tcg/optimize.c | 12 ++++++------
tcg/tcg-op-vec.c | 27 ++++++++++++++++++---------
tcg/tcg.c | 6 ++++++
10 files changed, 51 insertions(+), 15 deletions(-)
diff --git a/include/tcg/tcg-opc.h b/include/tcg/tcg-opc.h
index 675873e200..dd444734d9 100644
--- a/include/tcg/tcg-opc.h
+++ b/include/tcg/tcg-opc.h
@@ -245,6 +245,9 @@ DEF(or_vec, 1, 2, 0, IMPLVEC)
DEF(xor_vec, 1, 2, 0, IMPLVEC)
DEF(andc_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_andc_vec))
DEF(orc_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_orc_vec))
+DEF(nand_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_nand_vec))
+DEF(nor_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_nor_vec))
+DEF(eqv_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_eqv_vec))
DEF(not_vec, 1, 1, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_not_vec))
DEF(shli_vec, 1, 1, 1, IMPLVEC | IMPL(TCG_TARGET_HAS_shi_vec))
diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h
index 939041103e..73869fd9d0 100644
--- a/include/tcg/tcg.h
+++ b/include/tcg/tcg.h
@@ -183,6 +183,9 @@ typedef uint64_t TCGRegSet;
#define TCG_TARGET_HAS_not_vec 0
#define TCG_TARGET_HAS_andc_vec 0
#define TCG_TARGET_HAS_orc_vec 0
+#define TCG_TARGET_HAS_nand_vec 0
+#define TCG_TARGET_HAS_nor_vec 0
+#define TCG_TARGET_HAS_eqv_vec 0
#define TCG_TARGET_HAS_roti_vec 0
#define TCG_TARGET_HAS_rots_vec 0
#define TCG_TARGET_HAS_rotv_vec 0
diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h
index 876af589ce..485f685bd2 100644
--- a/tcg/aarch64/tcg-target.h
+++ b/tcg/aarch64/tcg-target.h
@@ -131,6 +131,9 @@ typedef enum {
#define TCG_TARGET_HAS_andc_vec 1
#define TCG_TARGET_HAS_orc_vec 1
+#define TCG_TARGET_HAS_nand_vec 0
+#define TCG_TARGET_HAS_nor_vec 0
+#define TCG_TARGET_HAS_eqv_vec 0
#define TCG_TARGET_HAS_not_vec 1
#define TCG_TARGET_HAS_neg_vec 1
#define TCG_TARGET_HAS_abs_vec 1
diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
index 27c27a1f14..7e96495392 100644
--- a/tcg/arm/tcg-target.h
+++ b/tcg/arm/tcg-target.h
@@ -130,6 +130,9 @@ extern bool use_neon_instructions;
#define TCG_TARGET_HAS_andc_vec 1
#define TCG_TARGET_HAS_orc_vec 1
+#define TCG_TARGET_HAS_nand_vec 0
+#define TCG_TARGET_HAS_nor_vec 0
+#define TCG_TARGET_HAS_eqv_vec 0
#define TCG_TARGET_HAS_not_vec 1
#define TCG_TARGET_HAS_neg_vec 1
#define TCG_TARGET_HAS_abs_vec 1
diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
index 3b2c9437a0..ecd0fa6e05 100644
--- a/tcg/i386/tcg-target.h
+++ b/tcg/i386/tcg-target.h
@@ -185,6 +185,9 @@ extern bool have_movbe;
#define TCG_TARGET_HAS_andc_vec 1
#define TCG_TARGET_HAS_orc_vec 0
+#define TCG_TARGET_HAS_nand_vec 0
+#define TCG_TARGET_HAS_nor_vec 0
+#define TCG_TARGET_HAS_eqv_vec 0
#define TCG_TARGET_HAS_not_vec 0
#define TCG_TARGET_HAS_neg_vec 0
#define TCG_TARGET_HAS_abs_vec 1
diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h
index c775c97b61..3e543161eb 100644
--- a/tcg/ppc/tcg-target.h
+++ b/tcg/ppc/tcg-target.h
@@ -162,6 +162,9 @@ extern bool have_vsx;
#define TCG_TARGET_HAS_andc_vec 1
#define TCG_TARGET_HAS_orc_vec have_isa_2_07
+#define TCG_TARGET_HAS_nand_vec 0
+#define TCG_TARGET_HAS_nor_vec 0
+#define TCG_TARGET_HAS_eqv_vec 0
#define TCG_TARGET_HAS_not_vec 1
#define TCG_TARGET_HAS_neg_vec have_isa_3_00
#define TCG_TARGET_HAS_abs_vec 0
diff --git a/tcg/s390x/tcg-target.h b/tcg/s390x/tcg-target.h
index 69217d995b..94ccb179b8 100644
--- a/tcg/s390x/tcg-target.h
+++ b/tcg/s390x/tcg-target.h
@@ -145,6 +145,9 @@ extern uint64_t s390_facilities[3];
#define TCG_TARGET_HAS_andc_vec 1
#define TCG_TARGET_HAS_orc_vec HAVE_FACILITY(VECTOR_ENH1)
+#define TCG_TARGET_HAS_nand_vec 0
+#define TCG_TARGET_HAS_nor_vec 0
+#define TCG_TARGET_HAS_eqv_vec 0
#define TCG_TARGET_HAS_not_vec 1
#define TCG_TARGET_HAS_neg_vec 1
#define TCG_TARGET_HAS_abs_vec 1
diff --git a/tcg/optimize.c b/tcg/optimize.c
index 06213fd434..ae081ab29c 100644
--- a/tcg/optimize.c
+++ b/tcg/optimize.c
@@ -359,13 +359,13 @@ static uint64_t do_constant_folding_2(TCGOpcode op, uint64_t x, uint64_t y)
CASE_OP_32_64_VEC(orc):
return x | ~y;
- CASE_OP_32_64(eqv):
+ CASE_OP_32_64_VEC(eqv):
return ~(x ^ y);
- CASE_OP_32_64(nand):
+ CASE_OP_32_64_VEC(nand):
return ~(x & y);
- CASE_OP_32_64(nor):
+ CASE_OP_32_64_VEC(nor):
return ~(x | y);
case INDEX_op_clz_i32:
@@ -2119,7 +2119,7 @@ void tcg_optimize(TCGContext *s)
case INDEX_op_dup2_vec:
done = fold_dup2(&ctx, op);
break;
- CASE_OP_32_64(eqv):
+ CASE_OP_32_64_VEC(eqv):
done = fold_eqv(&ctx, op);
break;
CASE_OP_32_64(extract):
@@ -2170,13 +2170,13 @@ void tcg_optimize(TCGContext *s)
CASE_OP_32_64(mulu2):
done = fold_multiply2(&ctx, op);
break;
- CASE_OP_32_64(nand):
+ CASE_OP_32_64_VEC(nand):
done = fold_nand(&ctx, op);
break;
CASE_OP_32_64(neg):
done = fold_neg(&ctx, op);
break;
- CASE_OP_32_64(nor):
+ CASE_OP_32_64_VEC(nor):
done = fold_nor(&ctx, op);
break;
CASE_OP_32_64_VEC(not):
diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c
index faf30f9cdd..463dabf515 100644
--- a/tcg/tcg-op-vec.c
+++ b/tcg/tcg-op-vec.c
@@ -371,23 +371,32 @@ void tcg_gen_orc_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
void tcg_gen_nand_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
{
- /* TODO: Add TCG_TARGET_HAS_nand_vec when adding a backend supports it. */
- tcg_gen_and_vec(0, r, a, b);
- tcg_gen_not_vec(0, r, r);
+ if (TCG_TARGET_HAS_nand_vec) {
+ vec_gen_op3(INDEX_op_nand_vec, 0, r, a, b);
+ } else {
+ tcg_gen_and_vec(0, r, a, b);
+ tcg_gen_not_vec(0, r, r);
+ }
}
void tcg_gen_nor_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
{
- /* TODO: Add TCG_TARGET_HAS_nor_vec when adding a backend supports it. */
- tcg_gen_or_vec(0, r, a, b);
- tcg_gen_not_vec(0, r, r);
+ if (TCG_TARGET_HAS_nor_vec) {
+ vec_gen_op3(INDEX_op_nor_vec, 0, r, a, b);
+ } else {
+ tcg_gen_or_vec(0, r, a, b);
+ tcg_gen_not_vec(0, r, r);
+ }
}
void tcg_gen_eqv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b)
{
- /* TODO: Add TCG_TARGET_HAS_eqv_vec when adding a backend supports it. */
- tcg_gen_xor_vec(0, r, a, b);
- tcg_gen_not_vec(0, r, r);
+ if (TCG_TARGET_HAS_eqv_vec) {
+ vec_gen_op3(INDEX_op_eqv_vec, 0, r, a, b);
+ } else {
+ tcg_gen_xor_vec(0, r, a, b);
+ tcg_gen_not_vec(0, r, r);
+ }
}
static bool do_op2(unsigned vece, TCGv_vec r, TCGv_vec a, TCGOpcode opc)
diff --git a/tcg/tcg.c b/tcg/tcg.c
index 528277d1d3..33a97eabdb 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -1407,6 +1407,12 @@ bool tcg_op_supported(TCGOpcode op)
return have_vec && TCG_TARGET_HAS_andc_vec;
case INDEX_op_orc_vec:
return have_vec && TCG_TARGET_HAS_orc_vec;
+ case INDEX_op_nand_vec:
+ return have_vec && TCG_TARGET_HAS_nand_vec;
+ case INDEX_op_nor_vec:
+ return have_vec && TCG_TARGET_HAS_nor_vec;
+ case INDEX_op_eqv_vec:
+ return have_vec && TCG_TARGET_HAS_eqv_vec;
case INDEX_op_mul_vec:
return have_vec && TCG_TARGET_HAS_mul_vec;
case INDEX_op_shli_vec:
--
2.25.1
^ permalink raw reply related [flat|nested] 33+ messages in thread* [PULL 04/30] tcg/ppc: Implement vector NAND, NOR, EQV
2022-03-03 20:59 [PULL 00/30] tcg patch queue Richard Henderson
` (2 preceding siblings ...)
2022-03-03 20:59 ` [PULL 03/30] tcg: Add opcodes for vector nand, nor, eqv Richard Henderson
@ 2022-03-03 20:59 ` Richard Henderson
2022-03-03 20:59 ` [PULL 05/30] tcg/s390x: " Richard Henderson
` (26 subsequent siblings)
30 siblings, 0 replies; 33+ messages in thread
From: Richard Henderson @ 2022-03-03 20:59 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Alex Bennée, Philippe Mathieu-Daudé
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/ppc/tcg-target.h | 6 +++---
tcg/ppc/tcg-target.c.inc | 15 +++++++++++++++
2 files changed, 18 insertions(+), 3 deletions(-)
diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h
index 3e543161eb..e6cf72503f 100644
--- a/tcg/ppc/tcg-target.h
+++ b/tcg/ppc/tcg-target.h
@@ -162,9 +162,9 @@ extern bool have_vsx;
#define TCG_TARGET_HAS_andc_vec 1
#define TCG_TARGET_HAS_orc_vec have_isa_2_07
-#define TCG_TARGET_HAS_nand_vec 0
-#define TCG_TARGET_HAS_nor_vec 0
-#define TCG_TARGET_HAS_eqv_vec 0
+#define TCG_TARGET_HAS_nand_vec have_isa_2_07
+#define TCG_TARGET_HAS_nor_vec 1
+#define TCG_TARGET_HAS_eqv_vec have_isa_2_07
#define TCG_TARGET_HAS_not_vec 1
#define TCG_TARGET_HAS_neg_vec have_isa_3_00
#define TCG_TARGET_HAS_abs_vec 0
diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
index 69d22e08cb..1f3c5c171c 100644
--- a/tcg/ppc/tcg-target.c.inc
+++ b/tcg/ppc/tcg-target.c.inc
@@ -3122,6 +3122,9 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
case INDEX_op_xor_vec:
case INDEX_op_andc_vec:
case INDEX_op_not_vec:
+ case INDEX_op_nor_vec:
+ case INDEX_op_eqv_vec:
+ case INDEX_op_nand_vec:
return 1;
case INDEX_op_orc_vec:
return have_isa_2_07;
@@ -3400,6 +3403,15 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
case INDEX_op_orc_vec:
insn = VORC;
break;
+ case INDEX_op_nand_vec:
+ insn = VNAND;
+ break;
+ case INDEX_op_nor_vec:
+ insn = VNOR;
+ break;
+ case INDEX_op_eqv_vec:
+ insn = VEQV;
+ break;
case INDEX_op_cmp_vec:
switch (args[3]) {
@@ -3787,6 +3799,9 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
case INDEX_op_xor_vec:
case INDEX_op_andc_vec:
case INDEX_op_orc_vec:
+ case INDEX_op_nor_vec:
+ case INDEX_op_eqv_vec:
+ case INDEX_op_nand_vec:
case INDEX_op_cmp_vec:
case INDEX_op_ssadd_vec:
case INDEX_op_sssub_vec:
--
2.25.1
^ permalink raw reply related [flat|nested] 33+ messages in thread* [PULL 05/30] tcg/s390x: Implement vector NAND, NOR, EQV
2022-03-03 20:59 [PULL 00/30] tcg patch queue Richard Henderson
` (3 preceding siblings ...)
2022-03-03 20:59 ` [PULL 04/30] tcg/ppc: Implement vector NAND, NOR, EQV Richard Henderson
@ 2022-03-03 20:59 ` Richard Henderson
2022-03-03 20:59 ` [PULL 06/30] tcg/i386: Detect AVX512 Richard Henderson
` (25 subsequent siblings)
30 siblings, 0 replies; 33+ messages in thread
From: Richard Henderson @ 2022-03-03 20:59 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Alex Bennée, Philippe Mathieu-Daudé
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/s390x/tcg-target.h | 6 +++---
tcg/s390x/tcg-target.c.inc | 17 +++++++++++++++++
2 files changed, 20 insertions(+), 3 deletions(-)
diff --git a/tcg/s390x/tcg-target.h b/tcg/s390x/tcg-target.h
index 94ccb179b8..23e2063667 100644
--- a/tcg/s390x/tcg-target.h
+++ b/tcg/s390x/tcg-target.h
@@ -145,9 +145,9 @@ extern uint64_t s390_facilities[3];
#define TCG_TARGET_HAS_andc_vec 1
#define TCG_TARGET_HAS_orc_vec HAVE_FACILITY(VECTOR_ENH1)
-#define TCG_TARGET_HAS_nand_vec 0
-#define TCG_TARGET_HAS_nor_vec 0
-#define TCG_TARGET_HAS_eqv_vec 0
+#define TCG_TARGET_HAS_nand_vec HAVE_FACILITY(VECTOR_ENH1)
+#define TCG_TARGET_HAS_nor_vec 1
+#define TCG_TARGET_HAS_eqv_vec HAVE_FACILITY(VECTOR_ENH1)
#define TCG_TARGET_HAS_not_vec 1
#define TCG_TARGET_HAS_neg_vec 1
#define TCG_TARGET_HAS_abs_vec 1
diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc
index d56c1e51e4..6e65828c09 100644
--- a/tcg/s390x/tcg-target.c.inc
+++ b/tcg/s390x/tcg-target.c.inc
@@ -290,7 +290,9 @@ typedef enum S390Opcode {
VRRc_VMXL = 0xe7fd,
VRRc_VN = 0xe768,
VRRc_VNC = 0xe769,
+ VRRc_VNN = 0xe76e,
VRRc_VNO = 0xe76b,
+ VRRc_VNX = 0xe76c,
VRRc_VO = 0xe76a,
VRRc_VOC = 0xe76f,
VRRc_VPKS = 0xe797, /* we leave the m5 cs field 0 */
@@ -2805,6 +2807,15 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
case INDEX_op_xor_vec:
tcg_out_insn(s, VRRc, VX, a0, a1, a2, 0);
break;
+ case INDEX_op_nand_vec:
+ tcg_out_insn(s, VRRc, VNN, a0, a1, a2, 0);
+ break;
+ case INDEX_op_nor_vec:
+ tcg_out_insn(s, VRRc, VNO, a0, a1, a2, 0);
+ break;
+ case INDEX_op_eqv_vec:
+ tcg_out_insn(s, VRRc, VNX, a0, a1, a2, 0);
+ break;
case INDEX_op_shli_vec:
tcg_out_insn(s, VRSa, VESL, a0, a2, TCG_REG_NONE, a1, vece);
@@ -2901,7 +2912,10 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
case INDEX_op_and_vec:
case INDEX_op_andc_vec:
case INDEX_op_bitsel_vec:
+ case INDEX_op_eqv_vec:
+ case INDEX_op_nand_vec:
case INDEX_op_neg_vec:
+ case INDEX_op_nor_vec:
case INDEX_op_not_vec:
case INDEX_op_or_vec:
case INDEX_op_orc_vec:
@@ -3246,6 +3260,9 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
case INDEX_op_or_vec:
case INDEX_op_orc_vec:
case INDEX_op_xor_vec:
+ case INDEX_op_nand_vec:
+ case INDEX_op_nor_vec:
+ case INDEX_op_eqv_vec:
case INDEX_op_cmp_vec:
case INDEX_op_mul_vec:
case INDEX_op_rotlv_vec:
--
2.25.1
^ permalink raw reply related [flat|nested] 33+ messages in thread* [PULL 06/30] tcg/i386: Detect AVX512
2022-03-03 20:59 [PULL 00/30] tcg patch queue Richard Henderson
` (4 preceding siblings ...)
2022-03-03 20:59 ` [PULL 05/30] tcg/s390x: " Richard Henderson
@ 2022-03-03 20:59 ` Richard Henderson
2022-03-03 20:59 ` [PULL 07/30] tcg/i386: Add tcg_out_evex_opc Richard Henderson
` (24 subsequent siblings)
30 siblings, 0 replies; 33+ messages in thread
From: Richard Henderson @ 2022-03-03 20:59 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Alex Bennée
There are some operation sizes in some subsets of AVX512 that
are missing from previous iterations of AVX. Detect them.
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/qemu/cpuid.h | 20 +++++++++++++++++---
tcg/i386/tcg-target.h | 4 ++++
tcg/i386/tcg-target.c.inc | 24 ++++++++++++++++++++++--
3 files changed, 43 insertions(+), 5 deletions(-)
diff --git a/include/qemu/cpuid.h b/include/qemu/cpuid.h
index 09fc245b91..7adb12d320 100644
--- a/include/qemu/cpuid.h
+++ b/include/qemu/cpuid.h
@@ -45,12 +45,26 @@
#ifndef bit_AVX2
#define bit_AVX2 (1 << 5)
#endif
-#ifndef bit_AVX512F
-#define bit_AVX512F (1 << 16)
-#endif
#ifndef bit_BMI2
#define bit_BMI2 (1 << 8)
#endif
+#ifndef bit_AVX512F
+#define bit_AVX512F (1 << 16)
+#endif
+#ifndef bit_AVX512DQ
+#define bit_AVX512DQ (1 << 17)
+#endif
+#ifndef bit_AVX512BW
+#define bit_AVX512BW (1 << 30)
+#endif
+#ifndef bit_AVX512VL
+#define bit_AVX512VL (1u << 31)
+#endif
+
+/* Leaf 7, %ecx */
+#ifndef bit_AVX512VBMI2
+#define bit_AVX512VBMI2 (1 << 6)
+#endif
/* Leaf 0x80000001, %ecx */
#ifndef bit_LZCNT
diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
index ecd0fa6e05..79af353860 100644
--- a/tcg/i386/tcg-target.h
+++ b/tcg/i386/tcg-target.h
@@ -103,6 +103,10 @@ extern bool have_bmi1;
extern bool have_popcnt;
extern bool have_avx1;
extern bool have_avx2;
+extern bool have_avx512bw;
+extern bool have_avx512dq;
+extern bool have_avx512vbmi2;
+extern bool have_avx512vl;
extern bool have_movbe;
/* optional instructions */
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
index faa15eecab..7516be5d5f 100644
--- a/tcg/i386/tcg-target.c.inc
+++ b/tcg/i386/tcg-target.c.inc
@@ -171,6 +171,10 @@ bool have_bmi1;
bool have_popcnt;
bool have_avx1;
bool have_avx2;
+bool have_avx512bw;
+bool have_avx512dq;
+bool have_avx512vbmi2;
+bool have_avx512vl;
bool have_movbe;
#ifdef CONFIG_CPUID_H
@@ -3839,12 +3843,12 @@ static void tcg_out_nop_fill(tcg_insn_unit *p, int count)
static void tcg_target_init(TCGContext *s)
{
#ifdef CONFIG_CPUID_H
- unsigned a, b, c, d, b7 = 0;
+ unsigned a, b, c, d, b7 = 0, c7 = 0;
unsigned max = __get_cpuid_max(0, 0);
if (max >= 7) {
/* BMI1 is available on AMD Piledriver and Intel Haswell CPUs. */
- __cpuid_count(7, 0, a, b7, c, d);
+ __cpuid_count(7, 0, a, b7, c7, d);
have_bmi1 = (b7 & bit_BMI) != 0;
have_bmi2 = (b7 & bit_BMI2) != 0;
}
@@ -3874,6 +3878,22 @@ static void tcg_target_init(TCGContext *s)
if ((xcrl & 6) == 6) {
have_avx1 = (c & bit_AVX) != 0;
have_avx2 = (b7 & bit_AVX2) != 0;
+
+ /*
+ * There are interesting instructions in AVX512, so long
+ * as we have AVX512VL, which indicates support for EVEX
+ * on sizes smaller than 512 bits. We are required to
+ * check that OPMASK and all extended ZMM state are enabled
+ * even if we're not using them -- the insns will fault.
+ */
+ if ((xcrl & 0xe0) == 0xe0
+ && (b7 & bit_AVX512F)
+ && (b7 & bit_AVX512VL)) {
+ have_avx512vl = true;
+ have_avx512bw = (b7 & bit_AVX512BW) != 0;
+ have_avx512dq = (b7 & bit_AVX512DQ) != 0;
+ have_avx512vbmi2 = (c7 & bit_AVX512VBMI2) != 0;
+ }
}
}
}
--
2.25.1
^ permalink raw reply related [flat|nested] 33+ messages in thread* [PULL 07/30] tcg/i386: Add tcg_out_evex_opc
2022-03-03 20:59 [PULL 00/30] tcg patch queue Richard Henderson
` (5 preceding siblings ...)
2022-03-03 20:59 ` [PULL 06/30] tcg/i386: Detect AVX512 Richard Henderson
@ 2022-03-03 20:59 ` Richard Henderson
2022-03-03 20:59 ` [PULL 08/30] tcg/i386: Use tcg_can_emit_vec_op in expand_vec_cmp_noinv Richard Henderson
` (23 subsequent siblings)
30 siblings, 0 replies; 33+ messages in thread
From: Richard Henderson @ 2022-03-03 20:59 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Alex Bennée
The evex encoding is added here, for use in a subsequent patch.
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/i386/tcg-target.c.inc | 51 ++++++++++++++++++++++++++++++++++++++-
1 file changed, 50 insertions(+), 1 deletion(-)
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
index 7516be5d5f..89497b2b45 100644
--- a/tcg/i386/tcg-target.c.inc
+++ b/tcg/i386/tcg-target.c.inc
@@ -262,6 +262,7 @@ static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
#define P_SIMDF3 0x20000 /* 0xf3 opcode prefix */
#define P_SIMDF2 0x40000 /* 0xf2 opcode prefix */
#define P_VEXL 0x80000 /* Set VEX.L = 1 */
+#define P_EVEX 0x100000 /* Requires EVEX encoding */
#define OPC_ARITH_EvIz (0x81)
#define OPC_ARITH_EvIb (0x83)
@@ -626,9 +627,57 @@ static void tcg_out_vex_opc(TCGContext *s, int opc, int r, int v,
tcg_out8(s, opc);
}
+static void tcg_out_evex_opc(TCGContext *s, int opc, int r, int v,
+ int rm, int index)
+{
+ /* The entire 4-byte evex prefix; with R' and V' set. */
+ uint32_t p = 0x08041062;
+ int mm, pp;
+
+ tcg_debug_assert(have_avx512vl);
+
+ /* EVEX.mm */
+ if (opc & P_EXT3A) {
+ mm = 3;
+ } else if (opc & P_EXT38) {
+ mm = 2;
+ } else if (opc & P_EXT) {
+ mm = 1;
+ } else {
+ g_assert_not_reached();
+ }
+
+ /* EVEX.pp */
+ if (opc & P_DATA16) {
+ pp = 1; /* 0x66 */
+ } else if (opc & P_SIMDF3) {
+ pp = 2; /* 0xf3 */
+ } else if (opc & P_SIMDF2) {
+ pp = 3; /* 0xf2 */
+ } else {
+ pp = 0;
+ }
+
+ p = deposit32(p, 8, 2, mm);
+ p = deposit32(p, 13, 1, (rm & 8) == 0); /* EVEX.RXB.B */
+ p = deposit32(p, 14, 1, (index & 8) == 0); /* EVEX.RXB.X */
+ p = deposit32(p, 15, 1, (r & 8) == 0); /* EVEX.RXB.R */
+ p = deposit32(p, 16, 2, pp);
+ p = deposit32(p, 19, 4, ~v);
+ p = deposit32(p, 23, 1, (opc & P_VEXW) != 0);
+ p = deposit32(p, 29, 2, (opc & P_VEXL) != 0);
+
+ tcg_out32(s, p);
+ tcg_out8(s, opc);
+}
+
static void tcg_out_vex_modrm(TCGContext *s, int opc, int r, int v, int rm)
{
- tcg_out_vex_opc(s, opc, r, v, rm, 0);
+ if (opc & P_EVEX) {
+ tcg_out_evex_opc(s, opc, r, v, rm, 0);
+ } else {
+ tcg_out_vex_opc(s, opc, r, v, rm, 0);
+ }
tcg_out8(s, 0xc0 | (LOWREGMASK(r) << 3) | LOWREGMASK(rm));
}
--
2.25.1
^ permalink raw reply related [flat|nested] 33+ messages in thread* [PULL 08/30] tcg/i386: Use tcg_can_emit_vec_op in expand_vec_cmp_noinv
2022-03-03 20:59 [PULL 00/30] tcg patch queue Richard Henderson
` (6 preceding siblings ...)
2022-03-03 20:59 ` [PULL 07/30] tcg/i386: Add tcg_out_evex_opc Richard Henderson
@ 2022-03-03 20:59 ` Richard Henderson
2022-03-03 20:59 ` [PULL 09/30] tcg/i386: Implement avx512 variable shifts Richard Henderson
` (22 subsequent siblings)
30 siblings, 0 replies; 33+ messages in thread
From: Richard Henderson @ 2022-03-03 20:59 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Alex Bennée
The condition for UMIN/UMAX availability is about to change;
use the canonical version.
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/i386/tcg-target.c.inc | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
index 89497b2b45..6a53f378cc 100644
--- a/tcg/i386/tcg-target.c.inc
+++ b/tcg/i386/tcg-target.c.inc
@@ -3620,28 +3620,28 @@ static bool expand_vec_cmp_noinv(TCGType type, unsigned vece, TCGv_vec v0,
fixup = NEED_SWAP | NEED_INV;
break;
case TCG_COND_LEU:
- if (vece <= MO_32) {
+ if (tcg_can_emit_vec_op(INDEX_op_umin_vec, type, vece)) {
fixup = NEED_UMIN;
} else {
fixup = NEED_BIAS | NEED_INV;
}
break;
case TCG_COND_GTU:
- if (vece <= MO_32) {
+ if (tcg_can_emit_vec_op(INDEX_op_umin_vec, type, vece)) {
fixup = NEED_UMIN | NEED_INV;
} else {
fixup = NEED_BIAS;
}
break;
case TCG_COND_GEU:
- if (vece <= MO_32) {
+ if (tcg_can_emit_vec_op(INDEX_op_umax_vec, type, vece)) {
fixup = NEED_UMAX;
} else {
fixup = NEED_BIAS | NEED_SWAP | NEED_INV;
}
break;
case TCG_COND_LTU:
- if (vece <= MO_32) {
+ if (tcg_can_emit_vec_op(INDEX_op_umax_vec, type, vece)) {
fixup = NEED_UMAX | NEED_INV;
} else {
fixup = NEED_BIAS | NEED_SWAP;
--
2.25.1
^ permalink raw reply related [flat|nested] 33+ messages in thread* [PULL 09/30] tcg/i386: Implement avx512 variable shifts
2022-03-03 20:59 [PULL 00/30] tcg patch queue Richard Henderson
` (7 preceding siblings ...)
2022-03-03 20:59 ` [PULL 08/30] tcg/i386: Use tcg_can_emit_vec_op in expand_vec_cmp_noinv Richard Henderson
@ 2022-03-03 20:59 ` Richard Henderson
2022-03-03 20:59 ` [PULL 10/30] tcg/i386: Implement avx512 scalar shift Richard Henderson
` (21 subsequent siblings)
30 siblings, 0 replies; 33+ messages in thread
From: Richard Henderson @ 2022-03-03 20:59 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Alex Bennée
AVX512VL has VPSRAVQ, and
AVX512BW has VPSLLVW, VPSRAVW, VPSRLVW.
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/i386/tcg-target.c.inc | 32 ++++++++++++++++++++++++--------
1 file changed, 24 insertions(+), 8 deletions(-)
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
index 6a53f378cc..055db88422 100644
--- a/tcg/i386/tcg-target.c.inc
+++ b/tcg/i386/tcg-target.c.inc
@@ -419,9 +419,13 @@ static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
#define OPC_VPBROADCASTQ (0x59 | P_EXT38 | P_DATA16)
#define OPC_VPERMQ (0x00 | P_EXT3A | P_DATA16 | P_VEXW)
#define OPC_VPERM2I128 (0x46 | P_EXT3A | P_DATA16 | P_VEXL)
+#define OPC_VPSLLVW (0x12 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX)
#define OPC_VPSLLVD (0x47 | P_EXT38 | P_DATA16)
#define OPC_VPSLLVQ (0x47 | P_EXT38 | P_DATA16 | P_VEXW)
+#define OPC_VPSRAVW (0x11 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX)
#define OPC_VPSRAVD (0x46 | P_EXT38 | P_DATA16)
+#define OPC_VPSRAVQ (0x46 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX)
+#define OPC_VPSRLVW (0x10 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX)
#define OPC_VPSRLVD (0x45 | P_EXT38 | P_DATA16)
#define OPC_VPSRLVQ (0x45 | P_EXT38 | P_DATA16 | P_VEXW)
#define OPC_VZEROUPPER (0x77 | P_EXT)
@@ -2835,16 +2839,13 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
OPC_PMAXUB, OPC_PMAXUW, OPC_PMAXUD, OPC_UD2
};
static int const shlv_insn[4] = {
- /* TODO: AVX512 adds support for MO_16. */
- OPC_UD2, OPC_UD2, OPC_VPSLLVD, OPC_VPSLLVQ
+ OPC_UD2, OPC_VPSLLVW, OPC_VPSLLVD, OPC_VPSLLVQ
};
static int const shrv_insn[4] = {
- /* TODO: AVX512 adds support for MO_16. */
- OPC_UD2, OPC_UD2, OPC_VPSRLVD, OPC_VPSRLVQ
+ OPC_UD2, OPC_VPSRLVW, OPC_VPSRLVD, OPC_VPSRLVQ
};
static int const sarv_insn[4] = {
- /* TODO: AVX512 adds support for MO_16, MO_64. */
- OPC_UD2, OPC_UD2, OPC_VPSRAVD, OPC_UD2
+ OPC_UD2, OPC_VPSRAVW, OPC_VPSRAVD, OPC_VPSRAVQ
};
static int const shls_insn[4] = {
OPC_UD2, OPC_PSLLW, OPC_PSLLD, OPC_PSLLQ
@@ -3335,9 +3336,24 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
case INDEX_op_shlv_vec:
case INDEX_op_shrv_vec:
- return have_avx2 && vece >= MO_32;
+ switch (vece) {
+ case MO_16:
+ return have_avx512bw;
+ case MO_32:
+ case MO_64:
+ return have_avx2;
+ }
+ return 0;
case INDEX_op_sarv_vec:
- return have_avx2 && vece == MO_32;
+ switch (vece) {
+ case MO_16:
+ return have_avx512bw;
+ case MO_32:
+ return have_avx2;
+ case MO_64:
+ return have_avx512vl;
+ }
+ return 0;
case INDEX_op_rotlv_vec:
case INDEX_op_rotrv_vec:
return have_avx2 && vece >= MO_32 ? -1 : 0;
--
2.25.1
^ permalink raw reply related [flat|nested] 33+ messages in thread* [PULL 10/30] tcg/i386: Implement avx512 scalar shift
2022-03-03 20:59 [PULL 00/30] tcg patch queue Richard Henderson
` (8 preceding siblings ...)
2022-03-03 20:59 ` [PULL 09/30] tcg/i386: Implement avx512 variable shifts Richard Henderson
@ 2022-03-03 20:59 ` Richard Henderson
2022-03-03 20:59 ` [PULL 11/30] tcg/i386: Implement avx512 immediate sari shift Richard Henderson
` (20 subsequent siblings)
30 siblings, 0 replies; 33+ messages in thread
From: Richard Henderson @ 2022-03-03 20:59 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Alex Bennée
AVX512VL has VPSRAQ.
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/i386/tcg-target.c.inc | 12 ++++++++++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
index 055db88422..1ef34f0b52 100644
--- a/tcg/i386/tcg-target.c.inc
+++ b/tcg/i386/tcg-target.c.inc
@@ -369,6 +369,7 @@ static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
#define OPC_PSLLQ (0xf3 | P_EXT | P_DATA16)
#define OPC_PSRAW (0xe1 | P_EXT | P_DATA16)
#define OPC_PSRAD (0xe2 | P_EXT | P_DATA16)
+#define OPC_VPSRAQ (0x72 | P_EXT | P_DATA16 | P_VEXW | P_EVEX)
#define OPC_PSRLW (0xd1 | P_EXT | P_DATA16)
#define OPC_PSRLD (0xd2 | P_EXT | P_DATA16)
#define OPC_PSRLQ (0xd3 | P_EXT | P_DATA16)
@@ -2854,7 +2855,7 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
OPC_UD2, OPC_PSRLW, OPC_PSRLD, OPC_PSRLQ
};
static int const sars_insn[4] = {
- OPC_UD2, OPC_PSRAW, OPC_PSRAD, OPC_UD2
+ OPC_UD2, OPC_PSRAW, OPC_PSRAD, OPC_VPSRAQ
};
static int const abs_insn[4] = {
/* TODO: AVX512 adds support for MO_64. */
@@ -3330,7 +3331,14 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
case INDEX_op_shrs_vec:
return vece >= MO_16;
case INDEX_op_sars_vec:
- return vece >= MO_16 && vece <= MO_32;
+ switch (vece) {
+ case MO_16:
+ case MO_32:
+ return 1;
+ case MO_64:
+ return have_avx512vl;
+ }
+ return 0;
case INDEX_op_rotls_vec:
return vece >= MO_16 ? -1 : 0;
--
2.25.1
^ permalink raw reply related [flat|nested] 33+ messages in thread* [PULL 11/30] tcg/i386: Implement avx512 immediate sari shift
2022-03-03 20:59 [PULL 00/30] tcg patch queue Richard Henderson
` (9 preceding siblings ...)
2022-03-03 20:59 ` [PULL 10/30] tcg/i386: Implement avx512 scalar shift Richard Henderson
@ 2022-03-03 20:59 ` Richard Henderson
2022-03-03 20:59 ` [PULL 12/30] tcg/i386: Implement avx512 immediate rotate Richard Henderson
` (19 subsequent siblings)
30 siblings, 0 replies; 33+ messages in thread
From: Richard Henderson @ 2022-03-03 20:59 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Alex Bennée
AVX512 has VPSRAQ with immediate operand, in the same form as
with AVX, but requires EVEX encoding and W1.
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/i386/tcg-target.c.inc | 30 +++++++++++++++++++++---------
1 file changed, 21 insertions(+), 9 deletions(-)
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
index 1ef34f0b52..de01fbf40c 100644
--- a/tcg/i386/tcg-target.c.inc
+++ b/tcg/i386/tcg-target.c.inc
@@ -2986,17 +2986,22 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
break;
case INDEX_op_shli_vec:
+ insn = shift_imm_insn[vece];
sub = 6;
goto gen_shift;
case INDEX_op_shri_vec:
+ insn = shift_imm_insn[vece];
sub = 2;
goto gen_shift;
case INDEX_op_sari_vec:
- tcg_debug_assert(vece != MO_64);
+ if (vece == MO_64) {
+ insn = OPC_PSHIFTD_Ib | P_VEXW | P_EVEX;
+ } else {
+ insn = shift_imm_insn[vece];
+ }
sub = 4;
gen_shift:
tcg_debug_assert(vece != MO_8);
- insn = shift_imm_insn[vece];
if (type == TCG_TYPE_V256) {
insn |= P_VEXL;
}
@@ -3316,16 +3321,23 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
return vece == MO_8 ? -1 : 1;
case INDEX_op_sari_vec:
- /* We must expand the operation for MO_8. */
- if (vece == MO_8) {
+ switch (vece) {
+ case MO_8:
return -1;
- }
- /* We can emulate this for MO_64, but it does not pay off
- unless we're producing at least 4 values. */
- if (vece == MO_64) {
+ case MO_16:
+ case MO_32:
+ return 1;
+ case MO_64:
+ if (have_avx512vl) {
+ return 1;
+ }
+ /*
+ * We can emulate this for MO_64, but it does not pay off
+ * unless we're producing at least 4 values.
+ */
return type >= TCG_TYPE_V256 ? -1 : 0;
}
- return 1;
+ return 0;
case INDEX_op_shls_vec:
case INDEX_op_shrs_vec:
--
2.25.1
^ permalink raw reply related [flat|nested] 33+ messages in thread* [PULL 12/30] tcg/i386: Implement avx512 immediate rotate
2022-03-03 20:59 [PULL 00/30] tcg patch queue Richard Henderson
` (10 preceding siblings ...)
2022-03-03 20:59 ` [PULL 11/30] tcg/i386: Implement avx512 immediate sari shift Richard Henderson
@ 2022-03-03 20:59 ` Richard Henderson
2022-03-03 20:59 ` [PULL 13/30] tcg/i386: Implement avx512 variable rotate Richard Henderson
` (18 subsequent siblings)
30 siblings, 0 replies; 33+ messages in thread
From: Richard Henderson @ 2022-03-03 20:59 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell
AVX512VL has VPROLD and VPROLQ, layered onto the same
opcode as PSHIFTD, but requires EVEX encoding and W1.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/i386/tcg-target.h | 2 +-
tcg/i386/tcg-target.c.inc | 15 +++++++++++++--
2 files changed, 14 insertions(+), 3 deletions(-)
diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
index 79af353860..23a8b2a8c8 100644
--- a/tcg/i386/tcg-target.h
+++ b/tcg/i386/tcg-target.h
@@ -195,7 +195,7 @@ extern bool have_movbe;
#define TCG_TARGET_HAS_not_vec 0
#define TCG_TARGET_HAS_neg_vec 0
#define TCG_TARGET_HAS_abs_vec 1
-#define TCG_TARGET_HAS_roti_vec 0
+#define TCG_TARGET_HAS_roti_vec have_avx512vl
#define TCG_TARGET_HAS_rots_vec 0
#define TCG_TARGET_HAS_rotv_vec 0
#define TCG_TARGET_HAS_shi_vec 1
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
index de01fbf40c..3a9f6a3360 100644
--- a/tcg/i386/tcg-target.c.inc
+++ b/tcg/i386/tcg-target.c.inc
@@ -362,7 +362,7 @@ static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
#define OPC_PSHUFLW (0x70 | P_EXT | P_SIMDF2)
#define OPC_PSHUFHW (0x70 | P_EXT | P_SIMDF3)
#define OPC_PSHIFTW_Ib (0x71 | P_EXT | P_DATA16) /* /2 /6 /4 */
-#define OPC_PSHIFTD_Ib (0x72 | P_EXT | P_DATA16) /* /2 /6 /4 */
+#define OPC_PSHIFTD_Ib (0x72 | P_EXT | P_DATA16) /* /1 /2 /6 /4 */
#define OPC_PSHIFTQ_Ib (0x73 | P_EXT | P_DATA16) /* /2 /6 /4 */
#define OPC_PSLLW (0xf1 | P_EXT | P_DATA16)
#define OPC_PSLLD (0xf2 | P_EXT | P_DATA16)
@@ -3000,6 +3000,14 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
insn = shift_imm_insn[vece];
}
sub = 4;
+ goto gen_shift;
+ case INDEX_op_rotli_vec:
+ insn = OPC_PSHIFTD_Ib | P_EVEX; /* VPROL[DQ] */
+ if (vece == MO_64) {
+ insn |= P_VEXW;
+ }
+ sub = 1;
+ goto gen_shift;
gen_shift:
tcg_debug_assert(vece != MO_8);
if (type == TCG_TYPE_V256) {
@@ -3289,6 +3297,7 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
case INDEX_op_shli_vec:
case INDEX_op_shri_vec:
case INDEX_op_sari_vec:
+ case INDEX_op_rotli_vec:
case INDEX_op_x86_psrldq_vec:
return C_O1_I1(x, x);
@@ -3310,11 +3319,13 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
case INDEX_op_xor_vec:
case INDEX_op_andc_vec:
return 1;
- case INDEX_op_rotli_vec:
case INDEX_op_cmp_vec:
case INDEX_op_cmpsel_vec:
return -1;
+ case INDEX_op_rotli_vec:
+ return have_avx512vl && vece >= MO_32 ? 1 : -1;
+
case INDEX_op_shli_vec:
case INDEX_op_shri_vec:
/* We must expand the operation for MO_8. */
--
2.25.1
^ permalink raw reply related [flat|nested] 33+ messages in thread* [PULL 13/30] tcg/i386: Implement avx512 variable rotate
2022-03-03 20:59 [PULL 00/30] tcg patch queue Richard Henderson
` (11 preceding siblings ...)
2022-03-03 20:59 ` [PULL 12/30] tcg/i386: Implement avx512 immediate rotate Richard Henderson
@ 2022-03-03 20:59 ` Richard Henderson
2022-03-03 20:59 ` [PULL 14/30] tcg/i386: Support avx512vbmi2 vector shift-double instructions Richard Henderson
` (17 subsequent siblings)
30 siblings, 0 replies; 33+ messages in thread
From: Richard Henderson @ 2022-03-03 20:59 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Alex Bennée
AVX512VL has VPROLVD and VPRORVQ.
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/i386/tcg-target.h | 2 +-
tcg/i386/tcg-target.c.inc | 25 ++++++++++++++++++++++++-
2 files changed, 25 insertions(+), 2 deletions(-)
diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
index 23a8b2a8c8..da1eff59aa 100644
--- a/tcg/i386/tcg-target.h
+++ b/tcg/i386/tcg-target.h
@@ -197,7 +197,7 @@ extern bool have_movbe;
#define TCG_TARGET_HAS_abs_vec 1
#define TCG_TARGET_HAS_roti_vec have_avx512vl
#define TCG_TARGET_HAS_rots_vec 0
-#define TCG_TARGET_HAS_rotv_vec 0
+#define TCG_TARGET_HAS_rotv_vec have_avx512vl
#define TCG_TARGET_HAS_shi_vec 1
#define TCG_TARGET_HAS_shs_vec 1
#define TCG_TARGET_HAS_shv_vec have_avx2
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
index 3a9f6a3360..712ae3a168 100644
--- a/tcg/i386/tcg-target.c.inc
+++ b/tcg/i386/tcg-target.c.inc
@@ -420,6 +420,10 @@ static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
#define OPC_VPBROADCASTQ (0x59 | P_EXT38 | P_DATA16)
#define OPC_VPERMQ (0x00 | P_EXT3A | P_DATA16 | P_VEXW)
#define OPC_VPERM2I128 (0x46 | P_EXT3A | P_DATA16 | P_VEXL)
+#define OPC_VPROLVD (0x15 | P_EXT38 | P_DATA16 | P_EVEX)
+#define OPC_VPROLVQ (0x15 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX)
+#define OPC_VPRORVD (0x14 | P_EXT38 | P_DATA16 | P_EVEX)
+#define OPC_VPRORVQ (0x14 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX)
#define OPC_VPSLLVW (0x12 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX)
#define OPC_VPSLLVD (0x47 | P_EXT38 | P_DATA16)
#define OPC_VPSLLVQ (0x47 | P_EXT38 | P_DATA16 | P_VEXW)
@@ -2839,6 +2843,12 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
static int const umax_insn[4] = {
OPC_PMAXUB, OPC_PMAXUW, OPC_PMAXUD, OPC_UD2
};
+ static int const rotlv_insn[4] = {
+ OPC_UD2, OPC_UD2, OPC_VPROLVD, OPC_VPROLVQ
+ };
+ static int const rotrv_insn[4] = {
+ OPC_UD2, OPC_UD2, OPC_VPRORVD, OPC_VPRORVQ
+ };
static int const shlv_insn[4] = {
OPC_UD2, OPC_VPSLLVW, OPC_VPSLLVD, OPC_VPSLLVQ
};
@@ -2922,6 +2932,12 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
case INDEX_op_sarv_vec:
insn = sarv_insn[vece];
goto gen_simd;
+ case INDEX_op_rotlv_vec:
+ insn = rotlv_insn[vece];
+ goto gen_simd;
+ case INDEX_op_rotrv_vec:
+ insn = rotrv_insn[vece];
+ goto gen_simd;
case INDEX_op_shls_vec:
insn = shls_insn[vece];
goto gen_simd;
@@ -3275,6 +3291,8 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
case INDEX_op_shlv_vec:
case INDEX_op_shrv_vec:
case INDEX_op_sarv_vec:
+ case INDEX_op_rotlv_vec:
+ case INDEX_op_rotrv_vec:
case INDEX_op_shls_vec:
case INDEX_op_shrs_vec:
case INDEX_op_sars_vec:
@@ -3387,7 +3405,12 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
return 0;
case INDEX_op_rotlv_vec:
case INDEX_op_rotrv_vec:
- return have_avx2 && vece >= MO_32 ? -1 : 0;
+ switch (vece) {
+ case MO_32:
+ case MO_64:
+ return have_avx512vl ? 1 : have_avx2 ? -1 : 0;
+ }
+ return 0;
case INDEX_op_mul_vec:
if (vece == MO_8) {
--
2.25.1
^ permalink raw reply related [flat|nested] 33+ messages in thread* [PULL 14/30] tcg/i386: Support avx512vbmi2 vector shift-double instructions
2022-03-03 20:59 [PULL 00/30] tcg patch queue Richard Henderson
` (12 preceding siblings ...)
2022-03-03 20:59 ` [PULL 13/30] tcg/i386: Implement avx512 variable rotate Richard Henderson
@ 2022-03-03 20:59 ` Richard Henderson
2022-03-03 20:59 ` [PULL 15/30] tcg/i386: Expand vector word rotate as avx512vbmi2 shift-double Richard Henderson
` (16 subsequent siblings)
30 siblings, 0 replies; 33+ messages in thread
From: Richard Henderson @ 2022-03-03 20:59 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Alex Bennée
We will use VPSHLD, VPSHLDV and VPSHRDV for 16-bit rotates.
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/i386/tcg-target-con-set.h | 1 +
tcg/i386/tcg-target.opc.h | 3 +++
tcg/i386/tcg-target.c.inc | 38 +++++++++++++++++++++++++++++++++++
3 files changed, 42 insertions(+)
diff --git a/tcg/i386/tcg-target-con-set.h b/tcg/i386/tcg-target-con-set.h
index 78774d1005..91ceb0e1da 100644
--- a/tcg/i386/tcg-target-con-set.h
+++ b/tcg/i386/tcg-target-con-set.h
@@ -45,6 +45,7 @@ C_O1_I2(r, r, rI)
C_O1_I2(x, x, x)
C_N1_I2(r, r, r)
C_N1_I2(r, r, rW)
+C_O1_I3(x, 0, x, x)
C_O1_I3(x, x, x, x)
C_O1_I4(r, r, re, r, 0)
C_O1_I4(r, r, r, ri, ri)
diff --git a/tcg/i386/tcg-target.opc.h b/tcg/i386/tcg-target.opc.h
index 1312941800..b5f403e35e 100644
--- a/tcg/i386/tcg-target.opc.h
+++ b/tcg/i386/tcg-target.opc.h
@@ -33,3 +33,6 @@ DEF(x86_psrldq_vec, 1, 1, 1, IMPLVEC)
DEF(x86_vperm2i128_vec, 1, 2, 1, IMPLVEC)
DEF(x86_punpckl_vec, 1, 2, 0, IMPLVEC)
DEF(x86_punpckh_vec, 1, 2, 0, IMPLVEC)
+DEF(x86_vpshldi_vec, 1, 2, 1, IMPLVEC)
+DEF(x86_vpshldv_vec, 1, 3, 0, IMPLVEC)
+DEF(x86_vpshrdv_vec, 1, 3, 0, IMPLVEC)
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
index 712ae3a168..a39f890a7d 100644
--- a/tcg/i386/tcg-target.c.inc
+++ b/tcg/i386/tcg-target.c.inc
@@ -424,6 +424,15 @@ static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
#define OPC_VPROLVQ (0x15 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX)
#define OPC_VPRORVD (0x14 | P_EXT38 | P_DATA16 | P_EVEX)
#define OPC_VPRORVQ (0x14 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX)
+#define OPC_VPSHLDW (0x70 | P_EXT3A | P_DATA16 | P_VEXW | P_EVEX)
+#define OPC_VPSHLDD (0x71 | P_EXT3A | P_DATA16 | P_EVEX)
+#define OPC_VPSHLDQ (0x71 | P_EXT3A | P_DATA16 | P_VEXW | P_EVEX)
+#define OPC_VPSHLDVW (0x70 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX)
+#define OPC_VPSHLDVD (0x71 | P_EXT38 | P_DATA16 | P_EVEX)
+#define OPC_VPSHLDVQ (0x71 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX)
+#define OPC_VPSHRDVW (0x72 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX)
+#define OPC_VPSHRDVD (0x73 | P_EXT38 | P_DATA16 | P_EVEX)
+#define OPC_VPSHRDVQ (0x73 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX)
#define OPC_VPSLLVW (0x12 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX)
#define OPC_VPSLLVD (0x47 | P_EXT38 | P_DATA16)
#define OPC_VPSLLVQ (0x47 | P_EXT38 | P_DATA16 | P_VEXW)
@@ -2867,6 +2876,15 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
static int const sars_insn[4] = {
OPC_UD2, OPC_PSRAW, OPC_PSRAD, OPC_VPSRAQ
};
+ static int const vpshldi_insn[4] = {
+ OPC_UD2, OPC_VPSHLDW, OPC_VPSHLDD, OPC_VPSHLDQ
+ };
+ static int const vpshldv_insn[4] = {
+ OPC_UD2, OPC_VPSHLDVW, OPC_VPSHLDVD, OPC_VPSHLDVQ
+ };
+ static int const vpshrdv_insn[4] = {
+ OPC_UD2, OPC_VPSHRDVW, OPC_VPSHRDVD, OPC_VPSHRDVQ
+ };
static int const abs_insn[4] = {
/* TODO: AVX512 adds support for MO_64. */
OPC_PABSB, OPC_PABSW, OPC_PABSD, OPC_UD2
@@ -2959,6 +2977,16 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
case INDEX_op_x86_packus_vec:
insn = packus_insn[vece];
goto gen_simd;
+ case INDEX_op_x86_vpshldv_vec:
+ insn = vpshldv_insn[vece];
+ a1 = a2;
+ a2 = args[3];
+ goto gen_simd;
+ case INDEX_op_x86_vpshrdv_vec:
+ insn = vpshrdv_insn[vece];
+ a1 = a2;
+ a2 = args[3];
+ goto gen_simd;
#if TCG_TARGET_REG_BITS == 32
case INDEX_op_dup2_vec:
/* First merge the two 32-bit inputs to a single 64-bit element. */
@@ -3061,7 +3089,12 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
insn = OPC_VPERM2I128;
sub = args[3];
goto gen_simd_imm8;
+ case INDEX_op_x86_vpshldi_vec:
+ insn = vpshldi_insn[vece];
+ sub = args[3];
+ goto gen_simd_imm8;
gen_simd_imm8:
+ tcg_debug_assert(insn != OPC_UD2);
if (type == TCG_TYPE_V256) {
insn |= P_VEXL;
}
@@ -3305,6 +3338,7 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
case INDEX_op_x86_vperm2i128_vec:
case INDEX_op_x86_punpckl_vec:
case INDEX_op_x86_punpckh_vec:
+ case INDEX_op_x86_vpshldi_vec:
#if TCG_TARGET_REG_BITS == 32
case INDEX_op_dup2_vec:
#endif
@@ -3319,6 +3353,10 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
case INDEX_op_x86_psrldq_vec:
return C_O1_I1(x, x);
+ case INDEX_op_x86_vpshldv_vec:
+ case INDEX_op_x86_vpshrdv_vec:
+ return C_O1_I3(x, 0, x, x);
+
case INDEX_op_x86_vpblendvb_vec:
return C_O1_I3(x, x, x, x);
--
2.25.1
^ permalink raw reply related [flat|nested] 33+ messages in thread* [PULL 15/30] tcg/i386: Expand vector word rotate as avx512vbmi2 shift-double
2022-03-03 20:59 [PULL 00/30] tcg patch queue Richard Henderson
` (13 preceding siblings ...)
2022-03-03 20:59 ` [PULL 14/30] tcg/i386: Support avx512vbmi2 vector shift-double instructions Richard Henderson
@ 2022-03-03 20:59 ` Richard Henderson
2022-03-03 20:59 ` [PULL 16/30] tcg/i386: Remove rotls_vec from tcg_target_op_def Richard Henderson
` (15 subsequent siblings)
30 siblings, 0 replies; 33+ messages in thread
From: Richard Henderson @ 2022-03-03 20:59 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Alex Bennée
While there are no specific 16-bit rotate instructions, there
are double-word shifts, which can perform the same operation.
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/i386/tcg-target.c.inc | 18 +++++++++++++++++-
1 file changed, 17 insertions(+), 1 deletion(-)
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
index a39f890a7d..19cf124456 100644
--- a/tcg/i386/tcg-target.c.inc
+++ b/tcg/i386/tcg-target.c.inc
@@ -3444,6 +3444,8 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
case INDEX_op_rotlv_vec:
case INDEX_op_rotrv_vec:
switch (vece) {
+ case MO_16:
+ return have_avx512vbmi2 ? -1 : 0;
case MO_32:
case MO_64:
return have_avx512vl ? 1 : have_avx2 ? -1 : 0;
@@ -3588,6 +3590,12 @@ static void expand_vec_rotli(TCGType type, unsigned vece,
return;
}
+ if (have_avx512vbmi2) {
+ vec_gen_4(INDEX_op_x86_vpshldi_vec, type, vece,
+ tcgv_vec_arg(v0), tcgv_vec_arg(v1), tcgv_vec_arg(v1), imm);
+ return;
+ }
+
t = tcg_temp_new_vec(type);
tcg_gen_shli_vec(vece, t, v1, imm);
tcg_gen_shri_vec(vece, v0, v1, (8 << vece) - imm);
@@ -3618,8 +3626,16 @@ static void expand_vec_rotls(TCGType type, unsigned vece,
static void expand_vec_rotv(TCGType type, unsigned vece, TCGv_vec v0,
TCGv_vec v1, TCGv_vec sh, bool right)
{
- TCGv_vec t = tcg_temp_new_vec(type);
+ TCGv_vec t;
+ if (have_avx512vbmi2) {
+ vec_gen_4(right ? INDEX_op_x86_vpshrdv_vec : INDEX_op_x86_vpshldv_vec,
+ type, vece, tcgv_vec_arg(v0), tcgv_vec_arg(v1),
+ tcgv_vec_arg(v1), tcgv_vec_arg(sh));
+ return;
+ }
+
+ t = tcg_temp_new_vec(type);
tcg_gen_dupi_vec(vece, t, 8 << vece);
tcg_gen_sub_vec(vece, t, t, sh);
if (right) {
--
2.25.1
^ permalink raw reply related [flat|nested] 33+ messages in thread* [PULL 16/30] tcg/i386: Remove rotls_vec from tcg_target_op_def
2022-03-03 20:59 [PULL 00/30] tcg patch queue Richard Henderson
` (14 preceding siblings ...)
2022-03-03 20:59 ` [PULL 15/30] tcg/i386: Expand vector word rotate as avx512vbmi2 shift-double Richard Henderson
@ 2022-03-03 20:59 ` Richard Henderson
2022-03-03 20:59 ` [PULL 17/30] tcg/i386: Expand scalar rotate with avx512 insns Richard Henderson
` (14 subsequent siblings)
30 siblings, 0 replies; 33+ messages in thread
From: Richard Henderson @ 2022-03-03 20:59 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Alex Bennée
There is no such instruction on x86, so we should
not be pretending it has arguments.
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/i386/tcg-target.c.inc | 1 -
1 file changed, 1 deletion(-)
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
index 19cf124456..1fbb4b0593 100644
--- a/tcg/i386/tcg-target.c.inc
+++ b/tcg/i386/tcg-target.c.inc
@@ -3329,7 +3329,6 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
case INDEX_op_shls_vec:
case INDEX_op_shrs_vec:
case INDEX_op_sars_vec:
- case INDEX_op_rotls_vec:
case INDEX_op_cmp_vec:
case INDEX_op_x86_shufps_vec:
case INDEX_op_x86_blend_vec:
--
2.25.1
^ permalink raw reply related [flat|nested] 33+ messages in thread* [PULL 17/30] tcg/i386: Expand scalar rotate with avx512 insns
2022-03-03 20:59 [PULL 00/30] tcg patch queue Richard Henderson
` (15 preceding siblings ...)
2022-03-03 20:59 ` [PULL 16/30] tcg/i386: Remove rotls_vec from tcg_target_op_def Richard Henderson
@ 2022-03-03 20:59 ` Richard Henderson
2022-03-03 20:59 ` [PULL 18/30] tcg/i386: Implement avx512 min/max/abs Richard Henderson
` (13 subsequent siblings)
30 siblings, 0 replies; 33+ messages in thread
From: Richard Henderson @ 2022-03-03 20:59 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Alex Bennée
Expand 32-bit and 64-bit scalar rotate with VPRO[LR]V;
expand 16-bit scalar rotate with VPSHLDV.
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/i386/tcg-target.c.inc | 49 +++++++++++++++++++++++----------------
1 file changed, 29 insertions(+), 20 deletions(-)
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
index 1fbb4b0593..edf0d066e7 100644
--- a/tcg/i386/tcg-target.c.inc
+++ b/tcg/i386/tcg-target.c.inc
@@ -3602,26 +3602,6 @@ static void expand_vec_rotli(TCGType type, unsigned vece,
tcg_temp_free_vec(t);
}
-static void expand_vec_rotls(TCGType type, unsigned vece,
- TCGv_vec v0, TCGv_vec v1, TCGv_i32 lsh)
-{
- TCGv_i32 rsh;
- TCGv_vec t;
-
- tcg_debug_assert(vece != MO_8);
-
- t = tcg_temp_new_vec(type);
- rsh = tcg_temp_new_i32();
-
- tcg_gen_neg_i32(rsh, lsh);
- tcg_gen_andi_i32(rsh, rsh, (8 << vece) - 1);
- tcg_gen_shls_vec(vece, t, v1, lsh);
- tcg_gen_shrs_vec(vece, v0, v1, rsh);
- tcg_gen_or_vec(vece, v0, v0, t);
- tcg_temp_free_vec(t);
- tcg_temp_free_i32(rsh);
-}
-
static void expand_vec_rotv(TCGType type, unsigned vece, TCGv_vec v0,
TCGv_vec v1, TCGv_vec sh, bool right)
{
@@ -3648,6 +3628,35 @@ static void expand_vec_rotv(TCGType type, unsigned vece, TCGv_vec v0,
tcg_temp_free_vec(t);
}
+static void expand_vec_rotls(TCGType type, unsigned vece,
+ TCGv_vec v0, TCGv_vec v1, TCGv_i32 lsh)
+{
+ TCGv_vec t = tcg_temp_new_vec(type);
+
+ tcg_debug_assert(vece != MO_8);
+
+ if (vece >= MO_32 ? have_avx512vl : have_avx512vbmi2) {
+ tcg_gen_dup_i32_vec(vece, t, lsh);
+ if (vece >= MO_32) {
+ tcg_gen_rotlv_vec(vece, v0, v1, t);
+ } else {
+ expand_vec_rotv(type, vece, v0, v1, t, false);
+ }
+ } else {
+ TCGv_i32 rsh = tcg_temp_new_i32();
+
+ tcg_gen_neg_i32(rsh, lsh);
+ tcg_gen_andi_i32(rsh, rsh, (8 << vece) - 1);
+ tcg_gen_shls_vec(vece, t, v1, lsh);
+ tcg_gen_shrs_vec(vece, v0, v1, rsh);
+ tcg_gen_or_vec(vece, v0, v0, t);
+
+ tcg_temp_free_i32(rsh);
+ }
+
+ tcg_temp_free_vec(t);
+}
+
static void expand_vec_mul(TCGType type, unsigned vece,
TCGv_vec v0, TCGv_vec v1, TCGv_vec v2)
{
--
2.25.1
^ permalink raw reply related [flat|nested] 33+ messages in thread* [PULL 18/30] tcg/i386: Implement avx512 min/max/abs
2022-03-03 20:59 [PULL 00/30] tcg patch queue Richard Henderson
` (16 preceding siblings ...)
2022-03-03 20:59 ` [PULL 17/30] tcg/i386: Expand scalar rotate with avx512 insns Richard Henderson
@ 2022-03-03 20:59 ` Richard Henderson
2022-03-03 20:59 ` [PULL 19/30] tcg/i386: Implement avx512 multiply Richard Henderson
` (12 subsequent siblings)
30 siblings, 0 replies; 33+ messages in thread
From: Richard Henderson @ 2022-03-03 20:59 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Alex Bennée
AVX512VL has VPABSQ, VPMAXSQ, VPMAXUQ, VPMINSQ, VPMINUQ.
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/i386/tcg-target.c.inc | 18 +++++++++++-------
1 file changed, 11 insertions(+), 7 deletions(-)
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
index edf0d066e7..be94b82fd6 100644
--- a/tcg/i386/tcg-target.c.inc
+++ b/tcg/i386/tcg-target.c.inc
@@ -313,6 +313,7 @@ static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
#define OPC_PABSB (0x1c | P_EXT38 | P_DATA16)
#define OPC_PABSW (0x1d | P_EXT38 | P_DATA16)
#define OPC_PABSD (0x1e | P_EXT38 | P_DATA16)
+#define OPC_VPABSQ (0x1f | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX)
#define OPC_PACKSSDW (0x6b | P_EXT | P_DATA16)
#define OPC_PACKSSWB (0x63 | P_EXT | P_DATA16)
#define OPC_PACKUSDW (0x2b | P_EXT38 | P_DATA16)
@@ -339,15 +340,19 @@ static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
#define OPC_PMAXSB (0x3c | P_EXT38 | P_DATA16)
#define OPC_PMAXSW (0xee | P_EXT | P_DATA16)
#define OPC_PMAXSD (0x3d | P_EXT38 | P_DATA16)
+#define OPC_VPMAXSQ (0x3d | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX)
#define OPC_PMAXUB (0xde | P_EXT | P_DATA16)
#define OPC_PMAXUW (0x3e | P_EXT38 | P_DATA16)
#define OPC_PMAXUD (0x3f | P_EXT38 | P_DATA16)
+#define OPC_VPMAXUQ (0x3f | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX)
#define OPC_PMINSB (0x38 | P_EXT38 | P_DATA16)
#define OPC_PMINSW (0xea | P_EXT | P_DATA16)
#define OPC_PMINSD (0x39 | P_EXT38 | P_DATA16)
+#define OPC_VPMINSQ (0x39 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX)
#define OPC_PMINUB (0xda | P_EXT | P_DATA16)
#define OPC_PMINUW (0x3a | P_EXT38 | P_DATA16)
#define OPC_PMINUD (0x3b | P_EXT38 | P_DATA16)
+#define OPC_VPMINUQ (0x3b | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX)
#define OPC_PMOVSXBW (0x20 | P_EXT38 | P_DATA16)
#define OPC_PMOVSXWD (0x23 | P_EXT38 | P_DATA16)
#define OPC_PMOVSXDQ (0x25 | P_EXT38 | P_DATA16)
@@ -2841,16 +2846,16 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
OPC_PACKUSWB, OPC_PACKUSDW, OPC_UD2, OPC_UD2
};
static int const smin_insn[4] = {
- OPC_PMINSB, OPC_PMINSW, OPC_PMINSD, OPC_UD2
+ OPC_PMINSB, OPC_PMINSW, OPC_PMINSD, OPC_VPMINSQ
};
static int const smax_insn[4] = {
- OPC_PMAXSB, OPC_PMAXSW, OPC_PMAXSD, OPC_UD2
+ OPC_PMAXSB, OPC_PMAXSW, OPC_PMAXSD, OPC_VPMAXSQ
};
static int const umin_insn[4] = {
- OPC_PMINUB, OPC_PMINUW, OPC_PMINUD, OPC_UD2
+ OPC_PMINUB, OPC_PMINUW, OPC_PMINUD, OPC_VPMINUQ
};
static int const umax_insn[4] = {
- OPC_PMAXUB, OPC_PMAXUW, OPC_PMAXUD, OPC_UD2
+ OPC_PMAXUB, OPC_PMAXUW, OPC_PMAXUD, OPC_VPMAXUQ
};
static int const rotlv_insn[4] = {
OPC_UD2, OPC_UD2, OPC_VPROLVD, OPC_VPROLVQ
@@ -2886,8 +2891,7 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
OPC_UD2, OPC_VPSHRDVW, OPC_VPSHRDVD, OPC_VPSHRDVQ
};
static int const abs_insn[4] = {
- /* TODO: AVX512 adds support for MO_64. */
- OPC_PABSB, OPC_PABSW, OPC_PABSD, OPC_UD2
+ OPC_PABSB, OPC_PABSW, OPC_PABSD, OPC_VPABSQ
};
TCGType type = vecl + TCG_TYPE_V64;
@@ -3471,7 +3475,7 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
case INDEX_op_umin_vec:
case INDEX_op_umax_vec:
case INDEX_op_abs_vec:
- return vece <= MO_32;
+ return vece <= MO_32 || have_avx512vl;
default:
return 0;
--
2.25.1
^ permalink raw reply related [flat|nested] 33+ messages in thread* [PULL 19/30] tcg/i386: Implement avx512 multiply
2022-03-03 20:59 [PULL 00/30] tcg patch queue Richard Henderson
` (17 preceding siblings ...)
2022-03-03 20:59 ` [PULL 18/30] tcg/i386: Implement avx512 min/max/abs Richard Henderson
@ 2022-03-03 20:59 ` Richard Henderson
2022-03-03 20:59 ` [PULL 20/30] tcg/i386: Implement more logical operations for avx512 Richard Henderson
` (11 subsequent siblings)
30 siblings, 0 replies; 33+ messages in thread
From: Richard Henderson @ 2022-03-03 20:59 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Alex Bennée
AVX512DQ has VPMULLQ.
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/i386/tcg-target.c.inc | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
index be94b82fd6..a800764d2f 100644
--- a/tcg/i386/tcg-target.c.inc
+++ b/tcg/i386/tcg-target.c.inc
@@ -361,6 +361,7 @@ static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
#define OPC_PMOVZXDQ (0x35 | P_EXT38 | P_DATA16)
#define OPC_PMULLW (0xd5 | P_EXT | P_DATA16)
#define OPC_PMULLD (0x40 | P_EXT38 | P_DATA16)
+#define OPC_VPMULLQ (0x40 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX)
#define OPC_POR (0xeb | P_EXT | P_DATA16)
#define OPC_PSHUFB (0x00 | P_EXT38 | P_DATA16)
#define OPC_PSHUFD (0x70 | P_EXT | P_DATA16)
@@ -2822,7 +2823,7 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
OPC_PSUBUB, OPC_PSUBUW, OPC_UD2, OPC_UD2
};
static int const mul_insn[4] = {
- OPC_UD2, OPC_PMULLW, OPC_PMULLD, OPC_UD2
+ OPC_UD2, OPC_PMULLW, OPC_PMULLD, OPC_VPMULLQ
};
static int const shift_imm_insn[4] = {
OPC_UD2, OPC_PSHIFTW_Ib, OPC_PSHIFTD_Ib, OPC_PSHIFTQ_Ib
@@ -3456,12 +3457,11 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
return 0;
case INDEX_op_mul_vec:
- if (vece == MO_8) {
- /* We can expand the operation for MO_8. */
+ switch (vece) {
+ case MO_8:
return -1;
- }
- if (vece == MO_64) {
- return 0;
+ case MO_64:
+ return have_avx512dq;
}
return 1;
--
2.25.1
^ permalink raw reply related [flat|nested] 33+ messages in thread* [PULL 20/30] tcg/i386: Implement more logical operations for avx512
2022-03-03 20:59 [PULL 00/30] tcg patch queue Richard Henderson
` (18 preceding siblings ...)
2022-03-03 20:59 ` [PULL 19/30] tcg/i386: Implement avx512 multiply Richard Henderson
@ 2022-03-03 20:59 ` Richard Henderson
2022-03-03 20:59 ` [PULL 21/30] tcg/i386: Implement bitsel " Richard Henderson
` (10 subsequent siblings)
30 siblings, 0 replies; 33+ messages in thread
From: Richard Henderson @ 2022-03-03 20:59 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Alex Bennée
AVX512VL has a general ternary logic operation, VPTERNLOGQ,
which can implement NOT, ORC, NAND, NOR, EQV.
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/i386/tcg-target.h | 10 +++++-----
tcg/i386/tcg-target.c.inc | 34 ++++++++++++++++++++++++++++++++++
2 files changed, 39 insertions(+), 5 deletions(-)
diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
index da1eff59aa..e02cef7575 100644
--- a/tcg/i386/tcg-target.h
+++ b/tcg/i386/tcg-target.h
@@ -188,11 +188,11 @@ extern bool have_movbe;
#define TCG_TARGET_HAS_v256 have_avx2
#define TCG_TARGET_HAS_andc_vec 1
-#define TCG_TARGET_HAS_orc_vec 0
-#define TCG_TARGET_HAS_nand_vec 0
-#define TCG_TARGET_HAS_nor_vec 0
-#define TCG_TARGET_HAS_eqv_vec 0
-#define TCG_TARGET_HAS_not_vec 0
+#define TCG_TARGET_HAS_orc_vec have_avx512vl
+#define TCG_TARGET_HAS_nand_vec have_avx512vl
+#define TCG_TARGET_HAS_nor_vec have_avx512vl
+#define TCG_TARGET_HAS_eqv_vec have_avx512vl
+#define TCG_TARGET_HAS_not_vec have_avx512vl
#define TCG_TARGET_HAS_neg_vec 0
#define TCG_TARGET_HAS_abs_vec 1
#define TCG_TARGET_HAS_roti_vec have_avx512vl
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
index a800764d2f..140a51ce70 100644
--- a/tcg/i386/tcg-target.c.inc
+++ b/tcg/i386/tcg-target.c.inc
@@ -448,6 +448,7 @@ static bool tcg_target_const_match(int64_t val, TCGType type, int ct)
#define OPC_VPSRLVW (0x10 | P_EXT38 | P_DATA16 | P_VEXW | P_EVEX)
#define OPC_VPSRLVD (0x45 | P_EXT38 | P_DATA16)
#define OPC_VPSRLVQ (0x45 | P_EXT38 | P_DATA16 | P_VEXW)
+#define OPC_VPTERNLOGQ (0x25 | P_EXT3A | P_DATA16 | P_VEXW | P_EVEX)
#define OPC_VZEROUPPER (0x77 | P_EXT)
#define OPC_XCHG_ax_r32 (0x90)
@@ -3098,6 +3099,29 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
insn = vpshldi_insn[vece];
sub = args[3];
goto gen_simd_imm8;
+
+ case INDEX_op_not_vec:
+ insn = OPC_VPTERNLOGQ;
+ a2 = a1;
+ sub = 0x33; /* !B */
+ goto gen_simd_imm8;
+ case INDEX_op_nor_vec:
+ insn = OPC_VPTERNLOGQ;
+ sub = 0x11; /* norCB */
+ goto gen_simd_imm8;
+ case INDEX_op_nand_vec:
+ insn = OPC_VPTERNLOGQ;
+ sub = 0x77; /* nandCB */
+ goto gen_simd_imm8;
+ case INDEX_op_eqv_vec:
+ insn = OPC_VPTERNLOGQ;
+ sub = 0x99; /* xnorCB */
+ goto gen_simd_imm8;
+ case INDEX_op_orc_vec:
+ insn = OPC_VPTERNLOGQ;
+ sub = 0xdd; /* orB!C */
+ goto gen_simd_imm8;
+
gen_simd_imm8:
tcg_debug_assert(insn != OPC_UD2);
if (type == TCG_TYPE_V256) {
@@ -3318,6 +3342,10 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
case INDEX_op_or_vec:
case INDEX_op_xor_vec:
case INDEX_op_andc_vec:
+ case INDEX_op_orc_vec:
+ case INDEX_op_nand_vec:
+ case INDEX_op_nor_vec:
+ case INDEX_op_eqv_vec:
case INDEX_op_ssadd_vec:
case INDEX_op_usadd_vec:
case INDEX_op_sssub_vec:
@@ -3350,6 +3378,7 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
case INDEX_op_abs_vec:
case INDEX_op_dup_vec:
+ case INDEX_op_not_vec:
case INDEX_op_shli_vec:
case INDEX_op_shri_vec:
case INDEX_op_sari_vec:
@@ -3378,6 +3407,11 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
case INDEX_op_or_vec:
case INDEX_op_xor_vec:
case INDEX_op_andc_vec:
+ case INDEX_op_orc_vec:
+ case INDEX_op_nand_vec:
+ case INDEX_op_nor_vec:
+ case INDEX_op_eqv_vec:
+ case INDEX_op_not_vec:
return 1;
case INDEX_op_cmp_vec:
case INDEX_op_cmpsel_vec:
--
2.25.1
^ permalink raw reply related [flat|nested] 33+ messages in thread* [PULL 21/30] tcg/i386: Implement bitsel for avx512
2022-03-03 20:59 [PULL 00/30] tcg patch queue Richard Henderson
` (19 preceding siblings ...)
2022-03-03 20:59 ` [PULL 20/30] tcg/i386: Implement more logical operations for avx512 Richard Henderson
@ 2022-03-03 20:59 ` Richard Henderson
2022-03-03 20:59 ` [PULL 22/30] tcg: Add TCG_TARGET_SIGNED_ADDR32 Richard Henderson
` (9 subsequent siblings)
30 siblings, 0 replies; 33+ messages in thread
From: Richard Henderson @ 2022-03-03 20:59 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Alex Bennée
The general ternary logic operation can implement BITSEL.
Funnel the 4-operand operation into three variants of the
3-operand instruction, depending on input operand overlap.
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/i386/tcg-target.h | 2 +-
tcg/i386/tcg-target.c.inc | 20 +++++++++++++++++++-
2 files changed, 20 insertions(+), 2 deletions(-)
diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
index e02cef7575..00fcbe297d 100644
--- a/tcg/i386/tcg-target.h
+++ b/tcg/i386/tcg-target.h
@@ -204,7 +204,7 @@ extern bool have_movbe;
#define TCG_TARGET_HAS_mul_vec 1
#define TCG_TARGET_HAS_sat_vec 1
#define TCG_TARGET_HAS_minmax_vec 1
-#define TCG_TARGET_HAS_bitsel_vec 0
+#define TCG_TARGET_HAS_bitsel_vec have_avx512vl
#define TCG_TARGET_HAS_cmpsel_vec -1
#define TCG_TARGET_deposit_i32_valid(ofs, len) \
diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc
index 140a51ce70..b5c6159853 100644
--- a/tcg/i386/tcg-target.c.inc
+++ b/tcg/i386/tcg-target.c.inc
@@ -2898,7 +2898,7 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
TCGType type = vecl + TCG_TYPE_V64;
int insn, sub;
- TCGArg a0, a1, a2;
+ TCGArg a0, a1, a2, a3;
a0 = args[0];
a1 = args[1];
@@ -3122,6 +3122,22 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
sub = 0xdd; /* orB!C */
goto gen_simd_imm8;
+ case INDEX_op_bitsel_vec:
+ insn = OPC_VPTERNLOGQ;
+ a3 = args[3];
+ if (a0 == a1) {
+ a1 = a2;
+ a2 = a3;
+ sub = 0xca; /* A?B:C */
+ } else if (a0 == a2) {
+ a2 = a3;
+ sub = 0xe2; /* B?A:C */
+ } else {
+ tcg_out_mov(s, type, a0, a3);
+ sub = 0xb8; /* B?C:A */
+ }
+ goto gen_simd_imm8;
+
gen_simd_imm8:
tcg_debug_assert(insn != OPC_UD2);
if (type == TCG_TYPE_V256) {
@@ -3390,6 +3406,7 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
case INDEX_op_x86_vpshrdv_vec:
return C_O1_I3(x, 0, x, x);
+ case INDEX_op_bitsel_vec:
case INDEX_op_x86_vpblendvb_vec:
return C_O1_I3(x, x, x, x);
@@ -3412,6 +3429,7 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
case INDEX_op_nor_vec:
case INDEX_op_eqv_vec:
case INDEX_op_not_vec:
+ case INDEX_op_bitsel_vec:
return 1;
case INDEX_op_cmp_vec:
case INDEX_op_cmpsel_vec:
--
2.25.1
^ permalink raw reply related [flat|nested] 33+ messages in thread* [PULL 22/30] tcg: Add TCG_TARGET_SIGNED_ADDR32
2022-03-03 20:59 [PULL 00/30] tcg patch queue Richard Henderson
` (20 preceding siblings ...)
2022-03-03 20:59 ` [PULL 21/30] tcg/i386: Implement bitsel " Richard Henderson
@ 2022-03-03 20:59 ` Richard Henderson
2022-03-03 20:59 ` [PULL 23/30] accel/tcg: Split out g2h_tlbe Richard Henderson
` (8 subsequent siblings)
30 siblings, 0 replies; 33+ messages in thread
From: Richard Henderson @ 2022-03-03 20:59 UTC (permalink / raw)
To: qemu-devel
Cc: WANG Xuerui, peter.maydell, Alistair Francis, Alex Bennée,
Philippe Mathieu-Daudé
Define as 0 for all tcg hosts. Put this in a separate header,
because we'll want this in places that do not ordinarily have
access to all of tcg/tcg.h.
Reviewed-by: WANG Xuerui <git@xen0n.name>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/aarch64/tcg-target-sa32.h | 1 +
tcg/arm/tcg-target-sa32.h | 1 +
tcg/i386/tcg-target-sa32.h | 1 +
tcg/loongarch64/tcg-target-sa32.h | 1 +
tcg/mips/tcg-target-sa32.h | 1 +
tcg/ppc/tcg-target-sa32.h | 1 +
tcg/riscv/tcg-target-sa32.h | 1 +
tcg/s390x/tcg-target-sa32.h | 1 +
tcg/sparc/tcg-target-sa32.h | 1 +
tcg/tci/tcg-target-sa32.h | 1 +
tcg/tcg.c | 4 ++++
11 files changed, 14 insertions(+)
create mode 100644 tcg/aarch64/tcg-target-sa32.h
create mode 100644 tcg/arm/tcg-target-sa32.h
create mode 100644 tcg/i386/tcg-target-sa32.h
create mode 100644 tcg/loongarch64/tcg-target-sa32.h
create mode 100644 tcg/mips/tcg-target-sa32.h
create mode 100644 tcg/ppc/tcg-target-sa32.h
create mode 100644 tcg/riscv/tcg-target-sa32.h
create mode 100644 tcg/s390x/tcg-target-sa32.h
create mode 100644 tcg/sparc/tcg-target-sa32.h
create mode 100644 tcg/tci/tcg-target-sa32.h
diff --git a/tcg/aarch64/tcg-target-sa32.h b/tcg/aarch64/tcg-target-sa32.h
new file mode 100644
index 0000000000..cb185b1526
--- /dev/null
+++ b/tcg/aarch64/tcg-target-sa32.h
@@ -0,0 +1 @@
+#define TCG_TARGET_SIGNED_ADDR32 0
diff --git a/tcg/arm/tcg-target-sa32.h b/tcg/arm/tcg-target-sa32.h
new file mode 100644
index 0000000000..cb185b1526
--- /dev/null
+++ b/tcg/arm/tcg-target-sa32.h
@@ -0,0 +1 @@
+#define TCG_TARGET_SIGNED_ADDR32 0
diff --git a/tcg/i386/tcg-target-sa32.h b/tcg/i386/tcg-target-sa32.h
new file mode 100644
index 0000000000..cb185b1526
--- /dev/null
+++ b/tcg/i386/tcg-target-sa32.h
@@ -0,0 +1 @@
+#define TCG_TARGET_SIGNED_ADDR32 0
diff --git a/tcg/loongarch64/tcg-target-sa32.h b/tcg/loongarch64/tcg-target-sa32.h
new file mode 100644
index 0000000000..cb185b1526
--- /dev/null
+++ b/tcg/loongarch64/tcg-target-sa32.h
@@ -0,0 +1 @@
+#define TCG_TARGET_SIGNED_ADDR32 0
diff --git a/tcg/mips/tcg-target-sa32.h b/tcg/mips/tcg-target-sa32.h
new file mode 100644
index 0000000000..cb185b1526
--- /dev/null
+++ b/tcg/mips/tcg-target-sa32.h
@@ -0,0 +1 @@
+#define TCG_TARGET_SIGNED_ADDR32 0
diff --git a/tcg/ppc/tcg-target-sa32.h b/tcg/ppc/tcg-target-sa32.h
new file mode 100644
index 0000000000..cb185b1526
--- /dev/null
+++ b/tcg/ppc/tcg-target-sa32.h
@@ -0,0 +1 @@
+#define TCG_TARGET_SIGNED_ADDR32 0
diff --git a/tcg/riscv/tcg-target-sa32.h b/tcg/riscv/tcg-target-sa32.h
new file mode 100644
index 0000000000..cb185b1526
--- /dev/null
+++ b/tcg/riscv/tcg-target-sa32.h
@@ -0,0 +1 @@
+#define TCG_TARGET_SIGNED_ADDR32 0
diff --git a/tcg/s390x/tcg-target-sa32.h b/tcg/s390x/tcg-target-sa32.h
new file mode 100644
index 0000000000..cb185b1526
--- /dev/null
+++ b/tcg/s390x/tcg-target-sa32.h
@@ -0,0 +1 @@
+#define TCG_TARGET_SIGNED_ADDR32 0
diff --git a/tcg/sparc/tcg-target-sa32.h b/tcg/sparc/tcg-target-sa32.h
new file mode 100644
index 0000000000..cb185b1526
--- /dev/null
+++ b/tcg/sparc/tcg-target-sa32.h
@@ -0,0 +1 @@
+#define TCG_TARGET_SIGNED_ADDR32 0
diff --git a/tcg/tci/tcg-target-sa32.h b/tcg/tci/tcg-target-sa32.h
new file mode 100644
index 0000000000..cb185b1526
--- /dev/null
+++ b/tcg/tci/tcg-target-sa32.h
@@ -0,0 +1 @@
+#define TCG_TARGET_SIGNED_ADDR32 0
diff --git a/tcg/tcg.c b/tcg/tcg.c
index 33a97eabdb..8c131293fe 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -61,6 +61,10 @@
#include "exec/log.h"
#include "tcg/tcg-ldst.h"
#include "tcg-internal.h"
+#include "tcg-target-sa32.h"
+
+/* Sanity check for TCG_TARGET_SIGNED_ADDR32. */
+QEMU_BUILD_BUG_ON(TCG_TARGET_REG_BITS == 32 && TCG_TARGET_SIGNED_ADDR32);
#ifdef CONFIG_TCG_INTERPRETER
#include <ffi.h>
--
2.25.1
^ permalink raw reply related [flat|nested] 33+ messages in thread* [PULL 23/30] accel/tcg: Split out g2h_tlbe
2022-03-03 20:59 [PULL 00/30] tcg patch queue Richard Henderson
` (21 preceding siblings ...)
2022-03-03 20:59 ` [PULL 22/30] tcg: Add TCG_TARGET_SIGNED_ADDR32 Richard Henderson
@ 2022-03-03 20:59 ` Richard Henderson
2022-03-03 20:59 ` [PULL 24/30] accel/tcg: Support TCG_TARGET_SIGNED_ADDR32 for softmmu Richard Henderson
` (7 subsequent siblings)
30 siblings, 0 replies; 33+ messages in thread
From: Richard Henderson @ 2022-03-03 20:59 UTC (permalink / raw)
To: qemu-devel
Cc: WANG Xuerui, peter.maydell, Alistair Francis, Alex Bennée,
Philippe Mathieu-Daudé
Create a new function to combine a CPUTLBEntry addend
with the guest address to form a host address.
Reviewed-by: WANG Xuerui <git@xen0n.name>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
accel/tcg/cputlb.c | 24 ++++++++++++++----------
1 file changed, 14 insertions(+), 10 deletions(-)
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index 3b918fe018..0e62aa5d7c 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -91,6 +91,11 @@ static inline size_t sizeof_tlb(CPUTLBDescFast *fast)
return fast->mask + (1 << CPU_TLB_ENTRY_BITS);
}
+static inline uintptr_t g2h_tlbe(const CPUTLBEntry *tlb, target_ulong gaddr)
+{
+ return tlb->addend + (uintptr_t)gaddr;
+}
+
static void tlb_window_reset(CPUTLBDesc *desc, int64_t ns,
size_t max_entries)
{
@@ -986,8 +991,7 @@ static void tlb_reset_dirty_range_locked(CPUTLBEntry *tlb_entry,
if ((addr & (TLB_INVALID_MASK | TLB_MMIO |
TLB_DISCARD_WRITE | TLB_NOTDIRTY)) == 0) {
- addr &= TARGET_PAGE_MASK;
- addr += tlb_entry->addend;
+ addr = g2h_tlbe(tlb_entry, addr & TARGET_PAGE_MASK);
if ((addr - start) < length) {
#if TCG_OVERSIZED_GUEST
tlb_entry->addr_write |= TLB_NOTDIRTY;
@@ -1537,7 +1541,7 @@ tb_page_addr_t get_page_addr_code_hostp(CPUArchState *env, target_ulong addr,
return -1;
}
- p = (void *)((uintptr_t)addr + entry->addend);
+ p = (void *)g2h_tlbe(entry, addr);
if (hostp) {
*hostp = p;
}
@@ -1629,7 +1633,7 @@ static int probe_access_internal(CPUArchState *env, target_ulong addr,
}
/* Everything else is RAM. */
- *phost = (void *)((uintptr_t)addr + entry->addend);
+ *phost = (void *)g2h_tlbe(entry, addr);
return flags;
}
@@ -1737,7 +1741,7 @@ bool tlb_plugin_lookup(CPUState *cpu, target_ulong addr, int mmu_idx,
data->v.io.offset = (iotlbentry->addr & TARGET_PAGE_MASK) + addr;
} else {
data->is_io = false;
- data->v.ram.hostaddr = (void *)((uintptr_t)addr + tlbe->addend);
+ data->v.ram.hostaddr = (void *)g2h_tlbe(tlbe, addr);
}
return true;
} else {
@@ -1836,7 +1840,7 @@ static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr,
goto stop_the_world;
}
- hostaddr = (void *)((uintptr_t)addr + tlbe->addend);
+ hostaddr = (void *)g2h_tlbe(tlbe, addr);
if (unlikely(tlb_addr & TLB_NOTDIRTY)) {
notdirty_write(env_cpu(env), addr, size,
@@ -1967,7 +1971,7 @@ load_helper(CPUArchState *env, target_ulong addr, MemOpIdx oi,
access_type, op ^ (need_swap * MO_BSWAP));
}
- haddr = (void *)((uintptr_t)addr + entry->addend);
+ haddr = (void *)g2h_tlbe(entry, addr);
/*
* Keep these two load_memop separate to ensure that the compiler
@@ -2004,7 +2008,7 @@ load_helper(CPUArchState *env, target_ulong addr, MemOpIdx oi,
return res & MAKE_64BIT_MASK(0, size * 8);
}
- haddr = (void *)((uintptr_t)addr + entry->addend);
+ haddr = (void *)g2h_tlbe(entry, addr);
return load_memop(haddr, op);
}
@@ -2375,7 +2379,7 @@ store_helper(CPUArchState *env, target_ulong addr, uint64_t val,
notdirty_write(env_cpu(env), addr, size, iotlbentry, retaddr);
}
- haddr = (void *)((uintptr_t)addr + entry->addend);
+ haddr = (void *)g2h_tlbe(entry, addr);
/*
* Keep these two store_memop separate to ensure that the compiler
@@ -2400,7 +2404,7 @@ store_helper(CPUArchState *env, target_ulong addr, uint64_t val,
return;
}
- haddr = (void *)((uintptr_t)addr + entry->addend);
+ haddr = (void *)g2h_tlbe(entry, addr);
store_memop(haddr, val, op);
}
--
2.25.1
^ permalink raw reply related [flat|nested] 33+ messages in thread* [PULL 24/30] accel/tcg: Support TCG_TARGET_SIGNED_ADDR32 for softmmu
2022-03-03 20:59 [PULL 00/30] tcg patch queue Richard Henderson
` (22 preceding siblings ...)
2022-03-03 20:59 ` [PULL 23/30] accel/tcg: Split out g2h_tlbe Richard Henderson
@ 2022-03-03 20:59 ` Richard Henderson
2022-03-03 20:59 ` [PULL 25/30] accel/tcg: Add guest_base_signed_addr32 for user-only Richard Henderson
` (6 subsequent siblings)
30 siblings, 0 replies; 33+ messages in thread
From: Richard Henderson @ 2022-03-03 20:59 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Philippe Mathieu-Daudé
When TCG_TARGET_SIGNED_ADDR32 is set, adjust the tlb addend to
allow the 32-bit guest address to be sign extended within the
64-bit host register instead of zero extended.
This will simplify tcg hosts like MIPS, RISC-V, and LoongArch,
which naturally sign-extend 32-bit values, in contrast to x86_64
and AArch64 which zero-extend them.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
accel/tcg/cputlb.c | 12 +++++++++++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index 0e62aa5d7c..0dbc3efbc7 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -40,6 +40,7 @@
#include "qemu/plugin-memory.h"
#endif
#include "tcg/tcg-ldst.h"
+#include "tcg-target-sa32.h"
/* DEBUG defines, enable DEBUG_TLB_LOG to log to the CPU_LOG_MMU target */
/* #define DEBUG_TLB */
@@ -93,6 +94,9 @@ static inline size_t sizeof_tlb(CPUTLBDescFast *fast)
static inline uintptr_t g2h_tlbe(const CPUTLBEntry *tlb, target_ulong gaddr)
{
+ if (TCG_TARGET_SIGNED_ADDR32 && TARGET_LONG_BITS == 32) {
+ return tlb->addend + (int32_t)gaddr;
+ }
return tlb->addend + (uintptr_t)gaddr;
}
@@ -1244,7 +1248,13 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr,
desc->iotlb[index].attrs = attrs;
/* Now calculate the new entry */
- tn.addend = addend - vaddr_page;
+
+ if (TCG_TARGET_SIGNED_ADDR32 && TARGET_LONG_BITS == 32) {
+ tn.addend = addend - (int32_t)vaddr_page;
+ } else {
+ tn.addend = addend - vaddr_page;
+ }
+
if (prot & PAGE_READ) {
tn.addr_read = address;
if (wp_flags & BP_MEM_READ) {
--
2.25.1
^ permalink raw reply related [flat|nested] 33+ messages in thread* [PULL 25/30] accel/tcg: Add guest_base_signed_addr32 for user-only
2022-03-03 20:59 [PULL 00/30] tcg patch queue Richard Henderson
` (23 preceding siblings ...)
2022-03-03 20:59 ` [PULL 24/30] accel/tcg: Support TCG_TARGET_SIGNED_ADDR32 for softmmu Richard Henderson
@ 2022-03-03 20:59 ` Richard Henderson
2022-03-03 20:59 ` [PULL 26/30] linux-user: Support TCG_TARGET_SIGNED_ADDR32 Richard Henderson
` (5 subsequent siblings)
30 siblings, 0 replies; 33+ messages in thread
From: Richard Henderson @ 2022-03-03 20:59 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Philippe Mathieu-Daudé
While the host may prefer to treat 32-bit addresses as signed,
there are edge cases of guests that cannot be implemented with
addresses 0x7fff_ffff and 0x8000_0000 being non-consecutive.
Therefore, default to guest_base_signed_addr32 false, and allow
probe_guest_base to determine whether it is possible to set it
to true. A tcg backend which sets TCG_TARGET_SIGNED_ADDR32 will
have to cope with either setting for user-only.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/exec/cpu-all.h | 16 ++++++++++++++++
include/exec/cpu_ldst.h | 3 ++-
bsd-user/main.c | 4 ++++
linux-user/main.c | 3 +++
4 files changed, 25 insertions(+), 1 deletion(-)
diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h
index 84caf5c3d9..26ecd3c886 100644
--- a/include/exec/cpu-all.h
+++ b/include/exec/cpu-all.h
@@ -146,6 +146,7 @@ static inline void tswap64s(uint64_t *s)
#if defined(CONFIG_USER_ONLY)
#include "exec/user/abitypes.h"
+#include "tcg-target-sa32.h"
/* On some host systems the guest address space is reserved on the host.
* This allows the guest address space to be offset to a convenient location.
@@ -154,6 +155,21 @@ extern uintptr_t guest_base;
extern bool have_guest_base;
extern unsigned long reserved_va;
+#if TCG_TARGET_SIGNED_ADDR32 && TARGET_LONG_BITS == 32
+extern bool guest_base_signed_addr32;
+#else
+#define guest_base_signed_addr32 false
+#endif
+
+static inline void set_guest_base_signed_addr32(void)
+{
+#ifdef guest_base_signed_addr32
+ qemu_build_not_reached();
+#else
+ guest_base_signed_addr32 = true;
+#endif
+}
+
/*
* Limit the guest addresses as best we can.
*
diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h
index da987fe8ad..add45499ee 100644
--- a/include/exec/cpu_ldst.h
+++ b/include/exec/cpu_ldst.h
@@ -87,7 +87,8 @@ static inline abi_ptr cpu_untagged_addr(CPUState *cs, abi_ptr x)
/* All direct uses of g2h and h2g need to go away for usermode softmmu. */
static inline void *g2h_untagged(abi_ptr x)
{
- return (void *)((uintptr_t)(x) + guest_base);
+ uintptr_t hx = guest_base_signed_addr32 ? (int32_t)x : (uintptr_t)x;
+ return (void *)(guest_base + hx);
}
static inline void *g2h(CPUState *cs, abi_ptr x)
diff --git a/bsd-user/main.c b/bsd-user/main.c
index 88d347d05e..c181e54495 100644
--- a/bsd-user/main.c
+++ b/bsd-user/main.c
@@ -54,6 +54,10 @@
int singlestep;
uintptr_t guest_base;
bool have_guest_base;
+#ifndef guest_base_signed_addr32
+bool guest_base_signed_addr32;
+#endif
+
/*
* When running 32-on-64 we should make sure we can fit all of the possible
* guest address space into a contiguous chunk of virtual host memory.
diff --git a/linux-user/main.c b/linux-user/main.c
index fbc9bcfd5f..5d963ddb64 100644
--- a/linux-user/main.c
+++ b/linux-user/main.c
@@ -72,6 +72,9 @@ static const char *seed_optarg;
unsigned long mmap_min_addr;
uintptr_t guest_base;
bool have_guest_base;
+#ifndef guest_base_signed_addr32
+bool guest_base_signed_addr32;
+#endif
/*
* Used to implement backwards-compatibility for the `-strace`, and
--
2.25.1
^ permalink raw reply related [flat|nested] 33+ messages in thread* [PULL 26/30] linux-user: Support TCG_TARGET_SIGNED_ADDR32
2022-03-03 20:59 [PULL 00/30] tcg patch queue Richard Henderson
` (24 preceding siblings ...)
2022-03-03 20:59 ` [PULL 25/30] accel/tcg: Add guest_base_signed_addr32 for user-only Richard Henderson
@ 2022-03-03 20:59 ` Richard Henderson
2022-03-03 20:59 ` [PULL 27/30] tcg/aarch64: " Richard Henderson
` (4 subsequent siblings)
30 siblings, 0 replies; 33+ messages in thread
From: Richard Henderson @ 2022-03-03 20:59 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Alex Bennée, Philippe Mathieu-Daudé
When using reserved_va, which is the default for a 64-bit host
and a 32-bit guest, set guest_base_signed_addr32 if requested
by TCG_TARGET_SIGNED_ADDR32, and the executable layout allows.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
include/exec/cpu-all.h | 4 ---
linux-user/elfload.c | 62 ++++++++++++++++++++++++++++++++++--------
2 files changed, 50 insertions(+), 16 deletions(-)
diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h
index 26ecd3c886..8bea0e069e 100644
--- a/include/exec/cpu-all.h
+++ b/include/exec/cpu-all.h
@@ -269,11 +269,7 @@ extern const TargetPageBits target_page;
#define PAGE_RESET 0x0040
/* For linux-user, indicates that the page is MAP_ANON. */
#define PAGE_ANON 0x0080
-
-#if defined(CONFIG_BSD) && defined(CONFIG_USER_ONLY)
-/* FIXME: Code that sets/uses this is broken and needs to go away. */
#define PAGE_RESERVED 0x0100
-#endif
/* Target-specific bits that will be used via page_get_flags(). */
#define PAGE_TARGET_1 0x0200
#define PAGE_TARGET_2 0x0400
diff --git a/linux-user/elfload.c b/linux-user/elfload.c
index 9628a38361..5522f9e721 100644
--- a/linux-user/elfload.c
+++ b/linux-user/elfload.c
@@ -2482,34 +2482,72 @@ static void pgb_dynamic(const char *image_name, long align)
static void pgb_reserved_va(const char *image_name, abi_ulong guest_loaddr,
abi_ulong guest_hiaddr, long align)
{
- int flags = MAP_ANONYMOUS | MAP_PRIVATE | MAP_NORESERVE;
+ int flags = (MAP_ANONYMOUS | MAP_PRIVATE |
+ MAP_NORESERVE | MAP_FIXED_NOREPLACE);
+ unsigned long local_rva = reserved_va;
+ bool protect_wrap = false;
void *addr, *test;
- if (guest_hiaddr > reserved_va) {
+ if (guest_hiaddr > local_rva) {
error_report("%s: requires more than reserved virtual "
"address space (0x%" PRIx64 " > 0x%lx)",
- image_name, (uint64_t)guest_hiaddr, reserved_va);
+ image_name, (uint64_t)guest_hiaddr, local_rva);
exit(EXIT_FAILURE);
}
- /* Widen the "image" to the entire reserved address space. */
- pgb_static(image_name, 0, reserved_va, align);
+ if (TCG_TARGET_SIGNED_ADDR32 && TARGET_LONG_BITS == 32) {
+ if (guest_loaddr < 0x80000000u && guest_hiaddr > 0x80000000u) {
+ /*
+ * The executable itself wraps on signed addresses.
+ * Without per-page translation, we must keep the
+ * guest address 0x7fff_ffff adjacent to 0x8000_0000
+ * consecutive in host memory: unsigned addresses.
+ */
+ } else {
+ set_guest_base_signed_addr32();
+ if (local_rva <= 0x80000000u) {
+ /* No guest addresses are "negative": win! */
+ } else {
+ /* Begin by allocating the entire address space. */
+ local_rva = 0xfffffffful + 1;
+ protect_wrap = true;
+ }
+ }
+ }
- /* osdep.h defines this as 0 if it's missing */
- flags |= MAP_FIXED_NOREPLACE;
+ /* Widen the "image" to the entire reserved address space. */
+ pgb_static(image_name, 0, local_rva, align);
+ assert(guest_base != 0);
/* Reserve the memory on the host. */
- assert(guest_base != 0);
test = g2h_untagged(0);
- addr = mmap(test, reserved_va, PROT_NONE, flags, -1, 0);
+ addr = mmap(test, local_rva, PROT_NONE, flags, -1, 0);
if (addr == MAP_FAILED || addr != test) {
+ /*
+ * If protect_wrap, we could try again with the original reserved_va
+ * setting, but the edge case of low ulimit vm setting on a 64-bit
+ * host is probably useless.
+ */
error_report("Unable to reserve 0x%lx bytes of virtual address "
- "space at %p (%s) for use as guest address space (check your"
- "virtual memory ulimit setting, min_mmap_addr or reserve less "
- "using -R option)", reserved_va, test, strerror(errno));
+ "space at %p (%s) for use as guest address space "
+ "(check your virtual memory ulimit setting, "
+ "min_mmap_addr or reserve less using -R option)",
+ local_rva, test, strerror(errno));
exit(EXIT_FAILURE);
}
+ if (protect_wrap) {
+ /*
+ * Prevent the page just before 0x80000000 from being allocated.
+ * This prevents a single guest object/allocation from crossing
+ * the signed wrap, and thus being discontiguous in host memory.
+ */
+ page_set_flags(0x7fffffff & TARGET_PAGE_MASK, 0x80000000u,
+ PAGE_RESERVED);
+ /* Adjust guest_base so that 0 is in the middle of the reservation. */
+ guest_base += 0x80000000ul;
+ }
+
qemu_log_mask(CPU_LOG_PAGE, "%s: base @ %p for %lu bytes\n",
__func__, addr, reserved_va);
}
--
2.25.1
^ permalink raw reply related [flat|nested] 33+ messages in thread* [PULL 27/30] tcg/aarch64: Support TCG_TARGET_SIGNED_ADDR32
2022-03-03 20:59 [PULL 00/30] tcg patch queue Richard Henderson
` (25 preceding siblings ...)
2022-03-03 20:59 ` [PULL 26/30] linux-user: Support TCG_TARGET_SIGNED_ADDR32 Richard Henderson
@ 2022-03-03 20:59 ` Richard Henderson
2022-03-03 20:59 ` [PULL 28/30] tcg/mips: " Richard Henderson
` (3 subsequent siblings)
30 siblings, 0 replies; 33+ messages in thread
From: Richard Henderson @ 2022-03-03 20:59 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell
AArch64 has both sign and zero-extending addressing modes, which
means that either treatment of guest addresses is equally efficient.
Enabling this for AArch64 gives us testing of the feature in CI.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/aarch64/tcg-target-sa32.h | 8 +++-
tcg/aarch64/tcg-target.c.inc | 81 ++++++++++++++++++++++++-----------
2 files changed, 64 insertions(+), 25 deletions(-)
diff --git a/tcg/aarch64/tcg-target-sa32.h b/tcg/aarch64/tcg-target-sa32.h
index cb185b1526..c99e502e4c 100644
--- a/tcg/aarch64/tcg-target-sa32.h
+++ b/tcg/aarch64/tcg-target-sa32.h
@@ -1 +1,7 @@
-#define TCG_TARGET_SIGNED_ADDR32 0
+/*
+ * AArch64 has both SXTW and UXTW addressing modes, which means that
+ * it is agnostic to how guest addresses should be represented.
+ * Because aarch64 is more common than the other hosts that will
+ * want to use this feature, enable it for continuous testing.
+ */
+#define TCG_TARGET_SIGNED_ADDR32 1
diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc
index 077fc51401..4a3edd6963 100644
--- a/tcg/aarch64/tcg-target.c.inc
+++ b/tcg/aarch64/tcg-target.c.inc
@@ -361,6 +361,16 @@ typedef enum {
LDST_LD_S_W = 3, /* load and sign-extend into Wt */
} AArch64LdstType;
+/*
+ * See aarch64/instrs/extendreg/DecodeRegExtend
+ * But note that option<1> == 0 is UNDEFINED for LDR/STR.
+ */
+typedef enum {
+ LDST_EXT_UXTW = 2, /* zero-extend from uint32_t */
+ LDST_EXT_UXTX = 3, /* zero-extend from uint64_t (i.e. no extension) */
+ LDST_EXT_SXTW = 6, /* sign-extend from int32_t */
+} AArch64LdstExt;
+
/* We encode the format of the insn into the beginning of the name, so that
we can have the preprocessor help "typecheck" the insn vs the output
function. Arm didn't provide us with nice names for the formats, so we
@@ -806,12 +816,12 @@ static void tcg_out_insn_3617(TCGContext *s, AArch64Insn insn, bool q,
}
static void tcg_out_insn_3310(TCGContext *s, AArch64Insn insn,
- TCGReg rd, TCGReg base, TCGType ext,
+ TCGReg rd, TCGReg base, AArch64LdstExt option,
TCGReg regoff)
{
/* Note the AArch64Insn constants above are for C3.3.12. Adjust. */
tcg_out32(s, insn | I3312_TO_I3310 | regoff << 16 |
- 0x4000 | ext << 13 | base << 5 | (rd & 0x1f));
+ option << 13 | base << 5 | (rd & 0x1f));
}
static void tcg_out_insn_3312(TCGContext *s, AArch64Insn insn,
@@ -1126,7 +1136,7 @@ static void tcg_out_ldst(TCGContext *s, AArch64Insn insn, TCGReg rd,
/* Worst-case scenario, move offset to temp register, use reg offset. */
tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_TMP, offset);
- tcg_out_ldst_r(s, insn, rd, rn, TCG_TYPE_I64, TCG_REG_TMP);
+ tcg_out_ldst_r(s, insn, rd, rn, LDST_EXT_UXTX, TCG_REG_TMP);
}
static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
@@ -1765,31 +1775,31 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
static void tcg_out_qemu_ld_direct(TCGContext *s, MemOp memop, TCGType ext,
TCGReg data_r, TCGReg addr_r,
- TCGType otype, TCGReg off_r)
+ AArch64LdstExt option, TCGReg off_r)
{
switch (memop & MO_SSIZE) {
case MO_UB:
- tcg_out_ldst_r(s, I3312_LDRB, data_r, addr_r, otype, off_r);
+ tcg_out_ldst_r(s, I3312_LDRB, data_r, addr_r, option, off_r);
break;
case MO_SB:
tcg_out_ldst_r(s, ext ? I3312_LDRSBX : I3312_LDRSBW,
- data_r, addr_r, otype, off_r);
+ data_r, addr_r, option, off_r);
break;
case MO_UW:
- tcg_out_ldst_r(s, I3312_LDRH, data_r, addr_r, otype, off_r);
+ tcg_out_ldst_r(s, I3312_LDRH, data_r, addr_r, option, off_r);
break;
case MO_SW:
tcg_out_ldst_r(s, (ext ? I3312_LDRSHX : I3312_LDRSHW),
- data_r, addr_r, otype, off_r);
+ data_r, addr_r, option, off_r);
break;
case MO_UL:
- tcg_out_ldst_r(s, I3312_LDRW, data_r, addr_r, otype, off_r);
+ tcg_out_ldst_r(s, I3312_LDRW, data_r, addr_r, option, off_r);
break;
case MO_SL:
- tcg_out_ldst_r(s, I3312_LDRSWX, data_r, addr_r, otype, off_r);
+ tcg_out_ldst_r(s, I3312_LDRSWX, data_r, addr_r, option, off_r);
break;
case MO_UQ:
- tcg_out_ldst_r(s, I3312_LDRX, data_r, addr_r, otype, off_r);
+ tcg_out_ldst_r(s, I3312_LDRX, data_r, addr_r, option, off_r);
break;
default:
tcg_abort();
@@ -1798,31 +1808,52 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, MemOp memop, TCGType ext,
static void tcg_out_qemu_st_direct(TCGContext *s, MemOp memop,
TCGReg data_r, TCGReg addr_r,
- TCGType otype, TCGReg off_r)
+ AArch64LdstExt option, TCGReg off_r)
{
switch (memop & MO_SIZE) {
case MO_8:
- tcg_out_ldst_r(s, I3312_STRB, data_r, addr_r, otype, off_r);
+ tcg_out_ldst_r(s, I3312_STRB, data_r, addr_r, option, off_r);
break;
case MO_16:
- tcg_out_ldst_r(s, I3312_STRH, data_r, addr_r, otype, off_r);
+ tcg_out_ldst_r(s, I3312_STRH, data_r, addr_r, option, off_r);
break;
case MO_32:
- tcg_out_ldst_r(s, I3312_STRW, data_r, addr_r, otype, off_r);
+ tcg_out_ldst_r(s, I3312_STRW, data_r, addr_r, option, off_r);
break;
case MO_64:
- tcg_out_ldst_r(s, I3312_STRX, data_r, addr_r, otype, off_r);
+ tcg_out_ldst_r(s, I3312_STRX, data_r, addr_r, option, off_r);
break;
default:
tcg_abort();
}
}
+/*
+ * Bits for the option field of LDR/STR (register),
+ * for application to a guest address.
+ */
+static AArch64LdstExt ldst_ext_option(void)
+{
+#ifdef CONFIG_USER_ONLY
+ bool signed_addr32 = guest_base_signed_addr32;
+#else
+ bool signed_addr32 = TCG_TARGET_SIGNED_ADDR32;
+#endif
+
+ if (TARGET_LONG_BITS == 64) {
+ return LDST_EXT_UXTX;
+ } else if (signed_addr32) {
+ return LDST_EXT_SXTW;
+ } else {
+ return LDST_EXT_UXTW;
+ }
+}
+
static void tcg_out_qemu_ld(TCGContext *s, TCGReg data_reg, TCGReg addr_reg,
MemOpIdx oi, TCGType ext)
{
MemOp memop = get_memop(oi);
- const TCGType otype = TARGET_LONG_BITS == 64 ? TCG_TYPE_I64 : TCG_TYPE_I32;
+ AArch64LdstExt option = ldst_ext_option();
/* Byte swapping is left to middle-end expansion. */
tcg_debug_assert((memop & MO_BSWAP) == 0);
@@ -1833,7 +1864,7 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg data_reg, TCGReg addr_reg,
tcg_out_tlb_read(s, addr_reg, memop, &label_ptr, mem_index, 1);
tcg_out_qemu_ld_direct(s, memop, ext, data_reg,
- TCG_REG_X1, otype, addr_reg);
+ TCG_REG_X1, option, addr_reg);
add_qemu_ldst_label(s, true, oi, ext, data_reg, addr_reg,
s->code_ptr, label_ptr);
#else /* !CONFIG_SOFTMMU */
@@ -1843,10 +1874,11 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg data_reg, TCGReg addr_reg,
}
if (USE_GUEST_BASE) {
tcg_out_qemu_ld_direct(s, memop, ext, data_reg,
- TCG_REG_GUEST_BASE, otype, addr_reg);
+ TCG_REG_GUEST_BASE, option, addr_reg);
} else {
+ /* This case is always a 64-bit guest with no extension. */
tcg_out_qemu_ld_direct(s, memop, ext, data_reg,
- addr_reg, TCG_TYPE_I64, TCG_REG_XZR);
+ addr_reg, LDST_EXT_UXTX, TCG_REG_XZR);
}
#endif /* CONFIG_SOFTMMU */
}
@@ -1855,7 +1887,7 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg data_reg, TCGReg addr_reg,
MemOpIdx oi)
{
MemOp memop = get_memop(oi);
- const TCGType otype = TARGET_LONG_BITS == 64 ? TCG_TYPE_I64 : TCG_TYPE_I32;
+ AArch64LdstExt option = ldst_ext_option();
/* Byte swapping is left to middle-end expansion. */
tcg_debug_assert((memop & MO_BSWAP) == 0);
@@ -1866,7 +1898,7 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg data_reg, TCGReg addr_reg,
tcg_out_tlb_read(s, addr_reg, memop, &label_ptr, mem_index, 0);
tcg_out_qemu_st_direct(s, memop, data_reg,
- TCG_REG_X1, otype, addr_reg);
+ TCG_REG_X1, option, addr_reg);
add_qemu_ldst_label(s, false, oi, (memop & MO_SIZE)== MO_64,
data_reg, addr_reg, s->code_ptr, label_ptr);
#else /* !CONFIG_SOFTMMU */
@@ -1876,10 +1908,11 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg data_reg, TCGReg addr_reg,
}
if (USE_GUEST_BASE) {
tcg_out_qemu_st_direct(s, memop, data_reg,
- TCG_REG_GUEST_BASE, otype, addr_reg);
+ TCG_REG_GUEST_BASE, option, addr_reg);
} else {
+ /* This case is always a 64-bit guest with no extension. */
tcg_out_qemu_st_direct(s, memop, data_reg,
- addr_reg, TCG_TYPE_I64, TCG_REG_XZR);
+ addr_reg, LDST_EXT_UXTX, TCG_REG_XZR);
}
#endif /* CONFIG_SOFTMMU */
}
--
2.25.1
^ permalink raw reply related [flat|nested] 33+ messages in thread* [PULL 28/30] tcg/mips: Support TCG_TARGET_SIGNED_ADDR32
2022-03-03 20:59 [PULL 00/30] tcg patch queue Richard Henderson
` (26 preceding siblings ...)
2022-03-03 20:59 ` [PULL 27/30] tcg/aarch64: " Richard Henderson
@ 2022-03-03 20:59 ` Richard Henderson
2022-03-03 20:59 ` [PULL 29/30] tcg/riscv: " Richard Henderson
` (2 subsequent siblings)
30 siblings, 0 replies; 33+ messages in thread
From: Richard Henderson @ 2022-03-03 20:59 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Philippe Mathieu-Daudé
All 32-bit mips operations sign-extend the output, so we are easily
able to keep TCG_TYPE_I32 values sign-extended in host registers.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/mips/tcg-target-sa32.h | 8 ++++++++
tcg/mips/tcg-target.c.inc | 10 ++--------
2 files changed, 10 insertions(+), 8 deletions(-)
diff --git a/tcg/mips/tcg-target-sa32.h b/tcg/mips/tcg-target-sa32.h
index cb185b1526..51255e7cba 100644
--- a/tcg/mips/tcg-target-sa32.h
+++ b/tcg/mips/tcg-target-sa32.h
@@ -1 +1,9 @@
+/*
+ * Do not set TCG_TARGET_SIGNED_ADDR32 for mips32;
+ * TCG expects this to only be set for 64-bit hosts.
+ */
+#ifdef __mips64
+#define TCG_TARGET_SIGNED_ADDR32 1
+#else
#define TCG_TARGET_SIGNED_ADDR32 0
+#endif
diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc
index 993149d18a..b97c032ded 100644
--- a/tcg/mips/tcg-target.c.inc
+++ b/tcg/mips/tcg-target.c.inc
@@ -1168,12 +1168,6 @@ static void tcg_out_tlb_load(TCGContext *s, TCGReg base, TCGReg addrl,
TCG_TMP0, TCG_TMP3, cmp_off);
}
- /* Zero extend a 32-bit guest address for a 64-bit host. */
- if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
- tcg_out_ext32u(s, base, addrl);
- addrl = base;
- }
-
/*
* Mask the page bits, keeping the alignment bits to compare against.
* For unaligned accesses, compare against the end of the access to
@@ -1679,7 +1673,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64)
data_regl, data_regh, addr_regl, addr_regh,
s->code_ptr, label_ptr);
#else
- if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
+ if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS && !guest_base_signed_addr32) {
tcg_out_ext32u(s, base, addr_regl);
addr_regl = base;
}
@@ -1878,7 +1872,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64)
data_regl, data_regh, addr_regl, addr_regh,
s->code_ptr, label_ptr);
#else
- if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
+ if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS && !guest_base_signed_addr32) {
tcg_out_ext32u(s, base, addr_regl);
addr_regl = base;
}
--
2.25.1
^ permalink raw reply related [flat|nested] 33+ messages in thread* [PULL 29/30] tcg/riscv: Support TCG_TARGET_SIGNED_ADDR32
2022-03-03 20:59 [PULL 00/30] tcg patch queue Richard Henderson
` (27 preceding siblings ...)
2022-03-03 20:59 ` [PULL 28/30] tcg/mips: " Richard Henderson
@ 2022-03-03 20:59 ` Richard Henderson
2022-03-03 20:59 ` [PULL 30/30] tcg/loongarch64: " Richard Henderson
2022-03-04 15:22 ` [PULL 00/30] tcg patch queue Peter Maydell
30 siblings, 0 replies; 33+ messages in thread
From: Richard Henderson @ 2022-03-03 20:59 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, Alistair Francis, Philippe Mathieu-Daudé
All RV64 32-bit operations sign-extend the output, so we are easily
able to keep TCG_TYPE_I32 values sign-extended in host registers.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/riscv/tcg-target-sa32.h | 6 +++++-
tcg/riscv/tcg-target.c.inc | 8 ++------
2 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/tcg/riscv/tcg-target-sa32.h b/tcg/riscv/tcg-target-sa32.h
index cb185b1526..703467b37a 100644
--- a/tcg/riscv/tcg-target-sa32.h
+++ b/tcg/riscv/tcg-target-sa32.h
@@ -1 +1,5 @@
-#define TCG_TARGET_SIGNED_ADDR32 0
+/*
+ * Do not set TCG_TARGET_SIGNED_ADDR32 for RV32;
+ * TCG expects this to only be set for 64-bit hosts.
+ */
+#define TCG_TARGET_SIGNED_ADDR32 (__riscv_xlen == 64)
diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
index 6409d9c3d5..c999711494 100644
--- a/tcg/riscv/tcg-target.c.inc
+++ b/tcg/riscv/tcg-target.c.inc
@@ -951,10 +951,6 @@ static void tcg_out_tlb_load(TCGContext *s, TCGReg addrl,
tcg_out_opc_branch(s, OPC_BNE, TCG_REG_TMP0, TCG_REG_TMP1, 0);
/* TLB Hit - translate address using addend. */
- if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
- tcg_out_ext32u(s, TCG_REG_TMP0, addrl);
- addrl = TCG_REG_TMP0;
- }
tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, TCG_REG_TMP2, addrl);
}
@@ -1175,7 +1171,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64)
data_regl, data_regh, addr_regl, addr_regh,
s->code_ptr, label_ptr);
#else
- if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
+ if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS && !guest_base_signed_addr32) {
tcg_out_ext32u(s, base, addr_regl);
addr_regl = base;
}
@@ -1247,7 +1243,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64)
data_regl, data_regh, addr_regl, addr_regh,
s->code_ptr, label_ptr);
#else
- if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) {
+ if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS && !guest_base_signed_addr32) {
tcg_out_ext32u(s, base, addr_regl);
addr_regl = base;
}
--
2.25.1
^ permalink raw reply related [flat|nested] 33+ messages in thread* [PULL 30/30] tcg/loongarch64: Support TCG_TARGET_SIGNED_ADDR32
2022-03-03 20:59 [PULL 00/30] tcg patch queue Richard Henderson
` (28 preceding siblings ...)
2022-03-03 20:59 ` [PULL 29/30] tcg/riscv: " Richard Henderson
@ 2022-03-03 20:59 ` Richard Henderson
2022-03-04 15:22 ` [PULL 00/30] tcg patch queue Peter Maydell
30 siblings, 0 replies; 33+ messages in thread
From: Richard Henderson @ 2022-03-03 20:59 UTC (permalink / raw)
To: qemu-devel; +Cc: WANG Xuerui, peter.maydell, Philippe Mathieu-Daudé
All 32-bit LoongArch operations sign-extend the output, so we are easily
able to keep TCG_TYPE_I32 values sign-extended in host registers.
Cc: WANG Xuerui <git@xen0n.name>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/loongarch64/tcg-target-sa32.h | 2 +-
tcg/loongarch64/tcg-target.c.inc | 15 ++++++---------
2 files changed, 7 insertions(+), 10 deletions(-)
diff --git a/tcg/loongarch64/tcg-target-sa32.h b/tcg/loongarch64/tcg-target-sa32.h
index cb185b1526..aaffd777bf 100644
--- a/tcg/loongarch64/tcg-target-sa32.h
+++ b/tcg/loongarch64/tcg-target-sa32.h
@@ -1 +1 @@
-#define TCG_TARGET_SIGNED_ADDR32 0
+#define TCG_TARGET_SIGNED_ADDR32 1
diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc
index a3debf6da7..425f6629ca 100644
--- a/tcg/loongarch64/tcg-target.c.inc
+++ b/tcg/loongarch64/tcg-target.c.inc
@@ -880,8 +880,6 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
return tcg_out_fail_alignment(s, l);
}
-#endif /* CONFIG_SOFTMMU */
-
/*
* `ext32u` the address register into the temp register given,
* if target is 32-bit, no-op otherwise.
@@ -891,12 +889,13 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
static TCGReg tcg_out_zext_addr_if_32_bit(TCGContext *s,
TCGReg addr, TCGReg tmp)
{
- if (TARGET_LONG_BITS == 32) {
+ if (TARGET_LONG_BITS == 32 && !guest_base_signed_addr32) {
tcg_out_ext32u(s, tmp, addr);
return tmp;
}
return addr;
}
+#endif /* CONFIG_SOFTMMU */
static void tcg_out_qemu_ld_indexed(TCGContext *s, TCGReg rd, TCGReg rj,
TCGReg rk, MemOp opc, TCGType type)
@@ -944,8 +943,8 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, TCGType type)
tcg_insn_unit *label_ptr[1];
#else
unsigned a_bits;
-#endif
TCGReg base;
+#endif
data_regl = *args++;
addr_regl = *args++;
@@ -954,8 +953,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, TCGType type)
#if defined(CONFIG_SOFTMMU)
tcg_out_tlb_load(s, addr_regl, oi, label_ptr, 1);
- base = tcg_out_zext_addr_if_32_bit(s, addr_regl, TCG_REG_TMP0);
- tcg_out_qemu_ld_indexed(s, data_regl, base, TCG_REG_TMP2, opc, type);
+ tcg_out_qemu_ld_indexed(s, data_regl, addr_regl, TCG_REG_TMP2, opc, type);
add_qemu_ldst_label(s, 1, oi, type,
data_regl, addr_regl,
s->code_ptr, label_ptr);
@@ -1004,8 +1002,8 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args)
tcg_insn_unit *label_ptr[1];
#else
unsigned a_bits;
-#endif
TCGReg base;
+#endif
data_regl = *args++;
addr_regl = *args++;
@@ -1014,8 +1012,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args)
#if defined(CONFIG_SOFTMMU)
tcg_out_tlb_load(s, addr_regl, oi, label_ptr, 0);
- base = tcg_out_zext_addr_if_32_bit(s, addr_regl, TCG_REG_TMP0);
- tcg_out_qemu_st_indexed(s, data_regl, base, TCG_REG_TMP2, opc);
+ tcg_out_qemu_st_indexed(s, data_regl, addr_regl, TCG_REG_TMP2, opc);
add_qemu_ldst_label(s, 0, oi,
0, /* type param is unused for stores */
data_regl, addr_regl,
--
2.25.1
^ permalink raw reply related [flat|nested] 33+ messages in thread* Re: [PULL 00/30] tcg patch queue
2022-03-03 20:59 [PULL 00/30] tcg patch queue Richard Henderson
` (29 preceding siblings ...)
2022-03-03 20:59 ` [PULL 30/30] tcg/loongarch64: " Richard Henderson
@ 2022-03-04 15:22 ` Peter Maydell
2022-03-04 18:47 ` Richard Henderson
30 siblings, 1 reply; 33+ messages in thread
From: Peter Maydell @ 2022-03-04 15:22 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel
On Thu, 3 Mar 2022 at 20:59, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> The following changes since commit 36eae3a732a1f2aa81391e871ac0e9bb3233e7d7:
>
> Merge remote-tracking branch 'remotes/dgilbert-gitlab/tags/pull-migration-20220302b' into staging (2022-03-02 20:55:48 +0000)
>
> are available in the Git repository at:
>
> https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20220303
>
> for you to fetch changes up to f23e6de25c31cadd9a3b7122f9384e6b259ce37f:
>
> tcg/loongarch64: Support TCG_TARGET_SIGNED_ADDR32 (2022-03-03 10:47:20 -1000)
>
> ----------------------------------------------------------------
> Reorder do_constant_folding_cond test to satisfy valgrind.
> Fix value of MAX_OPC_PARAM_IARGS.
> Add opcodes for vector nand, nor, eqv.
> Support vector nand, nor, eqv on PPC and S390X hosts.
> Support AVX512VL, AVX512BW, AVX512DQ, and AVX512VBMI2.
> Support 32-bit guest addresses as signed values.
>
This causes the linux-user tests to fail on the aarch64 host:
https://gitlab.com/qemu-project/qemu/-/jobs/2163919769
All the qemu-i386 invocations fail like this:
timeout --foreground 90
/home/gitlab-runner/builds/CMuZxyfG/0/qemu-project/qemu/build/qemu-i386
sigbus > sigbus.out
qemu-i386: Unable to reserve 0x100000000 bytes of virtual address
space at 0x8000 (File exists) for use as guest address space (check
your virtual memory ulimit setting, min_mmap_addr or reserve less
using -R option)
The build-oss-fuzz test also failed with a timeout, but it
has a habit of doing that so could be unrelated to these changes:
https://gitlab.com/qemu-project/qemu/-/jobs/2163919743
thanks
-- PMM
^ permalink raw reply [flat|nested] 33+ messages in thread* Re: [PULL 00/30] tcg patch queue
2022-03-04 15:22 ` [PULL 00/30] tcg patch queue Peter Maydell
@ 2022-03-04 18:47 ` Richard Henderson
0 siblings, 0 replies; 33+ messages in thread
From: Richard Henderson @ 2022-03-04 18:47 UTC (permalink / raw)
To: Peter Maydell, Alex Bennée; +Cc: qemu-devel
On 3/4/22 05:22, Peter Maydell wrote:
> This causes the linux-user tests to fail on the aarch64 host:
> https://gitlab.com/qemu-project/qemu/-/jobs/2163919769
>
> All the qemu-i386 invocations fail like this:
>
> timeout --foreground 90
> /home/gitlab-runner/builds/CMuZxyfG/0/qemu-project/qemu/build/qemu-i386
> sigbus > sigbus.out
> qemu-i386: Unable to reserve 0x100000000 bytes of virtual address
> space at 0x8000 (File exists) for use as guest address space (check
> your virtual memory ulimit setting, min_mmap_addr or reserve less
> using -R option)
Hmm. It works when run standalone on aarch64.ci.qemu.org, so it must be something within
the ci environment. Alex, any idea how to replicate this?
r~
^ permalink raw reply [flat|nested] 33+ messages in thread