From: "Cédric Le Goater" <clg@kaod.org>
To: qemu-ppc@nongnu.org, qemu-devel@nongnu.org
Cc: "Peter Maydell" <peter.maydell@linaro.org>,
"Richard Henderson" <richard.henderson@linaro.org>,
"Matheus Ferst" <matheus.ferst@eldorado.org.br>,
"Cédric Le Goater" <clg@kaod.org>
Subject: [PULL 04/13] tests/tcg/ppc64le: drop __int128 usage in bcdsub
Date: Sat, 5 Mar 2022 12:00:01 +0100 [thread overview]
Message-ID: <20220305110010.1283654-5-clg@kaod.org> (raw)
In-Reply-To: <20220305110010.1283654-1-clg@kaod.org>
From: Matheus Ferst <matheus.ferst@eldorado.org.br>
Using __int128 with inline asm constraints like "v" generates incorrect
code when compiling with LLVM/Clang (e.g., only one doubleword of the
VSR is loaded). Instead, use a GPR pair to pass the 128-bits value and
load the VSR with mtvsrd/xxmrghd.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20220304165417.1981159-4-matheus.ferst@eldorado.org.br>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
tests/tcg/ppc64le/bcdsub.c | 129 ++++++++++++++++++-------------------
1 file changed, 61 insertions(+), 68 deletions(-)
diff --git a/tests/tcg/ppc64le/bcdsub.c b/tests/tcg/ppc64le/bcdsub.c
index 8c188cae6d28..12da19b78ef3 100644
--- a/tests/tcg/ppc64le/bcdsub.c
+++ b/tests/tcg/ppc64le/bcdsub.c
@@ -1,6 +1,7 @@
#include <assert.h>
#include <unistd.h>
#include <signal.h>
+#include <stdint.h>
#define CRF_LT (1 << 3)
#define CRF_GT (1 << 2)
@@ -8,24 +9,39 @@
#define CRF_SO (1 << 0)
#define UNDEF 0
-#define BCDSUB(vra, vrb, ps) \
- asm ("bcdsub. %1,%2,%3,%4;" \
- "mfocrf %0,0b10;" \
- : "=r" (cr), "=v" (vrt) \
- : "v" (vra), "v" (vrb), "i" (ps) \
- : );
-
-#define TEST(vra, vrb, ps, exp_res, exp_cr6) \
+/*
+ * Use GPR pairs to load the VSR values and place the resulting VSR and CR6 in
+ * th, tl, and cr. Note that we avoid newer instructions (e.g., mtvsrdd/mfvsrld)
+ * so we can run this test on POWER8 machines.
+ */
+#define BCDSUB(AH, AL, BH, BL, PS) \
+ asm ("mtvsrd 32, %3\n\t" \
+ "mtvsrd 33, %4\n\t" \
+ "xxmrghd 32, 32, 33\n\t" \
+ "mtvsrd 33, %5\n\t" \
+ "mtvsrd 34, %6\n\t" \
+ "xxmrghd 33, 33, 34\n\t" \
+ "bcdsub. 0, 0, 1, %7\n\t" \
+ "mfocrf %0, 0b10\n\t" \
+ "mfvsrd %1, 32\n\t" \
+ "xxswapd 32, 32\n\t" \
+ "mfvsrd %2, 32\n\t" \
+ : "=r" (cr), "=r" (th), "=r" (tl) \
+ : "r" (AH), "r" (AL), "r" (BH), "r" (BL), "i" (PS) \
+ : "v0", "v1", "v2");
+
+#define TEST(AH, AL, BH, BL, PS, TH, TL, CR6) \
do { \
- __int128 vrt = 0; \
int cr = 0; \
- BCDSUB(vra, vrb, ps); \
- if (exp_res) \
- assert(vrt == exp_res); \
- assert((cr >> 4) == exp_cr6); \
+ uint64_t th, tl; \
+ BCDSUB(AH, AL, BH, BL, PS); \
+ if (TH != UNDEF || TL != UNDEF) { \
+ assert(tl == TL); \
+ assert(th == TH); \
+ } \
+ assert((cr >> 4) == CR6); \
} while (0)
-
/*
* Unbounded result is equal to zero:
* sign = (PS) ? 0b1111 : 0b1100
@@ -33,13 +49,13 @@
*/
void test_bcdsub_eq(void)
{
- __int128 a, b;
-
/* maximum positive BCD value */
- a = b = (((__int128) 0x9999999999999999) << 64 | 0x999999999999999c);
-
- TEST(a, b, 0, 0xc, CRF_EQ);
- TEST(a, b, 1, 0xf, CRF_EQ);
+ TEST(0x9999999999999999, 0x999999999999999c,
+ 0x9999999999999999, 0x999999999999999c,
+ 0, 0x0, 0xc, CRF_EQ);
+ TEST(0x9999999999999999, 0x999999999999999c,
+ 0x9999999999999999, 0x999999999999999c,
+ 1, 0x0, 0xf, CRF_EQ);
}
/*
@@ -49,21 +65,16 @@ void test_bcdsub_eq(void)
*/
void test_bcdsub_gt(void)
{
- __int128 a, b, c;
-
- /* maximum positive BCD value */
- a = (((__int128) 0x9999999999999999) << 64 | 0x999999999999999c);
-
- /* negative one BCD value */
- b = (__int128) 0x1d;
-
- TEST(a, b, 0, 0xc, (CRF_GT | CRF_SO));
- TEST(a, b, 1, 0xf, (CRF_GT | CRF_SO));
-
- c = (((__int128) 0x9999999999999999) << 64 | 0x999999999999998c);
-
- TEST(c, b, 0, a, CRF_GT);
- TEST(c, b, 1, (a | 0x3), CRF_GT);
+ /* maximum positive and negative one BCD values */
+ TEST(0x9999999999999999, 0x999999999999999c, 0x0, 0x1d, 0,
+ 0x0, 0xc, (CRF_GT | CRF_SO));
+ TEST(0x9999999999999999, 0x999999999999999c, 0x0, 0x1d, 1,
+ 0x0, 0xf, (CRF_GT | CRF_SO));
+
+ TEST(0x9999999999999999, 0x999999999999998c, 0x0, 0x1d, 0,
+ 0x9999999999999999, 0x999999999999999c, CRF_GT);
+ TEST(0x9999999999999999, 0x999999999999998c, 0x0, 0x1d, 1,
+ 0x9999999999999999, 0x999999999999999f, CRF_GT);
}
/*
@@ -73,45 +84,27 @@ void test_bcdsub_gt(void)
*/
void test_bcdsub_lt(void)
{
- __int128 a, b;
-
- /* positive zero BCD value */
- a = (__int128) 0xc;
-
- /* positive one BCD value */
- b = (__int128) 0x1c;
-
- TEST(a, b, 0, 0x1d, CRF_LT);
- TEST(a, b, 1, 0x1d, CRF_LT);
-
- /* maximum negative BCD value */
- a = (((__int128) 0x9999999999999999) << 64 | 0x999999999999999d);
-
- /* positive one BCD value */
- b = (__int128) 0x1c;
-
- TEST(a, b, 0, 0xd, (CRF_LT | CRF_SO));
- TEST(a, b, 1, 0xd, (CRF_LT | CRF_SO));
+ /* positive zero and positive one BCD values */
+ TEST(0x0, 0xc, 0x0, 0x1c, 0, 0x0, 0x1d, CRF_LT);
+ TEST(0x0, 0xc, 0x0, 0x1c, 1, 0x0, 0x1d, CRF_LT);
+
+ /* maximum negative and positive one BCD values */
+ TEST(0x9999999999999999, 0x999999999999999d, 0x0, 0x1c, 0,
+ 0x0, 0xd, (CRF_LT | CRF_SO));
+ TEST(0x9999999999999999, 0x999999999999999d, 0x0, 0x1c, 1,
+ 0x0, 0xd, (CRF_LT | CRF_SO));
}
void test_bcdsub_invalid(void)
{
- __int128 a, b;
-
- /* positive one BCD value */
- a = (__int128) 0x1c;
- b = 0xf00;
-
- TEST(a, b, 0, UNDEF, CRF_SO);
- TEST(a, b, 1, UNDEF, CRF_SO);
-
- TEST(b, a, 0, UNDEF, CRF_SO);
- TEST(b, a, 1, UNDEF, CRF_SO);
+ TEST(0x0, 0x1c, 0x0, 0xf00, 0, UNDEF, UNDEF, CRF_SO);
+ TEST(0x0, 0x1c, 0x0, 0xf00, 1, UNDEF, UNDEF, CRF_SO);
- a = 0xbad;
+ TEST(0x0, 0xf00, 0x0, 0x1c, 0, UNDEF, UNDEF, CRF_SO);
+ TEST(0x0, 0xf00, 0x0, 0x1c, 1, UNDEF, UNDEF, CRF_SO);
- TEST(a, b, 0, UNDEF, CRF_SO);
- TEST(a, b, 1, UNDEF, CRF_SO);
+ TEST(0x0, 0xbad, 0x0, 0xf00, 0, UNDEF, UNDEF, CRF_SO);
+ TEST(0x0, 0xbad, 0x0, 0xf00, 1, UNDEF, UNDEF, CRF_SO);
}
int main(void)
--
2.34.1
next prev parent reply other threads:[~2022-03-05 11:17 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-03-05 10:59 [PULL 00/13] ppc queue Cédric Le Goater
2022-03-05 10:59 ` [PULL 01/13] Use long endian options for ppc64 Cédric Le Goater
2022-03-05 10:59 ` [PULL 02/13] tests/tcg/ppc64le: use inline asm instead of __builtin_mtfsf Cédric Le Goater
2022-03-05 11:00 ` [PULL 03/13] target/ppc: change xs[n]madd[am]sp to use float64r32_muladd Cédric Le Goater
2022-03-05 11:00 ` Cédric Le Goater [this message]
2022-03-05 11:00 ` [PULL 05/13] tests/tcg/ppc64le: emit bcdsub with .long when needed Cédric Le Goater
2022-03-05 11:00 ` [PULL 06/13] tests/tcg/ppc64le: Use Altivec register names in clobber list Cédric Le Goater
2022-03-05 11:00 ` [PULL 07/13] target/ppc: Fix vmul[eo]* instructions marked 2.07 Cédric Le Goater
2022-03-05 11:00 ` [PULL 08/13] target/ppc: use ext32u and deposit in do_vx_vmulhw_i64 Cédric Le Goater
2022-03-05 11:00 ` [PULL 09/13] target/ppc: use extract/extract2 to create vrlqnm mask Cédric Le Goater
2022-03-05 11:00 ` [PULL 10/13] target/ppc: use andc in vrlqmi Cédric Le Goater
2022-03-05 11:00 ` [PULL 11/13] target/ppc: split XXGENPCV macros for readability Cédric Le Goater
2022-03-05 11:00 ` [PULL 12/13] target/ppc: Add missing helper_reset_fpstatus to VSX_MAX_MINC Cédric Le Goater
2022-03-05 11:00 ` [PULL 13/13] target/ppc: Add missing helper_reset_fpstatus to helper_XVCVSPBF16 Cédric Le Goater
2022-03-06 11:57 ` [PULL 00/13] ppc queue Peter Maydell
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