* [PULL 01/16] target/mips: Fix cycle counter timing calculations
2022-03-07 10:11 [PULL 00/16] MIPS patches for 2022-03-07 Philippe Mathieu-Daudé
@ 2022-03-07 10:11 ` Philippe Mathieu-Daudé
2022-03-07 10:11 ` [PULL 02/16] target/mips: Remove duplicated MIPSCPU::cp0_count_rate Philippe Mathieu-Daudé
` (15 subsequent siblings)
16 siblings, 0 replies; 20+ messages in thread
From: Philippe Mathieu-Daudé @ 2022-03-07 10:11 UTC (permalink / raw)
To: qemu-devel; +Cc: Aleksandar Rikalo, Simon Burge, Philippe Mathieu-Daudé
From: Simon Burge <simonb@NetBSD.org>
The cp0_count_ns value is calculated from the CP0_COUNT_RATE_DEFAULT
constant in target/mips/cpu.c. The cycle counter resolution is defined
per-CPU in target/mips/cpu-defs.c.inc; use this value for calculating
cp0_count_ns. Fixings timing problems on guest OSs for the 20Kc CPU
which has a CCRes of 1.
Signed-off-by: Simon Burge <simonb@NetBSD.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20211213135125.18378-1-simonb@NetBSD.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/cpu.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index 4aae23934b..0766e25693 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -440,8 +440,9 @@ static void mips_cp0_period_set(MIPSCPU *cpu)
{
CPUMIPSState *env = &cpu->env;
+ /* env->CCRes isn't initialised this early, use env->cpu_model->CCRes. */
env->cp0_count_ns = clock_ticks_to_ns(MIPS_CPU(cpu)->clock,
- cpu->cp0_count_rate);
+ env->cpu_model->CCRes);
assert(env->cp0_count_ns);
}
--
2.34.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PULL 02/16] target/mips: Remove duplicated MIPSCPU::cp0_count_rate
2022-03-07 10:11 [PULL 00/16] MIPS patches for 2022-03-07 Philippe Mathieu-Daudé
2022-03-07 10:11 ` [PULL 01/16] target/mips: Fix cycle counter timing calculations Philippe Mathieu-Daudé
@ 2022-03-07 10:11 ` Philippe Mathieu-Daudé
2022-03-07 10:11 ` [PULL 03/16] hw/mips/gt64xxx_pci: Fix PCI IRQ levels to be preserved during migration Philippe Mathieu-Daudé
` (14 subsequent siblings)
16 siblings, 0 replies; 20+ messages in thread
From: Philippe Mathieu-Daudé @ 2022-03-07 10:11 UTC (permalink / raw)
To: qemu-devel
Cc: Aleksandar Rikalo, Richard Henderson, Philippe Mathieu-Daudé
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
Since the previous commit 9ea89876f9d ("target/mips: Fix cycle
counter timing calculations"), MIPSCPU::cp0_count_rate is not
used anymore. We don't need it since it is already expressed
as mips_def_t::CCRes. Remove the duplicate and clean.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <>20211213102340.1847248-1-f4bug@amsat.org>
---
target/mips/cpu.c | 10 ----------
target/mips/cpu.h | 9 ---------
target/mips/internal.h | 9 +++++++++
3 files changed, 9 insertions(+), 19 deletions(-)
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
index 0766e25693..af287177d5 100644
--- a/target/mips/cpu.c
+++ b/target/mips/cpu.c
@@ -434,13 +434,11 @@ static void mips_cpu_disas_set_info(CPUState *s, disassemble_info *info)
* Since commit 6af0bf9c7c3 this model assumes a CPU clocked at 200MHz.
*/
#define CPU_FREQ_HZ_DEFAULT 200000000
-#define CP0_COUNT_RATE_DEFAULT 2
static void mips_cp0_period_set(MIPSCPU *cpu)
{
CPUMIPSState *env = &cpu->env;
- /* env->CCRes isn't initialised this early, use env->cpu_model->CCRes. */
env->cp0_count_ns = clock_ticks_to_ns(MIPS_CPU(cpu)->clock,
env->cpu_model->CCRes);
assert(env->cp0_count_ns);
@@ -515,13 +513,6 @@ static ObjectClass *mips_cpu_class_by_name(const char *cpu_model)
return oc;
}
-static Property mips_cpu_properties[] = {
- /* CP0 timer running at half the clock of the CPU */
- DEFINE_PROP_UINT32("cp0-count-rate", MIPSCPU, cp0_count_rate,
- CP0_COUNT_RATE_DEFAULT),
- DEFINE_PROP_END_OF_LIST()
-};
-
#ifndef CONFIG_USER_ONLY
#include "hw/core/sysemu-cpu-ops.h"
@@ -561,7 +552,6 @@ static void mips_cpu_class_init(ObjectClass *c, void *data)
device_class_set_parent_realize(dc, mips_cpu_realizefn,
&mcc->parent_realize);
device_class_set_parent_reset(dc, mips_cpu_reset, &mcc->parent_reset);
- device_class_set_props(dc, mips_cpu_properties);
cc->class_by_name = mips_cpu_class_by_name;
cc->has_work = mips_cpu_has_work;
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 56b1cbd091..ea66b866c6 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -1168,7 +1168,6 @@ struct CPUMIPSState {
* @env: #CPUMIPSState
* @clock: this CPU input clock (may be connected
* to an output clock from another device).
- * @cp0_count_rate: rate at which the coprocessor 0 counter increments
*
* A MIPS CPU.
*/
@@ -1180,14 +1179,6 @@ struct MIPSCPU {
Clock *clock;
CPUNegativeOffsetState neg;
CPUMIPSState env;
- /*
- * The Count register acts as a timer, incrementing at a constant rate,
- * whether or not an instruction is executed, retired, or any forward
- * progress is made through the pipeline. The rate at which the counter
- * increments is implementation dependent, and is a function of the
- * pipeline clock of the processor, not the issue width of the processor.
- */
- unsigned cp0_count_rate;
};
diff --git a/target/mips/internal.h b/target/mips/internal.h
index daddb05fd4..1526fb880d 100644
--- a/target/mips/internal.h
+++ b/target/mips/internal.h
@@ -46,6 +46,15 @@ struct mips_def_t {
target_ulong CP0_LLAddr_rw_bitmask;
int CP0_LLAddr_shift;
int32_t SYNCI_Step;
+ /*
+ * @CCRes: rate at which the coprocessor 0 counter increments
+ *
+ * The Count register acts as a timer, incrementing at a constant rate,
+ * whether or not an instruction is executed, retired, or any forward
+ * progress is made through the pipeline. The rate at which the counter
+ * increments is implementation dependent, and is a function of the
+ * pipeline clock of the processor, not the issue width of the processor.
+ */
int32_t CCRes;
int32_t CP0_Status_rw_bitmask;
int32_t CP0_TCStatus_rw_bitmask;
--
2.34.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PULL 03/16] hw/mips/gt64xxx_pci: Fix PCI IRQ levels to be preserved during migration
2022-03-07 10:11 [PULL 00/16] MIPS patches for 2022-03-07 Philippe Mathieu-Daudé
2022-03-07 10:11 ` [PULL 01/16] target/mips: Fix cycle counter timing calculations Philippe Mathieu-Daudé
2022-03-07 10:11 ` [PULL 02/16] target/mips: Remove duplicated MIPSCPU::cp0_count_rate Philippe Mathieu-Daudé
@ 2022-03-07 10:11 ` Philippe Mathieu-Daudé
2022-03-07 10:11 ` [PULL 04/16] malta: Move PCI interrupt handling from gt64xxx_pci to piix4 Philippe Mathieu-Daudé
` (13 subsequent siblings)
16 siblings, 0 replies; 20+ messages in thread
From: Philippe Mathieu-Daudé @ 2022-03-07 10:11 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Aleksandar Rikalo, Bernhard Beschow,
Philippe Mathieu-Daudé
From: Bernhard Beschow <shentey@gmail.com>
Based on commit e735b55a8c11dd455e31ccd4420e6c9485191d0c:
piix_pci: eliminate PIIX3State::pci_irq_levels
PIIX3State::pci_irq_levels are redundant which is already tracked by
PCIBus layer. So eliminate them.
The IRQ levels in the PCIBus layer are already preserved during
migration. By reusing them and rather than having a redundant implementation
the bug is avoided in the first place.
Suggested-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <20220217101924.15347-2-shentey@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
hw/mips/gt64xxx_pci.c | 7 ++-----
1 file changed, 2 insertions(+), 5 deletions(-)
diff --git a/hw/mips/gt64xxx_pci.c b/hw/mips/gt64xxx_pci.c
index c7480bd019..4cbd0911f5 100644
--- a/hw/mips/gt64xxx_pci.c
+++ b/hw/mips/gt64xxx_pci.c
@@ -1006,14 +1006,11 @@ static int gt64120_pci_map_irq(PCIDevice *pci_dev, int irq_num)
}
}
-static int pci_irq_levels[4];
-
static void gt64120_pci_set_irq(void *opaque, int irq_num, int level)
{
int i, pic_irq, pic_level;
qemu_irq *pic = opaque;
-
- pci_irq_levels[irq_num] = level;
+ PCIBus *bus = pci_get_bus(piix4_dev);
/* now we change the pic irq level according to the piix irq mappings */
/* XXX: optimize */
@@ -1023,7 +1020,7 @@ static void gt64120_pci_set_irq(void *opaque, int irq_num, int level)
pic_level = 0;
for (i = 0; i < 4; i++) {
if (pic_irq == piix4_dev->config[PIIX_PIRQCA + i]) {
- pic_level |= pci_irq_levels[i];
+ pic_level |= pci_bus_get_irq_level(bus, i);
}
}
qemu_set_irq(pic[pic_irq], pic_level);
--
2.34.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PULL 04/16] malta: Move PCI interrupt handling from gt64xxx_pci to piix4
2022-03-07 10:11 [PULL 00/16] MIPS patches for 2022-03-07 Philippe Mathieu-Daudé
` (2 preceding siblings ...)
2022-03-07 10:11 ` [PULL 03/16] hw/mips/gt64xxx_pci: Fix PCI IRQ levels to be preserved during migration Philippe Mathieu-Daudé
@ 2022-03-07 10:11 ` Philippe Mathieu-Daudé
2022-03-07 10:11 ` [PULL 05/16] hw/isa/piix4: Resolve redundant i8259[] attribute Philippe Mathieu-Daudé
` (12 subsequent siblings)
16 siblings, 0 replies; 20+ messages in thread
From: Philippe Mathieu-Daudé @ 2022-03-07 10:11 UTC (permalink / raw)
To: qemu-devel
Cc: Aleksandar Rikalo, Bernhard Beschow, Philippe Mathieu-Daudé
From: Bernhard Beschow <shentey@gmail.com>
Handling PCI interrupts in piix4 increases cohesion and reduces differences
between piix4 and piix3.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20220217101924.15347-3-shentey@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
hw/isa/piix4.c | 55 ++++++++++++++++++++++++++++++++++++++
hw/mips/gt64xxx_pci.c | 60 ++++--------------------------------------
hw/mips/malta.c | 6 +----
include/hw/mips/mips.h | 2 +-
4 files changed, 62 insertions(+), 61 deletions(-)
diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
index 0fe7b69bc4..196b56e69c 100644
--- a/hw/isa/piix4.c
+++ b/hw/isa/piix4.c
@@ -45,6 +45,7 @@ struct PIIX4State {
PCIDevice dev;
qemu_irq cpu_intr;
qemu_irq *isa;
+ qemu_irq i8259[ISA_NUM_IRQS];
RTCState rtc;
/* Reset Control Register */
@@ -54,6 +55,27 @@ struct PIIX4State {
OBJECT_DECLARE_SIMPLE_TYPE(PIIX4State, PIIX4_PCI_DEVICE)
+static void piix4_set_irq(void *opaque, int irq_num, int level)
+{
+ int i, pic_irq, pic_level;
+ qemu_irq *pic = opaque;
+ PCIBus *bus = pci_get_bus(piix4_dev);
+
+ /* now we change the pic irq level according to the piix irq mappings */
+ /* XXX: optimize */
+ pic_irq = piix4_dev->config[PIIX_PIRQCA + irq_num];
+ if (pic_irq < 16) {
+ /* The pic level is the logical OR of all the PCI irqs mapped to it. */
+ pic_level = 0;
+ for (i = 0; i < 4; i++) {
+ if (pic_irq == piix4_dev->config[PIIX_PIRQCA + i]) {
+ pic_level |= pci_bus_get_irq_level(bus, i);
+ }
+ }
+ qemu_set_irq(pic[pic_irq], pic_level);
+ }
+}
+
static void piix4_isa_reset(DeviceState *dev)
{
PIIX4State *d = PIIX4_PCI_DEVICE(dev);
@@ -248,8 +270,34 @@ static void piix4_register_types(void)
type_init(piix4_register_types)
+static int pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num)
+{
+ int slot;
+
+ slot = PCI_SLOT(pci_dev->devfn);
+
+ switch (slot) {
+ /* PIIX4 USB */
+ case 10:
+ return 3;
+ /* AMD 79C973 Ethernet */
+ case 11:
+ return 1;
+ /* Crystal 4281 Sound */
+ case 12:
+ return 2;
+ /* PCI slot 1 to 4 */
+ case 18 ... 21:
+ return ((slot - 18) + irq_num) & 0x03;
+ /* Unknown device, don't do any translation */
+ default:
+ return irq_num;
+ }
+}
+
DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus, I2CBus **smbus)
{
+ PIIX4State *s;
PCIDevice *pci;
DeviceState *dev;
int devfn = PCI_DEVFN(10, 0);
@@ -257,6 +305,7 @@ DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus, I2CBus **smbus)
pci = pci_create_simple_multifunction(pci_bus, devfn, true,
TYPE_PIIX4_PCI_DEVICE);
dev = DEVICE(pci);
+ s = PIIX4_PCI_DEVICE(pci);
if (isa_bus) {
*isa_bus = ISA_BUS(qdev_get_child_bus(dev, "isa.0"));
}
@@ -271,5 +320,11 @@ DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus, I2CBus **smbus)
NULL, 0, NULL);
}
+ pci_bus_irqs(pci_bus, piix4_set_irq, pci_slot_get_pirq, s->i8259, 4);
+
+ for (int i = 0; i < ISA_NUM_IRQS; i++) {
+ s->i8259[i] = qdev_get_gpio_in_named(dev, "isa", i);
+ }
+
return dev;
}
diff --git a/hw/mips/gt64xxx_pci.c b/hw/mips/gt64xxx_pci.c
index 4cbd0911f5..eb205d6d70 100644
--- a/hw/mips/gt64xxx_pci.c
+++ b/hw/mips/gt64xxx_pci.c
@@ -29,7 +29,6 @@
#include "hw/mips/mips.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_host.h"
-#include "hw/southbridge/piix.h"
#include "migration/vmstate.h"
#include "hw/intc/i8259.h"
#include "hw/irq.h"
@@ -981,53 +980,6 @@ static const MemoryRegionOps isd_mem_ops = {
},
};
-static int gt64120_pci_map_irq(PCIDevice *pci_dev, int irq_num)
-{
- int slot;
-
- slot = PCI_SLOT(pci_dev->devfn);
-
- switch (slot) {
- /* PIIX4 USB */
- case 10:
- return 3;
- /* AMD 79C973 Ethernet */
- case 11:
- return 1;
- /* Crystal 4281 Sound */
- case 12:
- return 2;
- /* PCI slot 1 to 4 */
- case 18 ... 21:
- return ((slot - 18) + irq_num) & 0x03;
- /* Unknown device, don't do any translation */
- default:
- return irq_num;
- }
-}
-
-static void gt64120_pci_set_irq(void *opaque, int irq_num, int level)
-{
- int i, pic_irq, pic_level;
- qemu_irq *pic = opaque;
- PCIBus *bus = pci_get_bus(piix4_dev);
-
- /* now we change the pic irq level according to the piix irq mappings */
- /* XXX: optimize */
- pic_irq = piix4_dev->config[PIIX_PIRQCA + irq_num];
- if (pic_irq < 16) {
- /* The pic level is the logical OR of all the PCI irqs mapped to it. */
- pic_level = 0;
- for (i = 0; i < 4; i++) {
- if (pic_irq == piix4_dev->config[PIIX_PIRQCA + i]) {
- pic_level |= pci_bus_get_irq_level(bus, i);
- }
- }
- qemu_set_irq(pic[pic_irq], pic_level);
- }
-}
-
-
static void gt64120_reset(DeviceState *dev)
{
GT64120State *s = GT64120_PCI_HOST_BRIDGE(dev);
@@ -1204,7 +1156,7 @@ static void gt64120_realize(DeviceState *dev, Error **errp)
"gt64120-isd", 0x1000);
}
-PCIBus *gt64120_register(qemu_irq *pic)
+PCIBus *gt64120_register(void)
{
GT64120State *d;
PCIHostState *phb;
@@ -1215,12 +1167,10 @@ PCIBus *gt64120_register(qemu_irq *pic)
phb = PCI_HOST_BRIDGE(dev);
memory_region_init(&d->pci0_mem, OBJECT(dev), "pci0-mem", 4 * GiB);
address_space_init(&d->pci0_mem_as, &d->pci0_mem, "pci0-mem");
- phb->bus = pci_register_root_bus(dev, "pci",
- gt64120_pci_set_irq, gt64120_pci_map_irq,
- pic,
- &d->pci0_mem,
- get_system_io(),
- PCI_DEVFN(18, 0), 4, TYPE_PCI_BUS);
+ phb->bus = pci_root_bus_new(dev, "pci",
+ &d->pci0_mem,
+ get_system_io(),
+ PCI_DEVFN(18, 0), TYPE_PCI_BUS);
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
pci_create_simple(phb->bus, PCI_DEVFN(0, 0), "gt64120_pci");
diff --git a/hw/mips/malta.c b/hw/mips/malta.c
index b770b8d367..13254dbc89 100644
--- a/hw/mips/malta.c
+++ b/hw/mips/malta.c
@@ -97,7 +97,6 @@ struct MaltaState {
Clock *cpuclk;
MIPSCPSState cps;
- qemu_irq i8259[ISA_NUM_IRQS];
};
static struct _loaderparams {
@@ -1391,7 +1390,7 @@ void mips_malta_init(MachineState *machine)
stl_p(memory_region_get_ram_ptr(bios_copy) + 0x10, 0x00000420);
/* Northbridge */
- pci_bus = gt64120_register(s->i8259);
+ pci_bus = gt64120_register();
/*
* The whole address space decoded by the GT-64120A doesn't generate
* exception when accessing invalid memory. Create an empty slot to
@@ -1404,9 +1403,6 @@ void mips_malta_init(MachineState *machine)
/* Interrupt controller */
qdev_connect_gpio_out_named(dev, "intr", 0, i8259_irq);
- for (int i = 0; i < ISA_NUM_IRQS; i++) {
- s->i8259[i] = qdev_get_gpio_in_named(dev, "isa", i);
- }
/* generate SPD EEPROM data */
generate_eeprom_spd(&smbus_eeprom_buf[0 * 256], ram_size);
diff --git a/include/hw/mips/mips.h b/include/hw/mips/mips.h
index 6c9c8805f3..ff88942e63 100644
--- a/include/hw/mips/mips.h
+++ b/include/hw/mips/mips.h
@@ -10,7 +10,7 @@
#include "exec/memory.h"
/* gt64xxx.c */
-PCIBus *gt64120_register(qemu_irq *pic);
+PCIBus *gt64120_register(void);
/* bonito.c */
PCIBus *bonito_init(qemu_irq *pic);
--
2.34.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PULL 05/16] hw/isa/piix4: Resolve redundant i8259[] attribute
2022-03-07 10:11 [PULL 00/16] MIPS patches for 2022-03-07 Philippe Mathieu-Daudé
` (3 preceding siblings ...)
2022-03-07 10:11 ` [PULL 04/16] malta: Move PCI interrupt handling from gt64xxx_pci to piix4 Philippe Mathieu-Daudé
@ 2022-03-07 10:11 ` Philippe Mathieu-Daudé
2022-03-07 10:11 ` [PULL 06/16] hw/isa/piix4: Pass PIIX4State as opaque parameter for piix4_set_irq() Philippe Mathieu-Daudé
` (11 subsequent siblings)
16 siblings, 0 replies; 20+ messages in thread
From: Philippe Mathieu-Daudé @ 2022-03-07 10:11 UTC (permalink / raw)
To: qemu-devel
Cc: Aleksandar Rikalo, Bernhard Beschow, Philippe Mathieu-Daudé,
Michael S . Tsirkin
From: Bernhard Beschow <shentey@gmail.com>
This is a follow-up on patch "malta: Move PCI interrupt handling from
gt64xxx_pci to piix4" where i8259[] was moved from MaltaState to
PIIX4State to make the code movement more obvious. However, i8259[]
seems redundant to *isa, so remove it.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20220217101924.15347-4-shentey@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
hw/isa/piix4.c | 7 +------
1 file changed, 1 insertion(+), 6 deletions(-)
diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
index 196b56e69c..179968b18e 100644
--- a/hw/isa/piix4.c
+++ b/hw/isa/piix4.c
@@ -45,7 +45,6 @@ struct PIIX4State {
PCIDevice dev;
qemu_irq cpu_intr;
qemu_irq *isa;
- qemu_irq i8259[ISA_NUM_IRQS];
RTCState rtc;
/* Reset Control Register */
@@ -320,11 +319,7 @@ DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus, I2CBus **smbus)
NULL, 0, NULL);
}
- pci_bus_irqs(pci_bus, piix4_set_irq, pci_slot_get_pirq, s->i8259, 4);
-
- for (int i = 0; i < ISA_NUM_IRQS; i++) {
- s->i8259[i] = qdev_get_gpio_in_named(dev, "isa", i);
- }
+ pci_bus_irqs(pci_bus, piix4_set_irq, pci_slot_get_pirq, s->isa, 4);
return dev;
}
--
2.34.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PULL 06/16] hw/isa/piix4: Pass PIIX4State as opaque parameter for piix4_set_irq()
2022-03-07 10:11 [PULL 00/16] MIPS patches for 2022-03-07 Philippe Mathieu-Daudé
` (4 preceding siblings ...)
2022-03-07 10:11 ` [PULL 05/16] hw/isa/piix4: Resolve redundant i8259[] attribute Philippe Mathieu-Daudé
@ 2022-03-07 10:11 ` Philippe Mathieu-Daudé
2022-03-07 10:11 ` [PULL 07/16] hw/isa/piix4: Resolve global instance variable Philippe Mathieu-Daudé
` (10 subsequent siblings)
16 siblings, 0 replies; 20+ messages in thread
From: Philippe Mathieu-Daudé @ 2022-03-07 10:11 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Aleksandar Rikalo, Michael S . Tsirkin,
Philippe Mathieu-Daudé, Bernhard Beschow
From: Bernhard Beschow <shentey@gmail.com>
Passing PIIX4State rather than just the qemu_irq allows for resolving
the global piix4_dev variable.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20220217101924.15347-5-shentey@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
hw/isa/piix4.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
index 179968b18e..caa2002e2c 100644
--- a/hw/isa/piix4.c
+++ b/hw/isa/piix4.c
@@ -57,7 +57,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(PIIX4State, PIIX4_PCI_DEVICE)
static void piix4_set_irq(void *opaque, int irq_num, int level)
{
int i, pic_irq, pic_level;
- qemu_irq *pic = opaque;
+ PIIX4State *s = opaque;
PCIBus *bus = pci_get_bus(piix4_dev);
/* now we change the pic irq level according to the piix irq mappings */
@@ -71,7 +71,7 @@ static void piix4_set_irq(void *opaque, int irq_num, int level)
pic_level |= pci_bus_get_irq_level(bus, i);
}
}
- qemu_set_irq(pic[pic_irq], pic_level);
+ qemu_set_irq(s->isa[pic_irq], pic_level);
}
}
@@ -319,7 +319,7 @@ DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus, I2CBus **smbus)
NULL, 0, NULL);
}
- pci_bus_irqs(pci_bus, piix4_set_irq, pci_slot_get_pirq, s->isa, 4);
+ pci_bus_irqs(pci_bus, piix4_set_irq, pci_slot_get_pirq, s, 4);
return dev;
}
--
2.34.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PULL 07/16] hw/isa/piix4: Resolve global instance variable
2022-03-07 10:11 [PULL 00/16] MIPS patches for 2022-03-07 Philippe Mathieu-Daudé
` (5 preceding siblings ...)
2022-03-07 10:11 ` [PULL 06/16] hw/isa/piix4: Pass PIIX4State as opaque parameter for piix4_set_irq() Philippe Mathieu-Daudé
@ 2022-03-07 10:11 ` Philippe Mathieu-Daudé
2022-03-07 10:11 ` [PULL 08/16] hw/isa/piix4: Replace some magic IRQ constants Philippe Mathieu-Daudé
` (9 subsequent siblings)
16 siblings, 0 replies; 20+ messages in thread
From: Philippe Mathieu-Daudé @ 2022-03-07 10:11 UTC (permalink / raw)
To: qemu-devel
Cc: Aleksandar Rikalo, Bernhard Beschow, Philippe Mathieu-Daudé,
Michael S . Tsirkin
From: Bernhard Beschow <shentey@gmail.com>
Now that piix4_set_irq's opaque parameter references own PIIX4State,
piix4_dev becomes redundant.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20220217101924.15347-6-shentey@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
hw/isa/piix4.c | 10 +++-------
include/hw/southbridge/piix.h | 2 --
2 files changed, 3 insertions(+), 9 deletions(-)
diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
index caa2002e2c..2e9b5ccada 100644
--- a/hw/isa/piix4.c
+++ b/hw/isa/piix4.c
@@ -39,8 +39,6 @@
#include "sysemu/runstate.h"
#include "qom/object.h"
-PCIDevice *piix4_dev;
-
struct PIIX4State {
PCIDevice dev;
qemu_irq cpu_intr;
@@ -58,16 +56,16 @@ static void piix4_set_irq(void *opaque, int irq_num, int level)
{
int i, pic_irq, pic_level;
PIIX4State *s = opaque;
- PCIBus *bus = pci_get_bus(piix4_dev);
+ PCIBus *bus = pci_get_bus(&s->dev);
/* now we change the pic irq level according to the piix irq mappings */
/* XXX: optimize */
- pic_irq = piix4_dev->config[PIIX_PIRQCA + irq_num];
+ pic_irq = s->dev.config[PIIX_PIRQCA + irq_num];
if (pic_irq < 16) {
/* The pic level is the logical OR of all the PCI irqs mapped to it. */
pic_level = 0;
for (i = 0; i < 4; i++) {
- if (pic_irq == piix4_dev->config[PIIX_PIRQCA + i]) {
+ if (pic_irq == s->dev.config[PIIX_PIRQCA + i]) {
pic_level |= pci_bus_get_irq_level(bus, i);
}
}
@@ -219,8 +217,6 @@ static void piix4_realize(PCIDevice *dev, Error **errp)
return;
}
isa_init_irq(ISA_DEVICE(&s->rtc), &s->rtc.irq, RTC_ISA_IRQ);
-
- piix4_dev = dev;
}
static void piix4_init(Object *obj)
diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h
index 6387f2b612..f63f83e5c6 100644
--- a/include/hw/southbridge/piix.h
+++ b/include/hw/southbridge/piix.h
@@ -70,8 +70,6 @@ typedef struct PIIXState PIIX3State;
DECLARE_INSTANCE_CHECKER(PIIX3State, PIIX3_PCI_DEVICE,
TYPE_PIIX3_PCI_DEVICE)
-extern PCIDevice *piix4_dev;
-
PIIX3State *piix3_create(PCIBus *pci_bus, ISABus **isa_bus);
DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus, I2CBus **smbus);
--
2.34.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PULL 08/16] hw/isa/piix4: Replace some magic IRQ constants
2022-03-07 10:11 [PULL 00/16] MIPS patches for 2022-03-07 Philippe Mathieu-Daudé
` (6 preceding siblings ...)
2022-03-07 10:11 ` [PULL 07/16] hw/isa/piix4: Resolve global instance variable Philippe Mathieu-Daudé
@ 2022-03-07 10:11 ` Philippe Mathieu-Daudé
2022-03-07 10:12 ` [PULL 09/16] hw/mips/gt64xxx_pci: Resolve gt64120_register() Philippe Mathieu-Daudé
` (8 subsequent siblings)
16 siblings, 0 replies; 20+ messages in thread
From: Philippe Mathieu-Daudé @ 2022-03-07 10:11 UTC (permalink / raw)
To: qemu-devel
Cc: Aleksandar Rikalo, Bernhard Beschow, Philippe Mathieu-Daudé,
Michael S . Tsirkin
From: Bernhard Beschow <shentey@gmail.com>
This is a follow-up on patch "malta: Move PCI interrupt handling from
gt64xxx_pci to piix4". gt64xxx_pci used magic constants, and probably
didn't want to use piix4-specific constants. Now that the interrupt
handing resides in piix4, its constants can be used.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20220217101924.15347-7-shentey@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
hw/isa/piix4.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
index 2e9b5ccada..f876c71750 100644
--- a/hw/isa/piix4.c
+++ b/hw/isa/piix4.c
@@ -61,10 +61,10 @@ static void piix4_set_irq(void *opaque, int irq_num, int level)
/* now we change the pic irq level according to the piix irq mappings */
/* XXX: optimize */
pic_irq = s->dev.config[PIIX_PIRQCA + irq_num];
- if (pic_irq < 16) {
+ if (pic_irq < ISA_NUM_IRQS) {
/* The pic level is the logical OR of all the PCI irqs mapped to it. */
pic_level = 0;
- for (i = 0; i < 4; i++) {
+ for (i = 0; i < PIIX_NUM_PIRQS; i++) {
if (pic_irq == s->dev.config[PIIX_PIRQCA + i]) {
pic_level |= pci_bus_get_irq_level(bus, i);
}
@@ -315,7 +315,7 @@ DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus, I2CBus **smbus)
NULL, 0, NULL);
}
- pci_bus_irqs(pci_bus, piix4_set_irq, pci_slot_get_pirq, s, 4);
+ pci_bus_irqs(pci_bus, piix4_set_irq, pci_slot_get_pirq, s, PIIX_NUM_PIRQS);
return dev;
}
--
2.34.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PULL 09/16] hw/mips/gt64xxx_pci: Resolve gt64120_register()
2022-03-07 10:11 [PULL 00/16] MIPS patches for 2022-03-07 Philippe Mathieu-Daudé
` (7 preceding siblings ...)
2022-03-07 10:11 ` [PULL 08/16] hw/isa/piix4: Replace some magic IRQ constants Philippe Mathieu-Daudé
@ 2022-03-07 10:12 ` Philippe Mathieu-Daudé
2022-03-07 10:12 ` [PULL 10/16] hw/rtc/mc146818rtc: QOM'ify IRQ number Philippe Mathieu-Daudé
` (7 subsequent siblings)
16 siblings, 0 replies; 20+ messages in thread
From: Philippe Mathieu-Daudé @ 2022-03-07 10:12 UTC (permalink / raw)
To: qemu-devel
Cc: Aleksandar Rikalo, Bernhard Beschow, Philippe Mathieu-Daudé
From: Bernhard Beschow <shentey@gmail.com>
Now that gt64120_register() lost its pic parameter, there is an
opportunity to remove it. gt64120_register() is old style by wrapping
qdev API, and the new style is to use qdev directly. So take the
opportunity and modernize the code.
Suggested-by: BALATON Zoltan <balaton@eik.bme.hu>
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: BALATON Zoltan <balaton@eik.bme.hu>
Message-Id: <20220217101924.15347-8-shentey@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
hw/mips/gt64xxx_pci.c | 21 ++++-----------------
hw/mips/malta.c | 3 ++-
include/hw/mips/mips.h | 3 ---
3 files changed, 6 insertions(+), 21 deletions(-)
diff --git a/hw/mips/gt64xxx_pci.c b/hw/mips/gt64xxx_pci.c
index eb205d6d70..e0ff1b5566 100644
--- a/hw/mips/gt64xxx_pci.c
+++ b/hw/mips/gt64xxx_pci.c
@@ -26,7 +26,6 @@
#include "qapi/error.h"
#include "qemu/units.h"
#include "qemu/log.h"
-#include "hw/mips/mips.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_host.h"
#include "migration/vmstate.h"
@@ -1151,30 +1150,18 @@ static void gt64120_reset(DeviceState *dev)
static void gt64120_realize(DeviceState *dev, Error **errp)
{
GT64120State *s = GT64120_PCI_HOST_BRIDGE(dev);
+ PCIHostState *phb = PCI_HOST_BRIDGE(dev);
memory_region_init_io(&s->ISD_mem, OBJECT(dev), &isd_mem_ops, s,
"gt64120-isd", 0x1000);
-}
-
-PCIBus *gt64120_register(void)
-{
- GT64120State *d;
- PCIHostState *phb;
- DeviceState *dev;
-
- dev = qdev_new(TYPE_GT64120_PCI_HOST_BRIDGE);
- d = GT64120_PCI_HOST_BRIDGE(dev);
- phb = PCI_HOST_BRIDGE(dev);
- memory_region_init(&d->pci0_mem, OBJECT(dev), "pci0-mem", 4 * GiB);
- address_space_init(&d->pci0_mem_as, &d->pci0_mem, "pci0-mem");
+ memory_region_init(&s->pci0_mem, OBJECT(dev), "pci0-mem", 4 * GiB);
+ address_space_init(&s->pci0_mem_as, &s->pci0_mem, "pci0-mem");
phb->bus = pci_root_bus_new(dev, "pci",
- &d->pci0_mem,
+ &s->pci0_mem,
get_system_io(),
PCI_DEVFN(18, 0), TYPE_PCI_BUS);
- sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
pci_create_simple(phb->bus, PCI_DEVFN(0, 0), "gt64120_pci");
- return phb->bus;
}
static void gt64120_pci_realize(PCIDevice *d, Error **errp)
diff --git a/hw/mips/malta.c b/hw/mips/malta.c
index 13254dbc89..55037eb90f 100644
--- a/hw/mips/malta.c
+++ b/hw/mips/malta.c
@@ -1390,7 +1390,8 @@ void mips_malta_init(MachineState *machine)
stl_p(memory_region_get_ram_ptr(bios_copy) + 0x10, 0x00000420);
/* Northbridge */
- pci_bus = gt64120_register();
+ dev = sysbus_create_simple("gt64120", -1, NULL);
+ pci_bus = PCI_BUS(qdev_get_child_bus(dev, "pci"));
/*
* The whole address space decoded by the GT-64120A doesn't generate
* exception when accessing invalid memory. Create an empty slot to
diff --git a/include/hw/mips/mips.h b/include/hw/mips/mips.h
index ff88942e63..101799f7d3 100644
--- a/include/hw/mips/mips.h
+++ b/include/hw/mips/mips.h
@@ -9,9 +9,6 @@
#include "exec/memory.h"
-/* gt64xxx.c */
-PCIBus *gt64120_register(void);
-
/* bonito.c */
PCIBus *bonito_init(qemu_irq *pic);
--
2.34.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PULL 10/16] hw/rtc/mc146818rtc: QOM'ify IRQ number
2022-03-07 10:11 [PULL 00/16] MIPS patches for 2022-03-07 Philippe Mathieu-Daudé
` (8 preceding siblings ...)
2022-03-07 10:12 ` [PULL 09/16] hw/mips/gt64xxx_pci: Resolve gt64120_register() Philippe Mathieu-Daudé
@ 2022-03-07 10:12 ` Philippe Mathieu-Daudé
2022-03-07 10:12 ` [PULL 11/16] hw/rtc/m48t59-isa: " Philippe Mathieu-Daudé
` (6 subsequent siblings)
16 siblings, 0 replies; 20+ messages in thread
From: Philippe Mathieu-Daudé @ 2022-03-07 10:12 UTC (permalink / raw)
To: qemu-devel
Cc: Aleksandar Rikalo, Bernhard Beschow, Philippe Mathieu-Daudé
From: Bernhard Beschow <shentey@gmail.com>
Exposing the IRQ number as a QOM property not only allows it to be
configurable but also to be displayed in HMP:
Before:
(qemu) info qtree
...
dev: mc146818rtc, id ""
gpio-out "" 1
base_year = 0 (0x0)
lost_tick_policy = "discard"
After:
dev: mc146818rtc, id ""
gpio-out "" 1
base_year = 0 (0x0)
irq = 8 (0x8)
lost_tick_policy = "discard"
The reason the IRQ number didn's show up before is that this device does not
call isa_init_irq().
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20220301220037.76555-2-shentey@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
hw/isa/piix4.c | 2 +-
hw/rtc/mc146818rtc.c | 13 +++++++++++--
include/hw/rtc/mc146818rtc.h | 1 +
3 files changed, 13 insertions(+), 3 deletions(-)
diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
index f876c71750..fc3c8b3fd1 100644
--- a/hw/isa/piix4.c
+++ b/hw/isa/piix4.c
@@ -216,7 +216,7 @@ static void piix4_realize(PCIDevice *dev, Error **errp)
if (!qdev_realize(DEVICE(&s->rtc), BUS(isa_bus), errp)) {
return;
}
- isa_init_irq(ISA_DEVICE(&s->rtc), &s->rtc.irq, RTC_ISA_IRQ);
+ isa_init_irq(ISA_DEVICE(&s->rtc), &s->rtc.irq, s->rtc.isairq);
}
static void piix4_init(Object *obj)
diff --git a/hw/rtc/mc146818rtc.c b/hw/rtc/mc146818rtc.c
index ac9a60c90e..f235c2ddbe 100644
--- a/hw/rtc/mc146818rtc.c
+++ b/hw/rtc/mc146818rtc.c
@@ -912,6 +912,11 @@ static void rtc_realizefn(DeviceState *dev, Error **errp)
s->base_year = 0;
}
+ if (s->isairq >= ISA_NUM_IRQS) {
+ error_setg(errp, "Maximum value for \"irq\" is: %u", ISA_NUM_IRQS - 1);
+ return;
+ }
+
rtc_set_date_from_host(isadev);
switch (s->lost_tick_policy) {
@@ -957,15 +962,17 @@ ISADevice *mc146818_rtc_init(ISABus *bus, int base_year, qemu_irq intercept_irq)
{
DeviceState *dev;
ISADevice *isadev;
+ RTCState *s;
isadev = isa_new(TYPE_MC146818_RTC);
dev = DEVICE(isadev);
+ s = MC146818_RTC(isadev);
qdev_prop_set_int32(dev, "base_year", base_year);
isa_realize_and_unref(isadev, bus, &error_fatal);
if (intercept_irq) {
qdev_connect_gpio_out(dev, 0, intercept_irq);
} else {
- isa_connect_gpio_out(isadev, 0, RTC_ISA_IRQ);
+ isa_connect_gpio_out(isadev, 0, s->isairq);
}
object_property_add_alias(qdev_get_machine(), "rtc-time", OBJECT(isadev),
@@ -976,6 +983,7 @@ ISADevice *mc146818_rtc_init(ISABus *bus, int base_year, qemu_irq intercept_irq)
static Property mc146818rtc_properties[] = {
DEFINE_PROP_INT32("base_year", RTCState, base_year, 1980),
+ DEFINE_PROP_UINT8("irq", RTCState, isairq, RTC_ISA_IRQ),
DEFINE_PROP_LOSTTICKPOLICY("lost_tick_policy", RTCState,
lost_tick_policy, LOST_TICK_POLICY_DISCARD),
DEFINE_PROP_END_OF_LIST(),
@@ -1011,6 +1019,7 @@ static void rtc_reset_hold(Object *obj)
static void rtc_build_aml(ISADevice *isadev, Aml *scope)
{
+ RTCState *s = MC146818_RTC(isadev);
Aml *dev;
Aml *crs;
@@ -1021,7 +1030,7 @@ static void rtc_build_aml(ISADevice *isadev, Aml *scope)
crs = aml_resource_template();
aml_append(crs, aml_io(AML_DECODE16, RTC_ISA_BASE, RTC_ISA_BASE,
0x01, 0x08));
- aml_append(crs, aml_irq_no_flags(RTC_ISA_IRQ));
+ aml_append(crs, aml_irq_no_flags(s->isairq));
dev = aml_device("RTC");
aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0B00")));
diff --git a/include/hw/rtc/mc146818rtc.h b/include/hw/rtc/mc146818rtc.h
index 5b45b22924..deef93f89a 100644
--- a/include/hw/rtc/mc146818rtc.h
+++ b/include/hw/rtc/mc146818rtc.h
@@ -25,6 +25,7 @@ struct RTCState {
MemoryRegion coalesced_io;
uint8_t cmos_data[128];
uint8_t cmos_index;
+ uint8_t isairq;
int32_t base_year;
uint64_t base_rtc;
uint64_t last_update;
--
2.34.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PULL 11/16] hw/rtc/m48t59-isa: QOM'ify IRQ number
2022-03-07 10:11 [PULL 00/16] MIPS patches for 2022-03-07 Philippe Mathieu-Daudé
` (9 preceding siblings ...)
2022-03-07 10:12 ` [PULL 10/16] hw/rtc/mc146818rtc: QOM'ify IRQ number Philippe Mathieu-Daudé
@ 2022-03-07 10:12 ` Philippe Mathieu-Daudé
2022-03-07 10:12 ` [PULL 12/16] hw/input/pckbd: QOM'ify IRQ numbers Philippe Mathieu-Daudé
` (5 subsequent siblings)
16 siblings, 0 replies; 20+ messages in thread
From: Philippe Mathieu-Daudé @ 2022-03-07 10:12 UTC (permalink / raw)
To: qemu-devel
Cc: Aleksandar Rikalo, Bernhard Beschow, Philippe Mathieu-Daudé
From: Bernhard Beschow <shentey@gmail.com>
Exposing the IRQ number as a QOM property not only allows it to be
configurable but also to be printed by standard QOM mechanisms. This allows
isabus_dev_print() to be retired eventually.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20220301220037.76555-3-shentey@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
hw/rtc/m48t59-isa.c | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/hw/rtc/m48t59-isa.c b/hw/rtc/m48t59-isa.c
index dc21fb10a5..e9086eada4 100644
--- a/hw/rtc/m48t59-isa.c
+++ b/hw/rtc/m48t59-isa.c
@@ -42,6 +42,7 @@ struct M48txxISAState {
ISADevice parent_obj;
M48t59State state;
uint32_t io_base;
+ uint8_t isairq;
MemoryRegion io;
};
@@ -79,6 +80,7 @@ static void m48txx_isa_toggle_lock(Nvram *obj, int lock)
static Property m48t59_isa_properties[] = {
DEFINE_PROP_INT32("base-year", M48txxISAState, state.base_year, 0),
DEFINE_PROP_UINT32("iobase", M48txxISAState, io_base, 0x74),
+ DEFINE_PROP_UINT8("irq", M48txxISAState, isairq, 8),
DEFINE_PROP_END_OF_LIST(),
};
@@ -97,9 +99,14 @@ static void m48t59_isa_realize(DeviceState *dev, Error **errp)
M48txxISAState *d = M48TXX_ISA(dev);
M48t59State *s = &d->state;
+ if (d->isairq >= ISA_NUM_IRQS) {
+ error_setg(errp, "Maximum value for \"irq\" is: %u", ISA_NUM_IRQS - 1);
+ return;
+ }
+
s->model = u->info.model;
s->size = u->info.size;
- isa_init_irq(isadev, &s->IRQ, 8);
+ isa_init_irq(isadev, &s->IRQ, d->isairq);
m48t59_realize_common(s, errp);
memory_region_init_io(&d->io, OBJECT(dev), &m48t59_io_ops, s, "m48t59", 4);
if (d->io_base != 0) {
--
2.34.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PULL 12/16] hw/input/pckbd: QOM'ify IRQ numbers
2022-03-07 10:11 [PULL 00/16] MIPS patches for 2022-03-07 Philippe Mathieu-Daudé
` (10 preceding siblings ...)
2022-03-07 10:12 ` [PULL 11/16] hw/rtc/m48t59-isa: " Philippe Mathieu-Daudé
@ 2022-03-07 10:12 ` Philippe Mathieu-Daudé
2022-03-07 10:12 ` [PULL 13/16] hw/isa/isa-bus: Remove isabus_dev_print() Philippe Mathieu-Daudé
` (4 subsequent siblings)
16 siblings, 0 replies; 20+ messages in thread
From: Philippe Mathieu-Daudé @ 2022-03-07 10:12 UTC (permalink / raw)
To: qemu-devel
Cc: Aleksandar Rikalo, Bernhard Beschow, Philippe Mathieu-Daudé
From: Bernhard Beschow <shentey@gmail.com>
Exposing the IRQ numbers as QOM properties not only allows them to be
configurable but also to be printed by standard QOM mechanisms. This
allows isabus_dev_print() to be retired eventually.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20220301220037.76555-4-shentey@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
hw/input/pckbd.c | 26 ++++++++++++++++++++++----
1 file changed, 22 insertions(+), 4 deletions(-)
diff --git a/hw/input/pckbd.c b/hw/input/pckbd.c
index baba62f357..eb77e12f6f 100644
--- a/hw/input/pckbd.c
+++ b/hw/input/pckbd.c
@@ -26,6 +26,7 @@
#include "qemu/error-report.h"
#include "qemu/log.h"
#include "qemu/timer.h"
+#include "qapi/error.h"
#include "hw/isa/isa.h"
#include "migration/vmstate.h"
#include "hw/acpi/aml-build.h"
@@ -671,6 +672,8 @@ struct ISAKBDState {
KBDState kbd;
bool kbd_throttle;
MemoryRegion io[2];
+ uint8_t kbd_irq;
+ uint8_t mouse_irq;
};
void i8042_isa_mouse_fake_event(ISAKBDState *isa)
@@ -734,8 +737,20 @@ static void i8042_realizefn(DeviceState *dev, Error **errp)
ISAKBDState *isa_s = I8042(dev);
KBDState *s = &isa_s->kbd;
- isa_init_irq(isadev, &s->irq_kbd, 1);
- isa_init_irq(isadev, &s->irq_mouse, 12);
+ if (isa_s->kbd_irq >= ISA_NUM_IRQS) {
+ error_setg(errp, "Maximum value for \"kbd-irq\" is: %u",
+ ISA_NUM_IRQS - 1);
+ return;
+ }
+
+ if (isa_s->mouse_irq >= ISA_NUM_IRQS) {
+ error_setg(errp, "Maximum value for \"mouse-irq\" is: %u",
+ ISA_NUM_IRQS - 1);
+ return;
+ }
+
+ isa_init_irq(isadev, &s->irq_kbd, isa_s->kbd_irq);
+ isa_init_irq(isadev, &s->irq_mouse, isa_s->mouse_irq);
isa_register_ioport(isadev, isa_s->io + 0, 0x60);
isa_register_ioport(isadev, isa_s->io + 1, 0x64);
@@ -754,6 +769,7 @@ static void i8042_realizefn(DeviceState *dev, Error **errp)
static void i8042_build_aml(ISADevice *isadev, Aml *scope)
{
+ ISAKBDState *isa_s = I8042(isadev);
Aml *kbd;
Aml *mou;
Aml *crs;
@@ -761,7 +777,7 @@ static void i8042_build_aml(ISADevice *isadev, Aml *scope)
crs = aml_resource_template();
aml_append(crs, aml_io(AML_DECODE16, 0x0060, 0x0060, 0x01, 0x01));
aml_append(crs, aml_io(AML_DECODE16, 0x0064, 0x0064, 0x01, 0x01));
- aml_append(crs, aml_irq_no_flags(1));
+ aml_append(crs, aml_irq_no_flags(isa_s->kbd_irq));
kbd = aml_device("KBD");
aml_append(kbd, aml_name_decl("_HID", aml_eisaid("PNP0303")));
@@ -769,7 +785,7 @@ static void i8042_build_aml(ISADevice *isadev, Aml *scope)
aml_append(kbd, aml_name_decl("_CRS", crs));
crs = aml_resource_template();
- aml_append(crs, aml_irq_no_flags(12));
+ aml_append(crs, aml_irq_no_flags(isa_s->mouse_irq));
mou = aml_device("MOU");
aml_append(mou, aml_name_decl("_HID", aml_eisaid("PNP0F13")));
@@ -783,6 +799,8 @@ static void i8042_build_aml(ISADevice *isadev, Aml *scope)
static Property i8042_properties[] = {
DEFINE_PROP_BOOL("extended-state", ISAKBDState, kbd.extended_state, true),
DEFINE_PROP_BOOL("kbd-throttle", ISAKBDState, kbd_throttle, false),
+ DEFINE_PROP_UINT8("kbd-irq", ISAKBDState, kbd_irq, 1),
+ DEFINE_PROP_UINT8("mouse-irq", ISAKBDState, mouse_irq, 12),
DEFINE_PROP_END_OF_LIST(),
};
--
2.34.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PULL 13/16] hw/isa/isa-bus: Remove isabus_dev_print()
2022-03-07 10:11 [PULL 00/16] MIPS patches for 2022-03-07 Philippe Mathieu-Daudé
` (11 preceding siblings ...)
2022-03-07 10:12 ` [PULL 12/16] hw/input/pckbd: QOM'ify IRQ numbers Philippe Mathieu-Daudé
@ 2022-03-07 10:12 ` Philippe Mathieu-Daudé
2022-03-07 10:12 ` [PULL 14/16] isa: Drop unused attributes from ISADevice Philippe Mathieu-Daudé
` (3 subsequent siblings)
16 siblings, 0 replies; 20+ messages in thread
From: Philippe Mathieu-Daudé @ 2022-03-07 10:12 UTC (permalink / raw)
To: qemu-devel
Cc: Aleksandar Rikalo, Bernhard Beschow, Philippe Mathieu-Daudé
From: Bernhard Beschow <shentey@gmail.com>
All isabus_dev_print() did was to print up to two IRQ numbers per
device. This is redundant if the IRQ numbers are present as QOM
properties (see e.g. the modified tests/qemu-iotests/172.out).
Now that the last devices relying on isabus_dev_print() had their IRQ
numbers QOM'ified, the contribution of this function ultimately became
redundant. Remove it.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20220301220037.76555-5-shentey@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
hw/isa/isa-bus.c | 16 ----------------
tests/qemu-iotests/172.out | 26 --------------------------
2 files changed, 42 deletions(-)
diff --git a/hw/isa/isa-bus.c b/hw/isa/isa-bus.c
index 6c31398dda..af5add6a26 100644
--- a/hw/isa/isa-bus.c
+++ b/hw/isa/isa-bus.c
@@ -21,21 +21,18 @@
#include "qemu/error-report.h"
#include "qemu/module.h"
#include "qapi/error.h"
-#include "monitor/monitor.h"
#include "hw/sysbus.h"
#include "sysemu/sysemu.h"
#include "hw/isa/isa.h"
static ISABus *isabus;
-static void isabus_dev_print(Monitor *mon, DeviceState *dev, int indent);
static char *isabus_get_fw_dev_path(DeviceState *dev);
static void isa_bus_class_init(ObjectClass *klass, void *data)
{
BusClass *k = BUS_CLASS(klass);
- k->print_dev = isabus_dev_print;
k->get_fw_dev_path = isabus_get_fw_dev_path;
}
@@ -222,19 +219,6 @@ void isa_build_aml(ISABus *bus, Aml *scope)
}
}
-static void isabus_dev_print(Monitor *mon, DeviceState *dev, int indent)
-{
- ISADevice *d = ISA_DEVICE(dev);
-
- if (d->isairq[1] != -1) {
- monitor_printf(mon, "%*sisa irqs %d,%d\n", indent, "",
- d->isairq[0], d->isairq[1]);
- } else if (d->isairq[0] != -1) {
- monitor_printf(mon, "%*sisa irq %d\n", indent, "",
- d->isairq[0]);
- }
-}
-
static void isabus_bridge_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
diff --git a/tests/qemu-iotests/172.out b/tests/qemu-iotests/172.out
index 4cf4d536b4..9479b92185 100644
--- a/tests/qemu-iotests/172.out
+++ b/tests/qemu-iotests/172.out
@@ -15,7 +15,6 @@ Testing:
fdtypeA = "auto"
fdtypeB = "auto"
fallback = "288"
- isa irq 6
bus: floppy-bus.0
type floppy-bus
dev: floppy, id ""
@@ -43,7 +42,6 @@ Testing: -fda TEST_DIR/t.qcow2
fdtypeA = "auto"
fdtypeB = "auto"
fallback = "288"
- isa irq 6
bus: floppy-bus.0
type floppy-bus
dev: floppy, id ""
@@ -81,7 +79,6 @@ Testing: -fdb TEST_DIR/t.qcow2
fdtypeA = "auto"
fdtypeB = "auto"
fallback = "288"
- isa irq 6
bus: floppy-bus.0
type floppy-bus
dev: floppy, id ""
@@ -135,7 +132,6 @@ Testing: -fda TEST_DIR/t.qcow2 -fdb TEST_DIR/t.qcow2.2
fdtypeA = "auto"
fdtypeB = "auto"
fallback = "288"
- isa irq 6
bus: floppy-bus.0
type floppy-bus
dev: floppy, id ""
@@ -190,7 +186,6 @@ Testing: -fdb
fdtypeA = "auto"
fdtypeB = "auto"
fallback = "288"
- isa irq 6
bus: floppy-bus.0
type floppy-bus
dev: floppy, id ""
@@ -230,7 +225,6 @@ Testing: -drive if=floppy,file=TEST_DIR/t.qcow2
fdtypeA = "auto"
fdtypeB = "auto"
fallback = "288"
- isa irq 6
bus: floppy-bus.0
type floppy-bus
dev: floppy, id ""
@@ -268,7 +262,6 @@ Testing: -drive if=floppy,file=TEST_DIR/t.qcow2,index=1
fdtypeA = "auto"
fdtypeB = "auto"
fallback = "288"
- isa irq 6
bus: floppy-bus.0
type floppy-bus
dev: floppy, id ""
@@ -322,7 +315,6 @@ Testing: -drive if=floppy,file=TEST_DIR/t.qcow2 -drive if=floppy,file=TEST_DIR/t
fdtypeA = "auto"
fdtypeB = "auto"
fallback = "288"
- isa irq 6
bus: floppy-bus.0
type floppy-bus
dev: floppy, id ""
@@ -380,7 +372,6 @@ Testing: -drive if=none,file=TEST_DIR/t.qcow2 -device floppy,drive=none0
fdtypeA = "auto"
fdtypeB = "auto"
fallback = "288"
- isa irq 6
bus: floppy-bus.0
type floppy-bus
dev: floppy, id ""
@@ -418,7 +409,6 @@ Testing: -drive if=none,file=TEST_DIR/t.qcow2 -device floppy,drive=none0,unit=1
fdtypeA = "auto"
fdtypeB = "auto"
fallback = "288"
- isa irq 6
bus: floppy-bus.0
type floppy-bus
dev: floppy, id ""
@@ -456,7 +446,6 @@ Testing: -drive if=none,file=TEST_DIR/t.qcow2 -drive if=none,file=TEST_DIR/t.qco
fdtypeA = "auto"
fdtypeB = "auto"
fallback = "288"
- isa irq 6
bus: floppy-bus.0
type floppy-bus
dev: floppy, id ""
@@ -520,7 +509,6 @@ Testing: -fda TEST_DIR/t.qcow2 -drive if=none,file=TEST_DIR/t.qcow2.2 -device fl
fdtypeA = "auto"
fdtypeB = "auto"
fallback = "288"
- isa irq 6
bus: floppy-bus.0
type floppy-bus
dev: floppy, id ""
@@ -575,7 +563,6 @@ Testing: -fda TEST_DIR/t.qcow2 -drive if=none,file=TEST_DIR/t.qcow2.2 -device fl
fdtypeA = "auto"
fdtypeB = "auto"
fallback = "288"
- isa irq 6
bus: floppy-bus.0
type floppy-bus
dev: floppy, id ""
@@ -630,7 +617,6 @@ Testing: -fdb TEST_DIR/t.qcow2 -drive if=none,file=TEST_DIR/t.qcow2.2 -device fl
fdtypeA = "auto"
fdtypeB = "auto"
fallback = "288"
- isa irq 6
bus: floppy-bus.0
type floppy-bus
dev: floppy, id ""
@@ -685,7 +671,6 @@ Testing: -fdb TEST_DIR/t.qcow2 -drive if=none,file=TEST_DIR/t.qcow2.2 -device fl
fdtypeA = "auto"
fdtypeB = "auto"
fallback = "288"
- isa irq 6
bus: floppy-bus.0
type floppy-bus
dev: floppy, id ""
@@ -749,7 +734,6 @@ Testing: -drive if=floppy,file=TEST_DIR/t.qcow2 -drive if=none,file=TEST_DIR/t.q
fdtypeA = "auto"
fdtypeB = "auto"
fallback = "288"
- isa irq 6
bus: floppy-bus.0
type floppy-bus
dev: floppy, id ""
@@ -804,7 +788,6 @@ Testing: -drive if=floppy,file=TEST_DIR/t.qcow2 -drive if=none,file=TEST_DIR/t.q
fdtypeA = "auto"
fdtypeB = "auto"
fallback = "288"
- isa irq 6
bus: floppy-bus.0
type floppy-bus
dev: floppy, id ""
@@ -865,7 +848,6 @@ Testing: -drive if=none,file=TEST_DIR/t.qcow2 -global floppy.drive=none0 -device
fdtypeA = "auto"
fdtypeB = "auto"
fallback = "288"
- isa irq 6
bus: floppy-bus.0
type floppy-bus
dev: floppy, id ""
@@ -933,7 +915,6 @@ Testing: -device floppy
fdtypeA = "auto"
fdtypeB = "auto"
fallback = "288"
- isa irq 6
bus: floppy-bus.0
type floppy-bus
dev: floppy, id ""
@@ -958,7 +939,6 @@ Testing: -device floppy,drive-type=120
fdtypeA = "auto"
fdtypeB = "auto"
fallback = "288"
- isa irq 6
bus: floppy-bus.0
type floppy-bus
dev: floppy, id ""
@@ -983,7 +963,6 @@ Testing: -device floppy,drive-type=144
fdtypeA = "auto"
fdtypeB = "auto"
fallback = "288"
- isa irq 6
bus: floppy-bus.0
type floppy-bus
dev: floppy, id ""
@@ -1008,7 +987,6 @@ Testing: -device floppy,drive-type=288
fdtypeA = "auto"
fdtypeB = "auto"
fallback = "288"
- isa irq 6
bus: floppy-bus.0
type floppy-bus
dev: floppy, id ""
@@ -1036,7 +1014,6 @@ Testing: -drive if=none,file=TEST_DIR/t.qcow2 -device floppy,drive=none0,drive-t
fdtypeA = "auto"
fdtypeB = "auto"
fallback = "288"
- isa irq 6
bus: floppy-bus.0
type floppy-bus
dev: floppy, id ""
@@ -1074,7 +1051,6 @@ Testing: -drive if=none,file=TEST_DIR/t.qcow2 -device floppy,drive=none0,drive-t
fdtypeA = "auto"
fdtypeB = "auto"
fallback = "288"
- isa irq 6
bus: floppy-bus.0
type floppy-bus
dev: floppy, id ""
@@ -1115,7 +1091,6 @@ Testing: -drive if=none,file=TEST_DIR/t.qcow2 -device floppy,drive=none0,logical
fdtypeA = "auto"
fdtypeB = "auto"
fallback = "288"
- isa irq 6
bus: floppy-bus.0
type floppy-bus
dev: floppy, id ""
@@ -1153,7 +1128,6 @@ Testing: -drive if=none,file=TEST_DIR/t.qcow2 -device floppy,drive=none0,physica
fdtypeA = "auto"
fdtypeB = "auto"
fallback = "288"
- isa irq 6
bus: floppy-bus.0
type floppy-bus
dev: floppy, id ""
--
2.34.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PULL 14/16] isa: Drop unused attributes from ISADevice
2022-03-07 10:11 [PULL 00/16] MIPS patches for 2022-03-07 Philippe Mathieu-Daudé
` (12 preceding siblings ...)
2022-03-07 10:12 ` [PULL 13/16] hw/isa/isa-bus: Remove isabus_dev_print() Philippe Mathieu-Daudé
@ 2022-03-07 10:12 ` Philippe Mathieu-Daudé
2022-03-07 10:12 ` [PULL 15/16] isa: Inline and remove one-line isa_init_irq() Philippe Mathieu-Daudé
` (2 subsequent siblings)
16 siblings, 0 replies; 20+ messages in thread
From: Philippe Mathieu-Daudé @ 2022-03-07 10:12 UTC (permalink / raw)
To: qemu-devel
Cc: Aleksandar Rikalo, Bernhard Beschow, Philippe Mathieu-Daudé
From: Bernhard Beschow <shentey@gmail.com>
Now that the last users of ISADevice::isairq[] have been resolved during the
previous commits, it can be removed for good.
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20220301220037.76555-7-shentey@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
hw/isa/isa-bus.c | 13 -------------
include/hw/isa/isa.h | 2 --
2 files changed, 15 deletions(-)
diff --git a/hw/isa/isa-bus.c b/hw/isa/isa-bus.c
index af5add6a26..c64a14120b 100644
--- a/hw/isa/isa-bus.c
+++ b/hw/isa/isa-bus.c
@@ -87,11 +87,7 @@ qemu_irq isa_get_irq(ISADevice *dev, unsigned isairq)
void isa_init_irq(ISADevice *dev, qemu_irq *p, unsigned isairq)
{
- assert(dev->nirqs < ARRAY_SIZE(dev->isairq));
- assert(isairq < ISA_NUM_IRQS);
- dev->isairq[dev->nirqs] = isairq;
*p = isa_get_irq(dev, isairq);
- dev->nirqs++;
}
void isa_connect_gpio_out(ISADevice *isadev, int gpioirq, unsigned isairq)
@@ -150,14 +146,6 @@ int isa_register_portio_list(ISADevice *dev,
return 0;
}
-static void isa_device_init(Object *obj)
-{
- ISADevice *dev = ISA_DEVICE(obj);
-
- dev->isairq[0] = -1;
- dev->isairq[1] = -1;
-}
-
ISADevice *isa_new(const char *name)
{
return ISA_DEVICE(qdev_new(name));
@@ -244,7 +232,6 @@ static const TypeInfo isa_device_type_info = {
.name = TYPE_ISA_DEVICE,
.parent = TYPE_DEVICE,
.instance_size = sizeof(ISADevice),
- .instance_init = isa_device_init,
.abstract = true,
.class_size = sizeof(ISADeviceClass),
.class_init = isa_device_class_init,
diff --git a/include/hw/isa/isa.h b/include/hw/isa/isa.h
index d4417b34b6..d80cab5b79 100644
--- a/include/hw/isa/isa.h
+++ b/include/hw/isa/isa.h
@@ -83,8 +83,6 @@ struct ISADevice {
DeviceState parent_obj;
/*< public >*/
- int8_t isairq[2]; /* -1 = unassigned */
- int nirqs;
int ioport_id;
};
--
2.34.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PULL 15/16] isa: Inline and remove one-line isa_init_irq()
2022-03-07 10:11 [PULL 00/16] MIPS patches for 2022-03-07 Philippe Mathieu-Daudé
` (13 preceding siblings ...)
2022-03-07 10:12 ` [PULL 14/16] isa: Drop unused attributes from ISADevice Philippe Mathieu-Daudé
@ 2022-03-07 10:12 ` Philippe Mathieu-Daudé
2022-03-07 11:29 ` Bernhard Beschow
2022-03-07 10:12 ` [PULL 16/16] tests/avocado/linux_ssh_mips_malta.py: add missing accel (tcg) tag Philippe Mathieu-Daudé
2022-03-07 11:42 ` [PULL 00/16] MIPS patches for 2022-03-07 Philippe Mathieu-Daudé
16 siblings, 1 reply; 20+ messages in thread
From: Philippe Mathieu-Daudé @ 2022-03-07 10:12 UTC (permalink / raw)
To: qemu-devel
Cc: Corey Minyard, Aleksandar Rikalo, Philippe Mathieu-Daudé,
Gerd Hoffmann, Bernhard Beschow, Stefan Berger
From: Bernhard Beschow <shentey@gmail.com>
isa_init_irq() has become a trivial one-line wrapper for isa_get_irq().
It can therefore be removed.
isa_ipmi_kcs)
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Stefan Berger <stefanb@linux.ibm.com> (tpm_tis_isa)
Acked-by: Corey Minyard <cminyard@mvista.com> (isa_ipmi_bt,
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Acked-by: Gerd Hoffmann <kraxel@redhat.com>
Message-Id: <20220301220037.76555-8-shentey@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
hw/isa/piix4.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
index fc3c8b3fd1..8607e0ac36 100644
--- a/hw/isa/piix4.c
+++ b/hw/isa/piix4.c
@@ -216,7 +216,7 @@ static void piix4_realize(PCIDevice *dev, Error **errp)
if (!qdev_realize(DEVICE(&s->rtc), BUS(isa_bus), errp)) {
return;
}
- isa_init_irq(ISA_DEVICE(&s->rtc), &s->rtc.irq, s->rtc.isairq);
+ s->rtc.irq = isa_get_irq(ISA_DEVICE(&s->rtc), s->rtc.isairq);
}
static void piix4_init(Object *obj)
--
2.34.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* Re: [PULL 15/16] isa: Inline and remove one-line isa_init_irq()
2022-03-07 10:12 ` [PULL 15/16] isa: Inline and remove one-line isa_init_irq() Philippe Mathieu-Daudé
@ 2022-03-07 11:29 ` Bernhard Beschow
2022-03-07 13:39 ` Philippe Mathieu-Daudé
0 siblings, 1 reply; 20+ messages in thread
From: Bernhard Beschow @ 2022-03-07 11:29 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Corey Minyard, Aleksandar Rikalo, Philippe Mathieu-Daudé,
Gerd Hoffmann, Stefan Berger
Am 7. März 2022 10:12:06 UTC schrieb "Philippe Mathieu-Daudé" <philippe.mathieu.daude@gmail.com>:
>From: Bernhard Beschow <shentey@gmail.com>
>
>isa_init_irq() has become a trivial one-line wrapper for isa_get_irq().
>It can therefore be removed.
>
>isa_ipmi_kcs)
>
>Signed-off-by: Bernhard Beschow <shentey@gmail.com>
>Reviewed-by: Stefan Berger <stefanb@linux.ibm.com> (tpm_tis_isa)
>Acked-by: Corey Minyard <cminyard@mvista.com> (isa_ipmi_bt,
>Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
>Acked-by: Gerd Hoffmann <kraxel@redhat.com>
>Message-Id: <20220301220037.76555-8-shentey@gmail.com>
>Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
>---
> hw/isa/piix4.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
>diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
>index fc3c8b3fd1..8607e0ac36 100644
>--- a/hw/isa/piix4.c
>+++ b/hw/isa/piix4.c
>@@ -216,7 +216,7 @@ static void piix4_realize(PCIDevice *dev, Error **errp)
> if (!qdev_realize(DEVICE(&s->rtc), BUS(isa_bus), errp)) {
> return;
> }
>- isa_init_irq(ISA_DEVICE(&s->rtc), &s->rtc.irq, s->rtc.isairq);
>+ s->rtc.irq = isa_get_irq(ISA_DEVICE(&s->rtc), s->rtc.isairq);
> }
>
> static void piix4_init(Object *obj)
Hey Phil,
it looks like the majority of the patch is missing (only the resolved merge conflict is there). I can send this patch series rebased onto my Malta one which I could do later this day.
Best regards,
Bernhard
P.S. Unfortunately I can only do this work in my free time. Thus it can sometimes take a while until I respond.
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PULL 15/16] isa: Inline and remove one-line isa_init_irq()
2022-03-07 11:29 ` Bernhard Beschow
@ 2022-03-07 13:39 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 20+ messages in thread
From: Philippe Mathieu-Daudé @ 2022-03-07 13:39 UTC (permalink / raw)
To: Bernhard Beschow, qemu-devel
Cc: Corey Minyard, Aleksandar Rikalo, Philippe Mathieu-Daudé,
Gerd Hoffmann, Stefan Berger
On 7/3/22 12:29, Bernhard Beschow wrote:
> Am 7. März 2022 10:12:06 UTC schrieb "Philippe Mathieu-Daudé" <philippe.mathieu.daude@gmail.com>:
>> From: Bernhard Beschow <shentey@gmail.com>
>>
>> isa_init_irq() has become a trivial one-line wrapper for isa_get_irq().
>> It can therefore be removed.
>>
>> isa_ipmi_kcs)
>>
>> Signed-off-by: Bernhard Beschow <shentey@gmail.com>
>> Reviewed-by: Stefan Berger <stefanb@linux.ibm.com> (tpm_tis_isa)
>> Acked-by: Corey Minyard <cminyard@mvista.com> (isa_ipmi_bt,
>> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
>> Acked-by: Gerd Hoffmann <kraxel@redhat.com>
>> Message-Id: <20220301220037.76555-8-shentey@gmail.com>
>> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
>> ---
>> hw/isa/piix4.c | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
>> index fc3c8b3fd1..8607e0ac36 100644
>> --- a/hw/isa/piix4.c
>> +++ b/hw/isa/piix4.c
>> @@ -216,7 +216,7 @@ static void piix4_realize(PCIDevice *dev, Error **errp)
>> if (!qdev_realize(DEVICE(&s->rtc), BUS(isa_bus), errp)) {
>> return;
>> }
>> - isa_init_irq(ISA_DEVICE(&s->rtc), &s->rtc.irq, s->rtc.isairq);
>> + s->rtc.irq = isa_get_irq(ISA_DEVICE(&s->rtc), s->rtc.isairq);
>> }
>>
>> static void piix4_init(Object *obj)
>
> Hey Phil,
>
> it looks like the majority of the patch is missing (only the resolved merge conflict is there). I can send this patch series rebased onto my Malta one which I could do later this day.
Thanks for being careful and catching this. Not sure what I screwed.
Since I have this done locally I'll repost so you can verify.
Regards,
Phil.
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PULL 16/16] tests/avocado/linux_ssh_mips_malta.py: add missing accel (tcg) tag
2022-03-07 10:11 [PULL 00/16] MIPS patches for 2022-03-07 Philippe Mathieu-Daudé
` (14 preceding siblings ...)
2022-03-07 10:12 ` [PULL 15/16] isa: Inline and remove one-line isa_init_irq() Philippe Mathieu-Daudé
@ 2022-03-07 10:12 ` Philippe Mathieu-Daudé
2022-03-07 11:42 ` [PULL 00/16] MIPS patches for 2022-03-07 Philippe Mathieu-Daudé
16 siblings, 0 replies; 20+ messages in thread
From: Philippe Mathieu-Daudé @ 2022-03-07 10:12 UTC (permalink / raw)
To: qemu-devel; +Cc: Aleksandar Rikalo, Philippe Mathieu-Daudé, Cleber Rosa
From: Cleber Rosa <crosa@redhat.com>
Being explicit about the accelerator used on these tests is a good
thing in itself, but it will also be used in the filtering rules
applied on "make check-avocado".
Signed-off-by: Cleber Rosa <crosa@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20220225210156.2032055-6-crosa@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
tests/avocado/linux_ssh_mips_malta.py | 3 +++
1 file changed, 3 insertions(+)
diff --git a/tests/avocado/linux_ssh_mips_malta.py b/tests/avocado/linux_ssh_mips_malta.py
index c0f0be5ade..0179d8a6ca 100644
--- a/tests/avocado/linux_ssh_mips_malta.py
+++ b/tests/avocado/linux_ssh_mips_malta.py
@@ -23,6 +23,9 @@
@skipUnless(os.getenv('AVOCADO_TIMEOUT_EXPECTED'), 'Test might timeout')
@skipUnless(ssh.SSH_CLIENT_BINARY, 'No SSH client available')
class LinuxSSH(QemuSystemTest, LinuxSSHMixIn):
+ """
+ :avocado: tags=accel:tcg
+ """
timeout = 150 # Not for 'configure --enable-debug --enable-debug-tcg'
--
2.34.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* Re: [PULL 00/16] MIPS patches for 2022-03-07
2022-03-07 10:11 [PULL 00/16] MIPS patches for 2022-03-07 Philippe Mathieu-Daudé
` (15 preceding siblings ...)
2022-03-07 10:12 ` [PULL 16/16] tests/avocado/linux_ssh_mips_malta.py: add missing accel (tcg) tag Philippe Mathieu-Daudé
@ 2022-03-07 11:42 ` Philippe Mathieu-Daudé
16 siblings, 0 replies; 20+ messages in thread
From: Philippe Mathieu-Daudé @ 2022-03-07 11:42 UTC (permalink / raw)
To: qemu-devel, Peter Maydell; +Cc: Aleksandar Rikalo, Philippe Mathieu-Daudé
On 7/3/22 11:11, Philippe Mathieu-Daudé wrote:
> From: Philippe Mathieu-Daudé <f4bug@amsat.org>
>
> The following changes since commit 9d662a6b22a0838a85c5432385f35db2488a33a5:
>
> Merge remote-tracking branch 'remotes/legoater/tags/pull-ppc-20220305' into staging (2022-03-05 18:03:15 +0000)
>
> are available in the Git repository at:
>
> https://github.com/philmd/qemu.git tags/mips-20220307
>
> for you to fetch changes up to 9be5a9f464c1fc106a4aaf941f7792404c43556d:
>
> tests/avocado/linux_ssh_mips_malta.py: add missing accel (tcg) tag (2022-03-07 01:35:07 +0100)
>
> ----------------------------------------------------------------
> MIPS patches queue
>
> - Fix CP0 cycle counter timing
> - Fix VMState of gt64120 IRQs
> - Long due PIIX4 QOM cleanups
> - ISA IRQ QOM'ification / cleanups
>
> ----------------------------------------------------------------
Please ignore this PR, I'll send a v2.
^ permalink raw reply [flat|nested] 20+ messages in thread