From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, Thomas Huth <thuth@redhat.com>
Subject: [PULL 2/4] tcg/s390x: Fix INDEX_op_bitsel_vec vs VSEL
Date: Mon, 14 Mar 2022 10:36:05 -0700 [thread overview]
Message-ID: <20220314173607.145630-3-richard.henderson@linaro.org> (raw)
In-Reply-To: <20220314173607.145630-1-richard.henderson@linaro.org>
The operands are output in the wrong order: the tcg selector
argument is first, whereas the s390x selector argument is last.
Tested-by: Thomas Huth <thuth@redhat.com>
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/898
Fixes: 9bca986df88 ("tcg/s390x: Implement TCG_TARGET_HAS_bitsel_vec")
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/s390x/tcg-target.c.inc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc
index 508f1bccc7..3b185b3c96 100644
--- a/tcg/s390x/tcg-target.c.inc
+++ b/tcg/s390x/tcg-target.c.inc
@@ -2868,7 +2868,7 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
break;
case INDEX_op_bitsel_vec:
- tcg_out_insn(s, VRRe, VSEL, a0, a1, a2, args[3]);
+ tcg_out_insn(s, VRRe, VSEL, a0, a2, args[3], a1);
break;
case INDEX_op_cmp_vec:
--
2.25.1
next prev parent reply other threads:[~2022-03-14 17:56 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-03-14 17:36 [PULL 0/4] tcg patch queue Richard Henderson
2022-03-14 17:36 ` [PULL 1/4] tcg/s390x: Fix tcg_out_dupi_vec vs VGM Richard Henderson
2022-03-14 17:36 ` Richard Henderson [this message]
2022-03-14 17:36 ` [PULL 3/4] tcg/s390x: Fix tcg_out_dup_vec vs general registers Richard Henderson
2022-03-14 17:36 ` [PULL 4/4] tcg/arm: Don't emit UNPREDICTABLE LDRD with Rm == Rt or Rt+1 Richard Henderson
2022-03-15 9:53 ` [PULL 0/4] tcg patch queue Peter Maydell
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