From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org
Subject: [PULL 3/4] tcg/s390x: Fix tcg_out_dup_vec vs general registers
Date: Mon, 14 Mar 2022 10:36:06 -0700 [thread overview]
Message-ID: <20220314173607.145630-4-richard.henderson@linaro.org> (raw)
In-Reply-To: <20220314173607.145630-1-richard.henderson@linaro.org>
We copied the data from the general register input to the
vector register output, but have not yet replicated it.
We intended to fall through into the vector-vector case,
but failed to redirect the input register.
This is caught by an assertion failure in tcg_out_insn_VRIc,
which diagnosed the incorrect register class.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/s390x/tcg-target.c.inc | 1 +
1 file changed, 1 insertion(+)
diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc
index 3b185b3c96..33becd7694 100644
--- a/tcg/s390x/tcg-target.c.inc
+++ b/tcg/s390x/tcg-target.c.inc
@@ -2675,6 +2675,7 @@ static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece,
if (vece == MO_64) {
return true;
}
+ src = dst;
}
/*
--
2.25.1
next prev parent reply other threads:[~2022-03-14 17:43 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-03-14 17:36 [PULL 0/4] tcg patch queue Richard Henderson
2022-03-14 17:36 ` [PULL 1/4] tcg/s390x: Fix tcg_out_dupi_vec vs VGM Richard Henderson
2022-03-14 17:36 ` [PULL 2/4] tcg/s390x: Fix INDEX_op_bitsel_vec vs VSEL Richard Henderson
2022-03-14 17:36 ` Richard Henderson [this message]
2022-03-14 17:36 ` [PULL 4/4] tcg/arm: Don't emit UNPREDICTABLE LDRD with Rm == Rt or Rt+1 Richard Henderson
2022-03-15 9:53 ` [PULL 0/4] tcg patch queue Peter Maydell
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