From: Alistair Francis <alistair.francis@opensource.wdc.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
alistair23@gmail.com, Bin Meng <bin.meng@windriver.com>,
bmeng.cn@gmail.com, Alistair Francis <alistair.francis@wdc.com>
Subject: [PATCH 1/2] target/riscv: cpu: Fixup indentation
Date: Tue, 15 Mar 2022 16:40:06 +1000 [thread overview]
Message-ID: <20220315064007.3600746-2-alistair.francis@opensource.wdc.com> (raw)
In-Reply-To: <20220315064007.3600746-1-alistair.francis@opensource.wdc.com>
From: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index ddda4906ff..a4120c7fb4 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -709,11 +709,11 @@ static void riscv_cpu_set_irq(void *opaque, int irq, int level)
case IRQ_S_EXT:
case IRQ_VS_EXT:
case IRQ_M_EXT:
- if (kvm_enabled()) {
+ if (kvm_enabled()) {
kvm_riscv_set_irq(cpu, irq, level);
- } else {
+ } else {
riscv_cpu_update_mip(cpu, 1 << irq, BOOL_TO_MASK(level));
- }
+ }
break;
default:
g_assert_not_reached();
--
2.35.1
next prev parent reply other threads:[~2022-03-15 7:07 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-03-15 6:40 [PATCH 0/2] target/riscv: Allow software access to MIP SEIP Alistair Francis
2022-03-15 6:40 ` Alistair Francis [this message]
2022-03-15 7:29 ` [PATCH 1/2] target/riscv: cpu: Fixup indentation Bin Meng
2022-03-15 14:59 ` Weiwei Li
2022-03-15 6:40 ` [PATCH 2/2] target/riscv: Allow software access to MIP SEIP Alistair Francis
2022-03-15 8:51 ` Bin Meng
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