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envelope-from=prvs=066bbe4b2=alistair.francis@opensource.wdc.com; helo=esa6.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Alistair Francis The RISC-V specification states that: "Supervisor-level external interrupts are made pending based on the logical-OR of the software-writable SEIP bit and the signal from the external interrupt controller." We currently only allow either the interrupt controller or software to set the bit, which is incorrect. This patch removes the miclaim mask when writing MIP to allow M-mode software to inject interrupts, even with an interrupt controller. We then also need to keep track of which source is setting MIP_SEIP. The final value is a OR of both, so we add two bools and use that to keep track of the current state. This way either source can change without loosing the correct value. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/904 Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 8 ++++++++ target/riscv/cpu.c | 10 +++++++++- target/riscv/csr.c | 8 ++++++-- 3 files changed, 23 insertions(+), 3 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index c069fe85fa..05d40f8dbd 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -173,6 +173,14 @@ struct CPUArchState { uint64_t mstatus; =20 uint64_t mip; + /* + * MIP contains the software writable version of SEIP ORed with the + * external interrupt value. The MIP register is always up-to-date. + * To keep track of the current source, we also save booleans of the= values + * here. + */ + bool external_seip; + bool software_seip; =20 uint64_t miclaim; =20 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index a4120c7fb4..0bd19e16a2 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -706,7 +706,6 @@ static void riscv_cpu_set_irq(void *opaque, int irq, = int level) case IRQ_VS_TIMER: case IRQ_M_TIMER: case IRQ_U_EXT: - case IRQ_S_EXT: case IRQ_VS_EXT: case IRQ_M_EXT: if (kvm_enabled()) { @@ -715,6 +714,15 @@ static void riscv_cpu_set_irq(void *opaque, int irq,= int level) riscv_cpu_update_mip(cpu, 1 << irq, BOOL_TO_MASK(level))= ; } break; + case IRQ_S_EXT: + if (kvm_enabled()) { + kvm_riscv_set_irq(cpu, irq, level); + } else { + env->external_seip =3D level; + riscv_cpu_update_mip(cpu, 1 << irq, + BOOL_TO_MASK(level | env->software_= seip)); + } + break; default: g_assert_not_reached(); } diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 0606cd0ea8..48e78cf91e 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1403,10 +1403,14 @@ static RISCVException rmw_mip64(CPURISCVState *en= v, int csrno, uint64_t new_val, uint64_t wr_mask) { RISCVCPU *cpu =3D env_archcpu(env); - /* Allow software control of delegable interrupts not claimed by har= dware */ - uint64_t old_mip, mask =3D wr_mask & delegable_ints & ~env->miclaim; + uint64_t old_mip, mask =3D wr_mask & delegable_ints; uint32_t gin; =20 + if (mask & MIP_SEIP) { + env->software_seip =3D new_val & MIP_SEIP; + } + new_val |=3D env->external_seip << IRQ_S_EXT; + if (mask) { old_mip =3D riscv_cpu_update_mip(cpu, mask, (new_val & mask)); } else { --=20 2.35.1