From: Bin Meng <bmeng.cn@gmail.com>
To: Alistair Francis <Alistair.Francis@wdc.com>,
qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: Alistair Francis <alistair.francis@wdc.com>,
Bin Meng <bin.meng@windriver.com>,
Richard Henderson <richard.henderson@linaro.org>
Subject: [PATCH v4 7/7] hw/core: tcg-cpu-ops.h: Update comments of debug_check_watchpoint()
Date: Tue, 15 Mar 2022 14:55:29 +0800 [thread overview]
Message-ID: <20220315065529.62198-8-bmeng.cn@gmail.com> (raw)
In-Reply-To: <20220315065529.62198-1-bmeng.cn@gmail.com>
From: Bin Meng <bin.meng@windriver.com>
This is now used by RISC-V as well. Update the comments.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
(no changes since v1)
include/hw/core/tcg-cpu-ops.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h
index e13898553a..f98671ff32 100644
--- a/include/hw/core/tcg-cpu-ops.h
+++ b/include/hw/core/tcg-cpu-ops.h
@@ -90,6 +90,7 @@ struct TCGCPUOps {
/**
* @debug_check_watchpoint: return true if the architectural
* watchpoint whose address has matched should really fire, used by ARM
+ * and RISC-V
*/
bool (*debug_check_watchpoint)(CPUState *cpu, CPUWatchpoint *wp);
--
2.25.1
next prev parent reply other threads:[~2022-03-15 7:13 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-03-15 6:55 [PATCH v4 0/7] target/riscv: Initial support for the Sdtrig extension via M-mode CSRs Bin Meng
2022-03-15 6:55 ` [PATCH v4 1/7] target/riscv: Add initial support for the Sdtrig extension Bin Meng
2022-03-18 2:11 ` Alistair Francis
2022-03-15 6:55 ` [PATCH v4 2/7] target/riscv: machine: Add debug state description Bin Meng
2022-04-20 7:30 ` Alistair Francis
2022-04-20 7:33 ` Bin Meng
2022-04-20 9:52 ` Bin Meng
2022-04-20 22:45 ` Alistair Francis
2022-04-20 23:46 ` Bin Meng
2022-04-21 0:13 ` Alistair Francis
2022-04-21 0:19 ` Bin Meng
2022-04-21 15:51 ` Richard Henderson
2022-04-22 1:22 ` Bin Meng
2022-03-15 6:55 ` [PATCH v4 3/7] target/riscv: debug: Implement debug related TCGCPUOps Bin Meng
2022-03-15 6:55 ` [PATCH v4 4/7] target/riscv: cpu: Add a config option for native debug Bin Meng
2022-03-15 6:55 ` [PATCH v4 5/7] target/riscv: csr: Hook debug CSR read/write Bin Meng
2022-03-18 2:14 ` Alistair Francis
2022-03-15 6:55 ` [PATCH v4 6/7] target/riscv: cpu: Enable native debug feature Bin Meng
2022-03-18 2:17 ` Alistair Francis
2022-03-15 6:55 ` Bin Meng [this message]
2022-03-18 7:38 ` [PATCH v4 0/7] target/riscv: Initial support for the Sdtrig extension via M-mode CSRs Alistair Francis
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