From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: marex@denx.de, amir.gonnen@neuroblade.ai
Subject: [PATCH for-7.1 v6 18/51] target/nios2: Use hw/registerfields.h for CR_TLBMISC fields
Date: Wed, 16 Mar 2022 22:05:05 -0700 [thread overview]
Message-ID: <20220317050538.924111-19-richard.henderson@linaro.org> (raw)
In-Reply-To: <20220317050538.924111-1-richard.henderson@linaro.org>
Use FIELD_EX32 and FIELD_DP32 instead of managing the
masking by hand.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/nios2/cpu.h | 29 +++++++++++++++++++----------
target/nios2/helper.c | 7 ++-----
target/nios2/mmu.c | 35 +++++++++++++++++------------------
target/nios2/translate.c | 2 +-
4 files changed, 39 insertions(+), 34 deletions(-)
diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h
index 81472be686..7f805a933e 100644
--- a/target/nios2/cpu.h
+++ b/target/nios2/cpu.h
@@ -131,16 +131,25 @@ FIELD(CR_TLBACC, IG, 25, 7)
#define CR_TLBACC_G R_CR_TLBACC_G_MASK
#define CR_TLBMISC 10
-#define CR_TLBMISC_WAY_SHIFT 20
-#define CR_TLBMISC_WAY_MASK (0xF << CR_TLBMISC_WAY_SHIFT)
-#define CR_TLBMISC_RD (1 << 19)
-#define CR_TLBMISC_WE (1 << 18)
-#define CR_TLBMISC_PID_SHIFT 4
-#define CR_TLBMISC_PID_MASK (0x3FFF << CR_TLBMISC_PID_SHIFT)
-#define CR_TLBMISC_DBL (1 << 3)
-#define CR_TLBMISC_BAD (1 << 2)
-#define CR_TLBMISC_PERM (1 << 1)
-#define CR_TLBMISC_D (1 << 0)
+
+FIELD(CR_TLBMISC, D, 0, 1)
+FIELD(CR_TLBMISC, PERM, 1, 1)
+FIELD(CR_TLBMISC, BAD, 2, 1)
+FIELD(CR_TLBMISC, DBL, 3, 1)
+FIELD(CR_TLBMISC, PID, 4, 14)
+FIELD(CR_TLBMISC, WE, 18, 1)
+FIELD(CR_TLBMISC, RD, 19, 1)
+FIELD(CR_TLBMISC, WAY, 20, 4)
+FIELD(CR_TLBMISC, EE, 24, 1)
+
+#define CR_TLBMISC_EE R_CR_TLBMISC_EE_MASK
+#define CR_TLBMISC_RD R_CR_TLBMISC_RD_MASK
+#define CR_TLBMISC_WE R_CR_TLBMISC_WE_MASK
+#define CR_TLBMISC_DBL R_CR_TLBMISC_DBL_MASK
+#define CR_TLBMISC_BAD R_CR_TLBMISC_BAD_MASK
+#define CR_TLBMISC_PERM R_CR_TLBMISC_PERM_MASK
+#define CR_TLBMISC_D R_CR_TLBMISC_D_MASK
+
#define CR_ENCINJ 11
#define CR_BADADDR 12
#define CR_CONFIG 13
diff --git a/target/nios2/helper.c b/target/nios2/helper.c
index 308d66ad93..52a49f7ead 100644
--- a/target/nios2/helper.c
+++ b/target/nios2/helper.c
@@ -301,11 +301,8 @@ bool nios2_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
return false;
}
- if (access_type == MMU_INST_FETCH) {
- env->ctrl[CR_TLBMISC] &= ~CR_TLBMISC_D;
- } else {
- env->ctrl[CR_TLBMISC] |= CR_TLBMISC_D;
- }
+ env->ctrl[CR_TLBMISC] = FIELD_DP32(env->ctrl[CR_TLBMISC], CR_TLBMISC, D,
+ access_type != MMU_INST_FETCH);
env->ctrl[CR_PTEADDR] = FIELD_DP32(env->ctrl[CR_PTEADDR], CR_PTEADDR, VPN,
address >> TARGET_PAGE_BITS);
env->mmu.pteaddr_wr = env->ctrl[CR_PTEADDR];
diff --git a/target/nios2/mmu.c b/target/nios2/mmu.c
index 0f33ea5e04..d9b690b78e 100644
--- a/target/nios2/mmu.c
+++ b/target/nios2/mmu.c
@@ -33,7 +33,7 @@ unsigned int mmu_translate(CPUNios2State *env,
target_ulong vaddr, int rw, int mmu_idx)
{
Nios2CPU *cpu = env_archcpu(env);
- int pid = (env->mmu.tlbmisc_wr & CR_TLBMISC_PID_MASK) >> 4;
+ int pid = FIELD_EX32(env->mmu.tlbmisc_wr, CR_TLBMISC, PID);
int vpn = vaddr >> 12;
int way, n_ways = cpu->tlb_num_ways;
@@ -96,9 +96,9 @@ void helper_mmu_write_tlbacc(CPUNios2State *env, uint32_t v)
/* if tlbmisc.WE == 1 then trigger a TLB write on writes to TLBACC */
if (env->ctrl[CR_TLBMISC] & CR_TLBMISC_WE) {
- int way = (env->ctrl[CR_TLBMISC] >> CR_TLBMISC_WAY_SHIFT);
+ int way = FIELD_EX32(env->ctrl[CR_TLBMISC], CR_TLBMISC, WAY);
int vpn = FIELD_EX32(env->mmu.pteaddr_wr, CR_PTEADDR, VPN);
- int pid = (env->mmu.tlbmisc_wr & CR_TLBMISC_PID_MASK) >> 4;
+ int pid = FIELD_EX32(env->mmu.tlbmisc_wr, CR_TLBMISC, PID);
int g = FIELD_EX32(v, CR_TLBACC, G);
int valid = FIELD_EX32(vpn, CR_TLBACC, PFN) < 0xC0000;
Nios2TLBEntry *entry =
@@ -117,10 +117,9 @@ void helper_mmu_write_tlbacc(CPUNios2State *env, uint32_t v)
entry->data = newData;
}
/* Auto-increment tlbmisc.WAY */
- env->ctrl[CR_TLBMISC] =
- (env->ctrl[CR_TLBMISC] & ~CR_TLBMISC_WAY_MASK) |
- (((way + 1) & (cpu->tlb_num_ways - 1)) <<
- CR_TLBMISC_WAY_SHIFT);
+ env->ctrl[CR_TLBMISC] = FIELD_DP32(env->ctrl[CR_TLBMISC],
+ CR_TLBMISC, WAY,
+ (way + 1) & (cpu->tlb_num_ways - 1));
}
/* Writes to TLBACC don't change the read-back value */
@@ -130,24 +129,25 @@ void helper_mmu_write_tlbacc(CPUNios2State *env, uint32_t v)
void helper_mmu_write_tlbmisc(CPUNios2State *env, uint32_t v)
{
Nios2CPU *cpu = env_archcpu(env);
+ uint32_t new_pid = FIELD_EX32(v, CR_TLBMISC, PID);
+ uint32_t old_pid = FIELD_EX32(env->mmu.tlbmisc_wr, CR_TLBMISC, PID);
+ uint32_t way = FIELD_EX32(v, CR_TLBMISC, WAY);
- trace_nios2_mmu_write_tlbmisc(v >> CR_TLBMISC_WAY_SHIFT,
+ trace_nios2_mmu_write_tlbmisc(way,
(v & CR_TLBMISC_RD) ? 'R' : '.',
(v & CR_TLBMISC_WE) ? 'W' : '.',
(v & CR_TLBMISC_DBL) ? '2' : '.',
(v & CR_TLBMISC_BAD) ? 'B' : '.',
(v & CR_TLBMISC_PERM) ? 'P' : '.',
(v & CR_TLBMISC_D) ? 'D' : '.',
- (v & CR_TLBMISC_PID_MASK) >> 4);
+ new_pid);
- if ((v & CR_TLBMISC_PID_MASK) !=
- (env->mmu.tlbmisc_wr & CR_TLBMISC_PID_MASK)) {
- mmu_flush_pid(env, (env->mmu.tlbmisc_wr & CR_TLBMISC_PID_MASK) >>
- CR_TLBMISC_PID_SHIFT);
+ if (new_pid != old_pid) {
+ mmu_flush_pid(env, old_pid);
}
+
/* if tlbmisc.RD == 1 then trigger a TLB read on writes to TLBMISC */
if (v & CR_TLBMISC_RD) {
- int way = (v >> CR_TLBMISC_WAY_SHIFT);
int vpn = FIELD_EX32(env->mmu.pteaddr_wr, CR_PTEADDR, VPN);
Nios2TLBEntry *entry =
&env->mmu.tlb[(way * cpu->tlb_num_ways) +
@@ -156,10 +156,9 @@ void helper_mmu_write_tlbmisc(CPUNios2State *env, uint32_t v)
env->ctrl[CR_TLBACC] &= R_CR_TLBACC_IG_MASK;
env->ctrl[CR_TLBACC] |= entry->data;
env->ctrl[CR_TLBACC] |= (entry->tag & (1 << 11)) ? CR_TLBACC_G : 0;
- env->ctrl[CR_TLBMISC] =
- (v & ~CR_TLBMISC_PID_MASK) |
- ((entry->tag & ((1 << cpu->pid_num_bits) - 1)) <<
- CR_TLBMISC_PID_SHIFT);
+ env->ctrl[CR_TLBMISC] = FIELD_DP32(v, CR_TLBMISC, PID,
+ entry->tag &
+ ((1 << cpu->pid_num_bits) - 1));
env->ctrl[CR_PTEADDR] = FIELD_DP32(env->ctrl[CR_PTEADDR],
CR_PTEADDR, VPN,
entry->tag >> TARGET_PAGE_BITS);
diff --git a/target/nios2/translate.c b/target/nios2/translate.c
index 9b81a2b29e..459e30b338 100644
--- a/target/nios2/translate.c
+++ b/target/nios2/translate.c
@@ -924,7 +924,7 @@ void nios2_cpu_dump_state(CPUState *cs, FILE *f, int flags)
}
qemu_fprintf(f, " mmu write: VPN=%05X PID %02X TLBACC %08X\n",
env->mmu.pteaddr_wr & R_CR_PTEADDR_VPN_MASK,
- (env->mmu.tlbmisc_wr & CR_TLBMISC_PID_MASK) >> 4,
+ FIELD_EX32(env->mmu.tlbmisc_wr, CR_TLBMISC, PID),
env->mmu.tlbacc_wr);
#endif
qemu_fprintf(f, "\n\n");
--
2.25.1
next prev parent reply other threads:[~2022-03-17 5:19 UTC|newest]
Thread overview: 80+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-03-17 5:04 [PATCH for-7.1 v6 00/51] target/nios2: Shadow register set, EIC and VIC Richard Henderson
2022-03-17 5:04 ` [PATCH for-7.1 v6 01/51] tcg: Fix indirect lowering vs TCG_OPF_COND_BRANCH Richard Henderson
2022-03-17 13:38 ` Peter Maydell
2022-03-17 5:04 ` [PATCH for-7.1 v6 02/51] target/nios2: Check supervisor on eret Richard Henderson
2022-03-17 5:04 ` [PATCH for-7.1 v6 03/51] target/nios2: Stop generating code if gen_check_supervisor fails Richard Henderson
2022-03-17 5:04 ` [PATCH for-7.1 v6 04/51] target/nios2: Add NUM_GP_REGS and NUM_CP_REGS Richard Henderson
2022-03-17 5:04 ` [PATCH for-7.1 v6 05/51] target/nios2: Split PC out of env->regs[] Richard Henderson
2022-03-17 5:04 ` [PATCH for-7.1 v6 06/51] target/nios2: Split out helper for eret instruction Richard Henderson
2022-03-17 5:04 ` [PATCH for-7.1 v6 07/51] target/nios2: Fix BRET instruction Richard Henderson
2022-03-17 5:04 ` [PATCH for-7.1 v6 08/51] target/nios2: Do not create TCGv for control registers Richard Henderson
2022-03-17 5:04 ` [PATCH for-7.1 v6 09/51] linux-user/nios2: Only initialize SP and PC in target_cpu_copy_regs Richard Henderson
2022-03-17 5:04 ` [PATCH for-7.1 v6 10/51] target/nios2: Remove cpu_interrupts_enabled Richard Henderson
2022-03-17 5:04 ` [PATCH for-7.1 v6 11/51] target/nios2: Split control registers away from general registers Richard Henderson
2022-03-17 5:04 ` [PATCH for-7.1 v6 12/51] target/nios2: Clean up nios2_cpu_dump_state Richard Henderson
2022-03-17 5:05 ` [PATCH for-7.1 v6 13/51] target/nios2: Use hw/registerfields.h for CR_STATUS fields Richard Henderson
2022-03-17 15:13 ` Peter Maydell
2022-03-17 5:05 ` [PATCH for-7.1 v6 14/51] target/nios2: Use hw/registerfields.h for CR_EXCEPTION fields Richard Henderson
2022-03-17 5:05 ` [PATCH for-7.1 v6 15/51] target/nios2: Use hw/registerfields.h for CR_TLBADDR fields Richard Henderson
2022-03-17 5:05 ` [PATCH for-7.1 v6 16/51] target/nios2: Use hw/registerfields.h for CR_TLBACC fields Richard Henderson
2022-03-17 5:05 ` [PATCH for-7.1 v6 17/51] target/nios2: Rename CR_TLBMISC_WR to CR_TLBMISC_WE Richard Henderson
2022-03-17 5:05 ` Richard Henderson [this message]
2022-03-17 15:15 ` [PATCH for-7.1 v6 18/51] target/nios2: Use hw/registerfields.h for CR_TLBMISC fields Peter Maydell
2022-03-17 5:05 ` [PATCH for-7.1 v6 19/51] target/nios2: Move R_FOO and CR_BAR into enumerations Richard Henderson
2022-03-17 5:05 ` [PATCH for-7.1 v6 20/51] target/nios2: Create EXCP_SEMIHOST for semi-hosting Richard Henderson
2022-03-17 5:05 ` [PATCH for-7.1 v6 21/51] target/nios2: Clean up nios2_cpu_do_interrupt Richard Henderson
2022-03-17 15:24 ` Peter Maydell
2022-03-17 5:05 ` [PATCH for-7.1 v6 22/51] target/nios2: Hoist CPU_LOG_INT logging Richard Henderson
2022-03-17 15:25 ` Peter Maydell
2022-03-17 5:05 ` [PATCH for-7.1 v6 23/51] target/nios2: Handle EXCP_UNALIGN and EXCP_UALIGND Richard Henderson
2022-03-17 15:27 ` Peter Maydell
2022-03-17 16:47 ` Richard Henderson
2022-03-17 5:05 ` [PATCH for-7.1 v6 24/51] target/nios2: Cleanup set of CR_EXCEPTION for do_interrupt Richard Henderson
2022-03-17 15:28 ` Peter Maydell
2022-03-17 5:05 ` [PATCH for-7.1 v6 25/51] target/nios2: Clean up handling of tlbmisc in do_exception Richard Henderson
2022-03-17 15:41 ` Peter Maydell
2022-03-17 17:01 ` Richard Henderson
2022-03-17 5:05 ` [PATCH for-7.1 v6 26/51] target/nios2: Prevent writes to read-only or reserved control fields Richard Henderson
2022-03-17 15:49 ` Peter Maydell
2022-03-17 17:16 ` Richard Henderson
2022-03-17 5:05 ` [PATCH for-7.1 v6 27/51] target/nios2: Implement cpuid Richard Henderson
2022-03-17 5:05 ` [PATCH for-7.1 v6 28/51] target/nios2: Implement CR_STATUS.RSIE Richard Henderson
2022-03-17 5:05 ` [PATCH for-7.1 v6 29/51] target/nios2: Remove CPU_INTERRUPT_NMI Richard Henderson
2022-03-17 5:05 ` [PATCH for-7.1 v6 30/51] target/nios2: Support division error exception Richard Henderson
2022-03-17 15:52 ` Peter Maydell
2022-03-17 5:05 ` [PATCH for-7.1 v6 31/51] target/nios2: Use tcg_constant_tl Richard Henderson
2022-03-17 5:05 ` [PATCH for-7.1 v6 32/51] target/nios2: Introduce dest_gpr Richard Henderson
2022-03-17 5:05 ` [PATCH for-7.1 v6 33/51] target/nios2: Drop CR_STATUS_EH from tb->flags Richard Henderson
2022-03-17 5:05 ` [PATCH for-7.1 v6 34/51] target/nios2: Enable unaligned traps for system mode Richard Henderson
2022-03-17 16:06 ` Peter Maydell
2022-03-17 5:05 ` [PATCH for-7.1 v6 35/51] target/nios2: Create gen_jumpr Richard Henderson
2022-03-17 16:24 ` Peter Maydell
2022-03-17 5:05 ` [PATCH for-7.1 v6 36/51] target/nios2: Hoist set of is_jmp into gen_goto_tb Richard Henderson
2022-03-17 16:25 ` Peter Maydell
2022-03-17 5:05 ` [PATCH for-7.1 v6 37/51] target/nios2: Use gen_goto_tb for DISAS_TOO_MANY Richard Henderson
2022-03-17 16:28 ` Peter Maydell
2022-03-17 5:05 ` [PATCH for-7.1 v6 38/51] target/nios2: Use tcg_gen_lookup_and_goto_ptr Richard Henderson
2022-03-17 16:29 ` Peter Maydell
2022-03-17 5:05 ` [PATCH for-7.1 v6 39/51] target/nios2: Implement Misaligned destination exception Richard Henderson
2022-03-17 16:37 ` Peter Maydell
2022-03-17 17:41 ` Richard Henderson
2022-03-17 5:05 ` [PATCH for-7.1 v6 40/51] linux-user/nios2: Handle various SIGILL exceptions Richard Henderson
2022-03-17 16:38 ` Peter Maydell
2022-03-17 5:05 ` [PATCH for-7.1 v6 41/51] target/nios2: Introduce shadow register sets Richard Henderson
2022-03-17 18:33 ` Peter Maydell
2022-03-17 19:31 ` Richard Henderson
2022-03-17 5:05 ` [PATCH for-7.1 v6 42/51] target/nios2: Implement rdprs, wrprs Richard Henderson
2022-03-17 18:47 ` Peter Maydell
2022-03-17 5:05 ` [PATCH for-7.1 v6 43/51] target/nios2: Update helper_eret for shadow registers Richard Henderson
2022-03-17 18:53 ` Peter Maydell
2022-03-17 5:05 ` [PATCH for-7.1 v6 44/51] target/nios2: Implement EIC interrupt processing Richard Henderson
2022-03-17 19:11 ` Peter Maydell
2022-03-17 19:54 ` Richard Henderson
2022-03-17 5:05 ` [PATCH for-7.1 v6 45/51] hw/intc: Vectored Interrupt Controller (VIC) Richard Henderson
2022-03-17 5:05 ` [PATCH for-7.1 v6 46/51] hw/nios2: Introduce Nios2MachineState Richard Henderson
2022-03-17 5:05 ` [PATCH for-7.1 v6 47/51] hw/nios2: Move memory regions into Nios2Machine Richard Henderson
2022-03-17 5:05 ` [PATCH for-7.1 v6 48/51] hw/nios2: Machine with a Vectored Interrupt Controller Richard Henderson
2022-03-17 5:05 ` [PATCH for-7.1 v6 49/51] tests/tcg: Expose AR to test build environment if needed Richard Henderson
2022-03-17 5:05 ` [PATCH for-7.1 v6 50/51] test/tcg/nios2: Add semihosting multiarch tests Richard Henderson
2022-03-17 5:05 ` [PATCH for-7.1 v6 51/51] tests/tcg/nios2: Add test-shadow-1 Richard Henderson
2022-03-22 12:17 ` [PATCH for-7.1 v6 00/51] target/nios2: Shadow register set, EIC and VIC Amir Gonnen
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