From: Xiaoyao Li <xiaoyao.li@intel.com>
To: "Paolo Bonzini" <pbonzini@redhat.com>,
"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
"Richard Henderson" <richard.henderson@linaro.org>,
"Michael S. Tsirkin" <mst@redhat.com>,
"Marcel Apfelbaum" <marcel.apfelbaum@gmail.com>,
"Cornelia Huck" <cohuck@redhat.com>,
"Daniel P. Berrangé" <berrange@redhat.com>,
"Marcelo Tosatti" <mtosatti@redhat.com>,
"Laszlo Ersek" <lersek@redhat.com>,
"Gerd Hoffmann" <kraxel@redhat.com>,
"Eric Blake" <eblake@redhat.com>
Cc: isaku.yamahata@intel.com, kvm@vger.kernel.org,
Connor Kuehl <ckuehl@redhat.com>,
seanjc@google.com, xiaoyao.li@intel.com, qemu-devel@nongnu.org,
erdemaktas@google.com
Subject: [RFC PATCH v3 31/36] hw/i386: add option to forcibly report edge trigger in acpi tables
Date: Thu, 17 Mar 2022 21:59:08 +0800 [thread overview]
Message-ID: <20220317135913.2166202-32-xiaoyao.li@intel.com> (raw)
In-Reply-To: <20220317135913.2166202-1-xiaoyao.li@intel.com>
From: Isaku Yamahata <isaku.yamahata@intel.com>
When level trigger isn't supported on x86 platform,
forcibly report edge trigger in acpi tables.
Signed-off-by: Isaku Yamahata <isaku.yamahata@intel.com>
Signed-off-by: Xiaoyao Li <xiaoyao.li@intel.com>
---
hw/i386/acpi-build.c | 99 ++++++++++++++++++++++++++++---------------
hw/i386/acpi-common.c | 50 ++++++++++++++++------
2 files changed, 104 insertions(+), 45 deletions(-)
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index 4ad4d7286c89..a2323bad6e82 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -912,7 +912,8 @@ static void build_dbg_aml(Aml *table)
aml_append(table, scope);
}
-static Aml *build_link_dev(const char *name, uint8_t uid, Aml *reg)
+static Aml *build_link_dev(const char *name, uint8_t uid, Aml *reg,
+ bool level_trigger_unsupported)
{
Aml *dev;
Aml *crs;
@@ -924,7 +925,10 @@ static Aml *build_link_dev(const char *name, uint8_t uid, Aml *reg)
aml_append(dev, aml_name_decl("_UID", aml_int(uid)));
crs = aml_resource_template();
- aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
+ aml_append(crs, aml_interrupt(AML_CONSUMER,
+ level_trigger_unsupported ?
+ AML_EDGE : AML_LEVEL,
+ AML_ACTIVE_HIGH,
AML_SHARED, irqs, ARRAY_SIZE(irqs)));
aml_append(dev, aml_name_decl("_PRS", crs));
@@ -948,7 +952,8 @@ static Aml *build_link_dev(const char *name, uint8_t uid, Aml *reg)
return dev;
}
-static Aml *build_gsi_link_dev(const char *name, uint8_t uid, uint8_t gsi)
+static Aml *build_gsi_link_dev(const char *name, uint8_t uid,
+ uint8_t gsi, bool level_trigger_unsupported)
{
Aml *dev;
Aml *crs;
@@ -961,7 +966,10 @@ static Aml *build_gsi_link_dev(const char *name, uint8_t uid, uint8_t gsi)
crs = aml_resource_template();
irqs = gsi;
- aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
+ aml_append(crs, aml_interrupt(AML_CONSUMER,
+ level_trigger_unsupported ?
+ AML_EDGE : AML_LEVEL,
+ AML_ACTIVE_HIGH,
AML_SHARED, &irqs, 1));
aml_append(dev, aml_name_decl("_PRS", crs));
@@ -980,7 +988,7 @@ static Aml *build_gsi_link_dev(const char *name, uint8_t uid, uint8_t gsi)
}
/* _CRS method - get current settings */
-static Aml *build_iqcr_method(bool is_piix4)
+static Aml *build_iqcr_method(bool is_piix4, bool level_trigger_unsupported)
{
Aml *if_ctx;
uint32_t irqs;
@@ -988,7 +996,9 @@ static Aml *build_iqcr_method(bool is_piix4)
Aml *crs = aml_resource_template();
irqs = 0;
- aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL,
+ aml_append(crs, aml_interrupt(AML_CONSUMER,
+ level_trigger_unsupported ?
+ AML_EDGE : AML_LEVEL,
AML_ACTIVE_HIGH, AML_SHARED, &irqs, 1));
aml_append(method, aml_name_decl("PRR0", crs));
@@ -1022,7 +1032,7 @@ static Aml *build_irq_status_method(void)
return method;
}
-static void build_piix4_pci0_int(Aml *table)
+static void build_piix4_pci0_int(Aml *table, bool level_trigger_unsupported)
{
Aml *dev;
Aml *crs;
@@ -1043,12 +1053,16 @@ static void build_piix4_pci0_int(Aml *table)
aml_append(sb_scope, field);
aml_append(sb_scope, build_irq_status_method());
- aml_append(sb_scope, build_iqcr_method(true));
+ aml_append(sb_scope, build_iqcr_method(true, level_trigger_unsupported));
- aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQ0")));
- aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQ1")));
- aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQ2")));
- aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQ3")));
+ aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQ0"),
+ level_trigger_unsupported));
+ aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQ1"),
+ level_trigger_unsupported));
+ aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQ2"),
+ level_trigger_unsupported));
+ aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQ3"),
+ level_trigger_unsupported));
dev = aml_device("LNKS");
{
@@ -1057,7 +1071,9 @@ static void build_piix4_pci0_int(Aml *table)
crs = aml_resource_template();
irqs = 9;
- aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL,
+ aml_append(crs, aml_interrupt(AML_CONSUMER,
+ level_trigger_unsupported ?
+ AML_EDGE : AML_LEVEL,
AML_ACTIVE_HIGH, AML_SHARED,
&irqs, 1));
aml_append(dev, aml_name_decl("_PRS", crs));
@@ -1143,7 +1159,7 @@ static Aml *build_q35_routing_table(const char *str)
return pkg;
}
-static void build_q35_pci0_int(Aml *table)
+static void build_q35_pci0_int(Aml *table, bool level_trigger_unsupported)
{
Aml *field;
Aml *method;
@@ -1195,25 +1211,41 @@ static void build_q35_pci0_int(Aml *table)
aml_append(sb_scope, field);
aml_append(sb_scope, build_irq_status_method());
- aml_append(sb_scope, build_iqcr_method(false));
+ aml_append(sb_scope, build_iqcr_method(false, level_trigger_unsupported));
- aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQA")));
- aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQB")));
- aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQC")));
- aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQD")));
- aml_append(sb_scope, build_link_dev("LNKE", 4, aml_name("PRQE")));
- aml_append(sb_scope, build_link_dev("LNKF", 5, aml_name("PRQF")));
- aml_append(sb_scope, build_link_dev("LNKG", 6, aml_name("PRQG")));
- aml_append(sb_scope, build_link_dev("LNKH", 7, aml_name("PRQH")));
+ aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQA"),
+ level_trigger_unsupported));
+ aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQB"),
+ level_trigger_unsupported));
+ aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQC"),
+ level_trigger_unsupported));
+ aml_append(sb_scope, build_link_dev("LNKD", 3, aml_name("PRQD"),
+ level_trigger_unsupported));
+ aml_append(sb_scope, build_link_dev("LNKE", 4, aml_name("PRQE"),
+ level_trigger_unsupported));
+ aml_append(sb_scope, build_link_dev("LNKF", 5, aml_name("PRQF"),
+ level_trigger_unsupported));
+ aml_append(sb_scope, build_link_dev("LNKG", 6, aml_name("PRQG"),
+ level_trigger_unsupported));
+ aml_append(sb_scope, build_link_dev("LNKH", 7, aml_name("PRQH"),
+ level_trigger_unsupported));
- aml_append(sb_scope, build_gsi_link_dev("GSIA", 0x10, 0x10));
- aml_append(sb_scope, build_gsi_link_dev("GSIB", 0x11, 0x11));
- aml_append(sb_scope, build_gsi_link_dev("GSIC", 0x12, 0x12));
- aml_append(sb_scope, build_gsi_link_dev("GSID", 0x13, 0x13));
- aml_append(sb_scope, build_gsi_link_dev("GSIE", 0x14, 0x14));
- aml_append(sb_scope, build_gsi_link_dev("GSIF", 0x15, 0x15));
- aml_append(sb_scope, build_gsi_link_dev("GSIG", 0x16, 0x16));
- aml_append(sb_scope, build_gsi_link_dev("GSIH", 0x17, 0x17));
+ aml_append(sb_scope, build_gsi_link_dev("GSIA", 0x10, 0x10,
+ level_trigger_unsupported));
+ aml_append(sb_scope, build_gsi_link_dev("GSIB", 0x11, 0x11,
+ level_trigger_unsupported));
+ aml_append(sb_scope, build_gsi_link_dev("GSIC", 0x12, 0x12,
+ level_trigger_unsupported));
+ aml_append(sb_scope, build_gsi_link_dev("GSID", 0x13, 0x13,
+ level_trigger_unsupported));
+ aml_append(sb_scope, build_gsi_link_dev("GSIE", 0x14, 0x14,
+ level_trigger_unsupported));
+ aml_append(sb_scope, build_gsi_link_dev("GSIF", 0x15, 0x15,
+ level_trigger_unsupported));
+ aml_append(sb_scope, build_gsi_link_dev("GSIG", 0x16, 0x16,
+ level_trigger_unsupported));
+ aml_append(sb_scope, build_gsi_link_dev("GSIH", 0x17, 0x17,
+ level_trigger_unsupported));
aml_append(table, sb_scope);
}
@@ -1420,6 +1452,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker,
PCMachineState *pcms = PC_MACHINE(machine);
PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(machine);
X86MachineState *x86ms = X86_MACHINE(machine);
+ bool level_trigger_unsupported = x86ms->eoi_intercept_unsupported;
AcpiMcfgInfo mcfg;
bool mcfg_valid = !!acpi_get_mcfg(&mcfg);
uint32_t nr_mem = machine->ram_slots;
@@ -1454,7 +1487,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker,
if (pm->pcihp_bridge_en || pm->pcihp_root_en) {
build_x86_acpi_pci_hotplug(dsdt, pm->pcihp_io_base);
}
- build_piix4_pci0_int(dsdt);
+ build_piix4_pci0_int(dsdt, level_trigger_unsupported);
} else {
sb_scope = aml_scope("_SB");
dev = aml_device("PCI0");
@@ -1503,7 +1536,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker,
if (pm->pcihp_bridge_en) {
build_x86_acpi_pci_hotplug(dsdt, pm->pcihp_io_base);
}
- build_q35_pci0_int(dsdt);
+ build_q35_pci0_int(dsdt, level_trigger_unsupported);
if (pcms->smbus && !pcmc->do_not_add_smb_acpi) {
build_smb0(dsdt, pcms->smbus, ICH9_SMB_DEV, ICH9_SMB_FUNC);
}
diff --git a/hw/i386/acpi-common.c b/hw/i386/acpi-common.c
index 4aaafbdd7b5d..485fc17816be 100644
--- a/hw/i386/acpi-common.c
+++ b/hw/i386/acpi-common.c
@@ -105,6 +105,7 @@ void acpi_build_madt(GArray *table_data, BIOSLinker *linker,
AcpiDeviceIfClass *adevc = ACPI_DEVICE_IF_GET_CLASS(adev);
AcpiTable table = { .sig = "APIC", .rev = 1, .oem_id = oem_id,
.oem_table_id = oem_table_id };
+ bool level_trigger_unsupported = x86ms->eoi_intercept_unsupported;
acpi_table_begin(&table, table_data);
/* Local APIC Address */
@@ -124,18 +125,43 @@ void acpi_build_madt(GArray *table_data, BIOSLinker *linker,
IO_APIC_SECONDARY_ADDRESS, IO_APIC_SECONDARY_IRQBASE);
}
- if (x86ms->apic_xrupt_override) {
- build_xrupt_override(table_data, 0, 2,
- 0 /* Flags: Conforms to the specifications of the bus */);
- }
-
- for (i = 1; i < 16; i++) {
- if (!(x86ms->pci_irq_mask & (1 << i))) {
- /* No need for a INT source override structure. */
- continue;
- }
- build_xrupt_override(table_data, i, i,
- 0xd /* Flags: Active high, Level Triggered */);
+ if (level_trigger_unsupported) {
+ /* Force edge trigger */
+ if (x86ms->apic_xrupt_override) {
+ build_xrupt_override(table_data, 0, 2,
+ /* Flags: active high, edge triggered */
+ 1 | (1 << 2));
+ }
+
+ for (i = x86ms->apic_xrupt_override ? 1 : 0; i < 16; i++) {
+ build_xrupt_override(table_data, i, i,
+ /* Flags: active high, edge triggered */
+ 1 | (1 << 2));
+ }
+
+ if (x86ms->ioapic2) {
+ for (i = 0; i < 16; i++) {
+ build_xrupt_override(table_data, IO_APIC_SECONDARY_IRQBASE + i,
+ IO_APIC_SECONDARY_IRQBASE + i,
+ /* Flags: active high, edge triggered */
+ 1 | (1 << 2));
+ }
+ }
+ } else {
+ if (x86ms->apic_xrupt_override) {
+ build_xrupt_override(table_data, 0, 2,
+ 0 /* Flags: Conforms to the specifications of the bus */);
+ }
+
+ for (i = 1; i < 16; i++) {
+ if (!(x86ms->pci_irq_mask & (1 << i))) {
+ /* No need for a INT source override structure. */
+ continue;
+ }
+ build_xrupt_override(table_data, i, i,
+ 0xd /* Flags: Active high, Level Triggered */);
+
+ }
}
if (x2apic_mode) {
--
2.27.0
next prev parent reply other threads:[~2022-03-17 14:56 UTC|newest]
Thread overview: 77+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-03-17 13:58 [RFC PATCH v3 00/36] TDX QEMU support Xiaoyao Li
2022-03-17 13:58 ` [RFC PATCH v3 01/36] *** HACK *** linux-headers: Update headers to pull in TDX API changes Xiaoyao Li
2022-03-17 13:58 ` [RFC PATCH v3 02/36] i386: Introduce tdx-guest object Xiaoyao Li
2022-03-17 13:58 ` [RFC PATCH v3 03/36] target/i386: Implement mc->kvm_type() to get VM type Xiaoyao Li
2022-03-17 13:58 ` [RFC PATCH v3 04/36] target/i386: Introduce kvm_confidential_guest_init() Xiaoyao Li
2022-03-17 13:58 ` [RFC PATCH v3 05/36] i386/tdx: Implement tdx_kvm_init() to initialize TDX VM context Xiaoyao Li
2022-03-18 2:07 ` Isaku Yamahata
2022-03-21 5:35 ` Xiaoyao Li
2022-03-17 13:58 ` [RFC PATCH v3 06/36] i386/tdx: Get tdx_capabilities via KVM_TDX_CAPABILITIES Xiaoyao Li
2022-03-18 2:08 ` Isaku Yamahata
2022-03-21 6:56 ` Xiaoyao Li
2022-03-17 13:58 ` [RFC PATCH v3 07/36] i386/tdx: Introduce is_tdx_vm() helper and cache tdx_guest object Xiaoyao Li
2022-03-17 13:58 ` [RFC PATCH v3 08/36] i386/tdx: Adjust get_supported_cpuid() for TDX VM Xiaoyao Li
2022-03-18 16:55 ` Isaku Yamahata
2022-03-21 5:37 ` Xiaoyao Li
2022-03-17 13:58 ` [RFC PATCH v3 09/36] KVM: Introduce kvm_arch_pre_create_vcpu() Xiaoyao Li
2022-03-18 16:56 ` Isaku Yamahata
2022-03-21 7:02 ` Xiaoyao Li
2022-03-17 13:58 ` [RFC PATCH v3 10/36] i386/kvm: Move architectural CPUID leaf generation to separate helper Xiaoyao Li
2022-03-17 13:58 ` [RFC PATCH v3 11/36] i386/tdx: Initialize TDX before creating TD vcpus Xiaoyao Li
2022-03-17 13:58 ` [RFC PATCH v3 12/36] i386/tdx: Add property sept-ve-disable for tdx-guest object Xiaoyao Li
2022-03-22 9:02 ` Gerd Hoffmann
2022-03-24 6:52 ` Xiaoyao Li
2022-03-24 7:57 ` Gerd Hoffmann
2022-03-24 8:08 ` Xiaoyao Li
2022-03-24 9:37 ` Gerd Hoffmann
2022-03-24 14:36 ` Xiaoyao Li
2022-03-25 1:35 ` Isaku Yamahata
2022-03-17 13:58 ` [RFC PATCH v3 13/36] i386/tdx: Wire CPU features up with attributes of TD guest Xiaoyao Li
2022-03-17 13:58 ` [RFC PATCH v3 14/36] i386/tdx: Validate TD attributes Xiaoyao Li
2022-03-17 13:58 ` [RFC PATCH v3 15/36] i386/tdx: Implement user specified tsc frequency Xiaoyao Li
2022-03-17 13:58 ` [RFC PATCH v3 16/36] i386/tdx: Set kvm_readonly_mem_enabled to false for TDX VM Xiaoyao Li
2022-03-18 17:11 ` Isaku Yamahata
2022-03-21 8:15 ` Xiaoyao Li
2022-03-17 13:58 ` [RFC PATCH v3 17/36] pflash_cfi01/tdx: Introduce ram_mode of pflash for TDVF Xiaoyao Li
2022-03-18 14:07 ` Philippe Mathieu-Daudé
2022-03-21 8:54 ` Xiaoyao Li
2022-03-21 22:06 ` Isaku Yamahata
2022-03-22 9:21 ` Gerd Hoffmann
2022-03-22 9:29 ` Daniel P. Berrangé
2022-03-22 10:35 ` Gerd Hoffmann
2022-03-22 10:51 ` Daniel P. Berrangé
2022-03-22 12:20 ` Gerd Hoffmann
2022-03-24 8:35 ` Gerd Hoffmann
2022-03-31 6:57 ` Xiaoyao Li
2022-03-24 6:13 ` Xiaoyao Li
2022-03-24 7:58 ` Gerd Hoffmann
2022-03-24 8:18 ` Xiaoyao Li
2022-03-24 8:52 ` Daniel P. Berrangé
2022-03-22 9:27 ` Daniel P. Berrangé
2022-03-31 8:51 ` Xiaoyao Li
2022-03-31 9:00 ` Daniel P. Berrangé
2022-03-31 14:50 ` Xiaoyao Li
2022-03-17 13:58 ` [RFC PATCH v3 18/36] i386/tdvf: Introduce function to parse TDVF metadata Xiaoyao Li
2022-03-18 17:19 ` Isaku Yamahata
2022-03-21 6:11 ` Xiaoyao Li
2022-03-17 13:58 ` [RFC PATCH v3 19/36] i386/tdx: Parse TDVF metadata for TDX VM Xiaoyao Li
2022-03-17 13:58 ` [RFC PATCH v3 20/36] i386/tdx: Get and store the mem_ptr of TDVF firmware Xiaoyao Li
2022-03-17 13:58 ` [RFC PATCH v3 21/36] i386/tdx: Track mem_ptr for each firmware entry of TDVF Xiaoyao Li
2022-03-17 13:58 ` [RFC PATCH v3 22/36] i386/tdx: Track RAM entries for TDX VM Xiaoyao Li
2022-03-17 13:59 ` [RFC PATCH v3 23/36] i386/tdx: Create the TD HOB list upon machine init done Xiaoyao Li
2022-03-17 13:59 ` [RFC PATCH v3 24/36] i386/tdx: Call KVM_TDX_INIT_VCPU to initialize TDX vcpu Xiaoyao Li
2022-03-17 13:59 ` [RFC PATCH v3 25/36] i386/tdx: Add TDVF memory via KVM_TDX_INIT_MEM_REGION Xiaoyao Li
2022-03-17 13:59 ` [RFC PATCH v3 26/36] i386/tdx: Finalize TDX VM Xiaoyao Li
2022-03-17 13:59 ` [RFC PATCH v3 27/36] i386/tdx: Disable SMM for TDX VMs Xiaoyao Li
2022-03-21 6:51 ` Xiaoyao Li
2022-03-17 13:59 ` [RFC PATCH v3 28/36] i386/tdx: Disable PIC " Xiaoyao Li
2022-03-17 13:59 ` [RFC PATCH v3 29/36] i386/tdx: Don't allow system reset " Xiaoyao Li
2022-03-17 13:59 ` [RFC PATCH v3 30/36] hw/i386: add eoi_intercept_unsupported member to X86MachineState Xiaoyao Li
2022-03-17 13:59 ` Xiaoyao Li [this message]
2022-03-17 13:59 ` [RFC PATCH v3 32/36] i386/tdx: Don't synchronize guest tsc for TDs Xiaoyao Li
2022-03-17 13:59 ` [RFC PATCH v3 33/36] i386/tdx: Only configure MSR_IA32_UCODE_REV in kvm_init_msrs() " Xiaoyao Li
2022-03-18 17:31 ` Isaku Yamahata
2022-03-21 6:08 ` Xiaoyao Li
2022-03-17 13:59 ` [RFC PATCH v3 34/36] i386/tdx: Skip kvm_put_apicbase() " Xiaoyao Li
2022-03-17 13:59 ` [RFC PATCH v3 35/36] i386/tdx: Don't get/put guest state for TDX VMs Xiaoyao Li
2022-03-17 13:59 ` [RFC PATCH v3 36/36] docs: Add TDX documentation Xiaoyao Li
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