* [PULL 1/3] ppc64: Avoid pt_regs struct definition
2022-03-21 6:44 [PULL 0/3] ppc queue Cédric Le Goater
@ 2022-03-21 6:44 ` Cédric Le Goater
2022-03-21 6:44 ` [PULL 2/3] target/ppc: Replicate double->int32 result for some vector insns Cédric Le Goater
` (2 subsequent siblings)
3 siblings, 0 replies; 5+ messages in thread
From: Cédric Le Goater @ 2022-03-21 6:44 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Cédric Le Goater, Richard Henderson, Khem Raj,
Philippe Mathieu-Daudé
From: Khem Raj <raj.khem@gmail.com>
Remove pt_regs indirection and instead reference gp_regs directly, this
makes it portable across musl/glibc
Use PT_* constants defined in asm/ptrace.h
Move the file to ppc64 subdir and leave ppc empty
Fixes
../qemu-6.2.0/linux-user/host/ppc64/../ppc/host-signal.h:16:32: error: incomplete definition of type 'struct pt_regs'
return uc->uc_mcontext.regs->nip;
~~~~~~~~~~~~~~~~~~~~^
Signed-off-by: Khem Raj <raj.khem@gmail.com>
Cc: Peter Maydell <peter.maydell@linaro.org>
Cc: Philippe Mathieu-Daudé <f4bug@amsat.org>
Cc: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220315015740.847370-1-raj.khem@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
linux-user/include/host/ppc/host-signal.h | 38 -------------------
linux-user/include/host/ppc64/host-signal.h | 42 ++++++++++++++++++++-
2 files changed, 41 insertions(+), 39 deletions(-)
delete mode 100644 linux-user/include/host/ppc/host-signal.h
diff --git a/linux-user/include/host/ppc/host-signal.h b/linux-user/include/host/ppc/host-signal.h
deleted file mode 100644
index b80384d1356d..000000000000
--- a/linux-user/include/host/ppc/host-signal.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * host-signal.h: signal info dependent on the host architecture
- *
- * Copyright (c) 2003-2005 Fabrice Bellard
- * Copyright (c) 2021 Linaro Limited
- *
- * This work is licensed under the terms of the GNU LGPL, version 2.1 or later.
- * See the COPYING file in the top-level directory.
- */
-
-#ifndef PPC_HOST_SIGNAL_H
-#define PPC_HOST_SIGNAL_H
-
-/* The third argument to a SA_SIGINFO handler is ucontext_t. */
-typedef ucontext_t host_sigcontext;
-
-static inline uintptr_t host_signal_pc(host_sigcontext *uc)
-{
- return uc->uc_mcontext.regs->nip;
-}
-
-static inline void host_signal_set_pc(host_sigcontext *uc, uintptr_t pc)
-{
- uc->uc_mcontext.regs->nip = pc;
-}
-
-static inline void *host_signal_mask(host_sigcontext *uc)
-{
- return &uc->uc_sigmask;
-}
-
-static inline bool host_signal_write(siginfo_t *info, host_sigcontext *uc)
-{
- return uc->uc_mcontext.regs->trap != 0x400
- && (uc->uc_mcontext.regs->dsisr & 0x02000000);
-}
-
-#endif
diff --git a/linux-user/include/host/ppc64/host-signal.h b/linux-user/include/host/ppc64/host-signal.h
index a353c22a908c..c4ea86647291 100644
--- a/linux-user/include/host/ppc64/host-signal.h
+++ b/linux-user/include/host/ppc64/host-signal.h
@@ -1 +1,41 @@
-#include "../ppc/host-signal.h"
+/*
+ * host-signal.h: signal info dependent on the host architecture
+ *
+ * Copyright (c) 2003-2005 Fabrice Bellard
+ * Copyright (c) 2021 Linaro Limited
+ *
+ * This work is licensed under the terms of the GNU LGPL, version 2.1 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#ifndef PPC_HOST_SIGNAL_H
+#define PPC_HOST_SIGNAL_H
+
+/* Needed for PT_* constants */
+#include <asm/ptrace.h>
+
+/* The third argument to a SA_SIGINFO handler is ucontext_t. */
+typedef ucontext_t host_sigcontext;
+
+static inline uintptr_t host_signal_pc(host_sigcontext *uc)
+{
+ return uc->uc_mcontext.gp_regs[PT_NIP];
+}
+
+static inline void host_signal_set_pc(host_sigcontext *uc, uintptr_t pc)
+{
+ uc->uc_mcontext.gp_regs[PT_NIP] = pc;
+}
+
+static inline void *host_signal_mask(host_sigcontext *uc)
+{
+ return &uc->uc_sigmask;
+}
+
+static inline bool host_signal_write(siginfo_t *info, host_sigcontext *uc)
+{
+ return uc->uc_mcontext.gp_regs[PT_TRAP] != 0x400
+ && (uc->uc_mcontext.gp_regs[PT_DSISR] & 0x02000000);
+}
+
+#endif
--
2.34.1
^ permalink raw reply related [flat|nested] 5+ messages in thread* [PULL 2/3] target/ppc: Replicate double->int32 result for some vector insns
2022-03-21 6:44 [PULL 0/3] ppc queue Cédric Le Goater
2022-03-21 6:44 ` [PULL 1/3] ppc64: Avoid pt_regs struct definition Cédric Le Goater
@ 2022-03-21 6:44 ` Cédric Le Goater
2022-03-21 6:44 ` [PULL 3/3] target/ppc: Replicate Double->Single-Precision result Cédric Le Goater
2022-03-21 15:26 ` [PULL 0/3] ppc queue Peter Maydell
3 siblings, 0 replies; 5+ messages in thread
From: Cédric Le Goater @ 2022-03-21 6:44 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Peter Maydell, Richard Henderson, Cédric Le Goater
From: Richard Henderson <richard.henderson@linaro.org>
Power ISA v3.1 formalizes the previously undefined result in
words 1 and 3 to be a copy of the result in words 0 and 2.
This affects: xscvdpsxws, xscvdpuxws, xvcvdpsxws, xvcvdpuxws.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/852
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
[ clg: checkpatch fixes ]
Message-Id: <20220315053934.377519-1-richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/fpu_helper.c | 45 +++++++++++++++++++++++++++++++++++------
1 file changed, 39 insertions(+), 6 deletions(-)
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
index bd12db960af3..564f2ec35374 100644
--- a/target/ppc/fpu_helper.c
+++ b/target/ppc/fpu_helper.c
@@ -2891,22 +2891,55 @@ void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) \
VSX_CVT_FP_TO_INT(xscvdpsxds, 1, float64, int64, VsrD(0), VsrD(0), \
0x8000000000000000ULL)
-VSX_CVT_FP_TO_INT(xscvdpsxws, 1, float64, int32, VsrD(0), VsrW(1), \
- 0x80000000U)
VSX_CVT_FP_TO_INT(xscvdpuxds, 1, float64, uint64, VsrD(0), VsrD(0), 0ULL)
-VSX_CVT_FP_TO_INT(xscvdpuxws, 1, float64, uint32, VsrD(0), VsrW(1), 0U)
VSX_CVT_FP_TO_INT(xvcvdpsxds, 2, float64, int64, VsrD(i), VsrD(i), \
0x8000000000000000ULL)
-VSX_CVT_FP_TO_INT(xvcvdpsxws, 2, float64, int32, VsrD(i), VsrW(2 * i), \
- 0x80000000U)
VSX_CVT_FP_TO_INT(xvcvdpuxds, 2, float64, uint64, VsrD(i), VsrD(i), 0ULL)
-VSX_CVT_FP_TO_INT(xvcvdpuxws, 2, float64, uint32, VsrD(i), VsrW(2 * i), 0U)
VSX_CVT_FP_TO_INT(xvcvspsxds, 2, float32, int64, VsrW(2 * i), VsrD(i), \
0x8000000000000000ULL)
VSX_CVT_FP_TO_INT(xvcvspsxws, 4, float32, int32, VsrW(i), VsrW(i), 0x80000000U)
VSX_CVT_FP_TO_INT(xvcvspuxds, 2, float32, uint64, VsrW(2 * i), VsrD(i), 0ULL)
VSX_CVT_FP_TO_INT(xvcvspuxws, 4, float32, uint32, VsrW(i), VsrW(i), 0U)
+/*
+ * Likewise, except that the result is duplicated into both subwords.
+ * Power ISA v3.1 has Programming Notes for these insns:
+ * Previous versions of the architecture allowed the contents of
+ * word 0 of the result register to be undefined. However, all
+ * processors that support this instruction write the result into
+ * words 0 and 1 (and words 2 and 3) of the result register, as
+ * is required by this version of the architecture.
+ */
+#define VSX_CVT_FP_TO_INT2(op, nels, stp, ttp, rnan) \
+void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) \
+{ \
+ int all_flags = env->fp_status.float_exception_flags, flags; \
+ ppc_vsr_t t = { }; \
+ int i; \
+ \
+ for (i = 0; i < nels; i++) { \
+ env->fp_status.float_exception_flags = 0; \
+ t.VsrW(2 * i) = stp##_to_##ttp##_round_to_zero(xb->VsrD(i), \
+ &env->fp_status); \
+ flags = env->fp_status.float_exception_flags; \
+ if (unlikely(flags & float_flag_invalid)) { \
+ t.VsrW(2 * i) = float_invalid_cvt(env, flags, t.VsrW(2 * i), \
+ rnan, 0, GETPC()); \
+ } \
+ t.VsrW(2 * i + 1) = t.VsrW(2 * i); \
+ all_flags |= flags; \
+ } \
+ \
+ *xt = t; \
+ env->fp_status.float_exception_flags = all_flags; \
+ do_float_check_status(env, GETPC()); \
+}
+
+VSX_CVT_FP_TO_INT2(xscvdpsxws, 1, float64, int32, 0x80000000U)
+VSX_CVT_FP_TO_INT2(xscvdpuxws, 1, float64, uint32, 0U)
+VSX_CVT_FP_TO_INT2(xvcvdpsxws, 2, float64, int32, 0x80000000U)
+VSX_CVT_FP_TO_INT2(xvcvdpuxws, 2, float64, uint32, 0U)
+
/*
* VSX_CVT_FP_TO_INT_VECTOR - VSX floating point to integer conversion
* op - instruction mnemonic
--
2.34.1
^ permalink raw reply related [flat|nested] 5+ messages in thread* [PULL 3/3] target/ppc: Replicate Double->Single-Precision result
2022-03-21 6:44 [PULL 0/3] ppc queue Cédric Le Goater
2022-03-21 6:44 ` [PULL 1/3] ppc64: Avoid pt_regs struct definition Cédric Le Goater
2022-03-21 6:44 ` [PULL 2/3] target/ppc: Replicate double->int32 result for some vector insns Cédric Le Goater
@ 2022-03-21 6:44 ` Cédric Le Goater
2022-03-21 15:26 ` [PULL 0/3] ppc queue Peter Maydell
3 siblings, 0 replies; 5+ messages in thread
From: Cédric Le Goater @ 2022-03-21 6:44 UTC (permalink / raw)
To: qemu-ppc, qemu-devel; +Cc: Peter Maydell, Lucas Coutinho, Cédric Le Goater
From: Lucas Coutinho <lucas.coutinho@eldorado.org.br>
Power ISA v3.1 formalizes the previously undefined result in
words 1 and 3 to be a copy of the result in words 0 and 2.
This affects: xvcvsxdsp, xvcvuxdsp, xvcvdpsp.
And the previously undefined result in word 1 to be a copy of
the result in word 0.
This affects: xscvdpsp.
Signed-off-by: Lucas Coutinho <lucas.coutinho@eldorado.org.br>
Message-Id: <20220316200427.3410437-1-lucas.coutinho@eldorado.org.br>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/fpu_helper.c | 48 +++++++++++++++++++++++++++++++++++++----
1 file changed, 44 insertions(+), 4 deletions(-)
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
index 564f2ec35374..7e8be99cc0c8 100644
--- a/target/ppc/fpu_helper.c
+++ b/target/ppc/fpu_helper.c
@@ -2691,11 +2691,35 @@ void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) \
do_float_check_status(env, GETPC()); \
}
-VSX_CVT_FP_TO_FP(xscvdpsp, 1, float64, float32, VsrD(0), VsrW(0), 1)
VSX_CVT_FP_TO_FP(xscvspdp, 1, float32, float64, VsrW(0), VsrD(0), 1)
-VSX_CVT_FP_TO_FP(xvcvdpsp, 2, float64, float32, VsrD(i), VsrW(2 * i), 0)
VSX_CVT_FP_TO_FP(xvcvspdp, 2, float32, float64, VsrW(2 * i), VsrD(i), 0)
+#define VSX_CVT_FP_TO_FP2(op, nels, stp, ttp, sfprf) \
+void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) \
+{ \
+ ppc_vsr_t t = { }; \
+ int i; \
+ \
+ for (i = 0; i < nels; i++) { \
+ t.VsrW(2 * i) = stp##_to_##ttp(xb->VsrD(i), &env->fp_status); \
+ if (unlikely(stp##_is_signaling_nan(xb->VsrD(i), \
+ &env->fp_status))) { \
+ float_invalid_op_vxsnan(env, GETPC()); \
+ t.VsrW(2 * i) = ttp##_snan_to_qnan(t.VsrW(2 * i)); \
+ } \
+ if (sfprf) { \
+ helper_compute_fprf_##ttp(env, t.VsrW(2 * i)); \
+ } \
+ t.VsrW(2 * i + 1) = t.VsrW(2 * i); \
+ } \
+ \
+ *xt = t; \
+ do_float_check_status(env, GETPC()); \
+}
+
+VSX_CVT_FP_TO_FP2(xvcvdpsp, 2, float64, float32, 0)
+VSX_CVT_FP_TO_FP2(xscvdpsp, 1, float64, float32, 1)
+
/*
* VSX_CVT_FP_TO_FP_VECTOR - VSX floating point/floating point conversion
* op - instruction mnemonic
@@ -3013,11 +3037,27 @@ VSX_CVT_INT_TO_FP(xvcvsxddp, 2, int64, float64, VsrD(i), VsrD(i), 0, 0)
VSX_CVT_INT_TO_FP(xvcvuxddp, 2, uint64, float64, VsrD(i), VsrD(i), 0, 0)
VSX_CVT_INT_TO_FP(xvcvsxwdp, 2, int32, float64, VsrW(2 * i), VsrD(i), 0, 0)
VSX_CVT_INT_TO_FP(xvcvuxwdp, 2, uint64, float64, VsrW(2 * i), VsrD(i), 0, 0)
-VSX_CVT_INT_TO_FP(xvcvsxdsp, 2, int64, float32, VsrD(i), VsrW(2 * i), 0, 0)
-VSX_CVT_INT_TO_FP(xvcvuxdsp, 2, uint64, float32, VsrD(i), VsrW(2 * i), 0, 0)
VSX_CVT_INT_TO_FP(xvcvsxwsp, 4, int32, float32, VsrW(i), VsrW(i), 0, 0)
VSX_CVT_INT_TO_FP(xvcvuxwsp, 4, uint32, float32, VsrW(i), VsrW(i), 0, 0)
+#define VSX_CVT_INT_TO_FP2(op, stp, ttp) \
+void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, ppc_vsr_t *xb) \
+{ \
+ ppc_vsr_t t = { }; \
+ int i; \
+ \
+ for (i = 0; i < 2; i++) { \
+ t.VsrW(2 * i) = stp##_to_##ttp(xb->VsrD(i), &env->fp_status); \
+ t.VsrW(2 * i + 1) = t.VsrW(2 * i); \
+ } \
+ \
+ *xt = t; \
+ do_float_check_status(env, GETPC()); \
+}
+
+VSX_CVT_INT_TO_FP2(xvcvsxdsp, int64, float32)
+VSX_CVT_INT_TO_FP2(xvcvuxdsp, uint64, float32)
+
/*
* VSX_CVT_INT_TO_FP_VECTOR - VSX integer to floating point conversion
* op - instruction mnemonic
--
2.34.1
^ permalink raw reply related [flat|nested] 5+ messages in thread* Re: [PULL 0/3] ppc queue
2022-03-21 6:44 [PULL 0/3] ppc queue Cédric Le Goater
` (2 preceding siblings ...)
2022-03-21 6:44 ` [PULL 3/3] target/ppc: Replicate Double->Single-Precision result Cédric Le Goater
@ 2022-03-21 15:26 ` Peter Maydell
3 siblings, 0 replies; 5+ messages in thread
From: Peter Maydell @ 2022-03-21 15:26 UTC (permalink / raw)
To: Cédric Le Goater; +Cc: qemu-ppc, qemu-devel
On Mon, 21 Mar 2022 at 06:45, Cédric Le Goater <clg@kaod.org> wrote:
>
> The following changes since commit 2058fdbe81e2985c226a026851dd26b146d3395c:
>
> Merge tag 'fixes-20220318-pull-request' of git://git.kraxel.org/qemu into staging (2022-03-19 11:28:54 +0000)
>
> are available in the Git repository at:
>
> https://github.com/legoater/qemu/ tags/pull-ppc-20220321
>
> for you to fetch changes up to 3515553bf625ad48aa90210379c4f387c2596093:
>
> target/ppc: Replicate Double->Single-Precision result (2022-03-20 23:35:27 +0100)
>
> ----------------------------------------------------------------
> ppc-7.0 queue :
>
> * ISA v3.1 vector instruction fixes
> * Compilation fix regarding 'struct pt_regs' definition
>
> ----------------------------------------------------------------
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/7.0
for any user-visible changes.
-- PMM
^ permalink raw reply [flat|nested] 5+ messages in thread