* [PATCH 1/5] ppc/pnv: Fix PSI IRQ definition
2022-03-23 7:28 [PATCH 0/5] ppc/pnv: Introduce GPIO lines to drive the PSIHB device Cédric Le Goater
@ 2022-03-23 7:28 ` Cédric Le Goater
2022-03-23 7:28 ` [PATCH 2/5] ppc/pnv: Remove PnvLpcController::psi link Cédric Le Goater
` (5 subsequent siblings)
6 siblings, 0 replies; 9+ messages in thread
From: Cédric Le Goater @ 2022-03-23 7:28 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Frederic Barrat, Daniel Henrique Barboza, Cédric Le Goater
On HW, the PSI and FSP interrupt levels are muxed under the same
interrupt number. For coding reasons, an extra IRQ number was
introduced to index register values in an array. It increased the
count of IRQs which do not fit in the PSI IRQ range anymore.
The PSI and FSP interrupts should be modeled with an extra level of
GPIO lines but since QEMU does not support them, simply drop the extra
number to stay within the IRQ range.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
include/hw/ppc/pnv_psi.h | 3 +--
hw/ppc/pnv_psi.c | 9 +++------
2 files changed, 4 insertions(+), 8 deletions(-)
diff --git a/include/hw/ppc/pnv_psi.h b/include/hw/ppc/pnv_psi.h
index eb841b34a1f7..6d9f8ce7c031 100644
--- a/include/hw/ppc/pnv_psi.h
+++ b/include/hw/ppc/pnv_psi.h
@@ -1,7 +1,7 @@
/*
* QEMU PowerPC PowerNV Processor Service Interface (PSI) model
*
- * Copyright (c) 2015-2017, IBM Corporation.
+ * Copyright (c) 2015-2022, IBM Corporation.
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
@@ -85,7 +85,6 @@ struct PnvPsiClass {
/* The PSI and FSP interrupts are muxed on the same IRQ number */
typedef enum PnvPsiIrq {
- PSIHB_IRQ_PSI, /* internal use only */
PSIHB_IRQ_FSP, /* internal use only */
PSIHB_IRQ_OCC,
PSIHB_IRQ_FSI,
diff --git a/hw/ppc/pnv_psi.c b/hw/ppc/pnv_psi.c
index 466fb7979887..c588a506c7cc 100644
--- a/hw/ppc/pnv_psi.c
+++ b/hw/ppc/pnv_psi.c
@@ -184,8 +184,7 @@ static void pnv_psi_set_irsn(PnvPsi *psi, uint64_t val)
/*
* FSP and PSI interrupts are muxed under the same number.
*/
-static const uint32_t xivr_regs[] = {
- [PSIHB_IRQ_PSI] = PSIHB_XSCOM_XIVR_FSP,
+static const uint32_t xivr_regs[PSI_NUM_INTERRUPTS] = {
[PSIHB_IRQ_FSP] = PSIHB_XSCOM_XIVR_FSP,
[PSIHB_IRQ_OCC] = PSIHB_XSCOM_XIVR_OCC,
[PSIHB_IRQ_FSI] = PSIHB_XSCOM_XIVR_FSI,
@@ -194,8 +193,7 @@ static const uint32_t xivr_regs[] = {
[PSIHB_IRQ_EXTERNAL] = PSIHB_XSCOM_XIVR_EXT,
};
-static const uint32_t stat_regs[] = {
- [PSIHB_IRQ_PSI] = PSIHB_XSCOM_CR,
+static const uint32_t stat_regs[PSI_NUM_INTERRUPTS] = {
[PSIHB_IRQ_FSP] = PSIHB_XSCOM_CR,
[PSIHB_IRQ_OCC] = PSIHB_XSCOM_IRQ_STAT,
[PSIHB_IRQ_FSI] = PSIHB_XSCOM_IRQ_STAT,
@@ -204,8 +202,7 @@ static const uint32_t stat_regs[] = {
[PSIHB_IRQ_EXTERNAL] = PSIHB_XSCOM_IRQ_STAT,
};
-static const uint64_t stat_bits[] = {
- [PSIHB_IRQ_PSI] = PSIHB_CR_PSI_IRQ,
+static const uint64_t stat_bits[PSI_NUM_INTERRUPTS] = {
[PSIHB_IRQ_FSP] = PSIHB_CR_FSP_IRQ,
[PSIHB_IRQ_OCC] = PSIHB_IRQ_STAT_OCC,
[PSIHB_IRQ_FSI] = PSIHB_IRQ_STAT_FSI,
--
2.34.1
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH 2/5] ppc/pnv: Remove PnvLpcController::psi link
2022-03-23 7:28 [PATCH 0/5] ppc/pnv: Introduce GPIO lines to drive the PSIHB device Cédric Le Goater
2022-03-23 7:28 ` [PATCH 1/5] ppc/pnv: Fix PSI IRQ definition Cédric Le Goater
@ 2022-03-23 7:28 ` Cédric Le Goater
2022-03-23 7:28 ` [PATCH 3/5] ppc/pnv: Remove PnvOCC::psi link Cédric Le Goater
` (4 subsequent siblings)
6 siblings, 0 replies; 9+ messages in thread
From: Cédric Le Goater @ 2022-03-23 7:28 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Frederic Barrat, Daniel Henrique Barboza, Cédric Le Goater
Create an anonymous output GPIO line to connect the LPC device with
the PSIHB device and raise the appropriate PSI IRQ line depending on
the processor model.
A temporary __pnv_psi_irq_set() routine is introduced to handle the
transition. It will be removed when all devices raising PSI interrupts
are converted to use GPIOs.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
include/hw/ppc/pnv_lpc.h | 8 ++------
hw/ppc/pnv.c | 18 ++++++++++++------
hw/ppc/pnv_lpc.c | 19 ++++---------------
hw/ppc/pnv_psi.c | 10 ++++++++++
4 files changed, 28 insertions(+), 27 deletions(-)
diff --git a/include/hw/ppc/pnv_lpc.h b/include/hw/ppc/pnv_lpc.h
index e893e763dd5f..8a8d1a3d4209 100644
--- a/include/hw/ppc/pnv_lpc.h
+++ b/include/hw/ppc/pnv_lpc.h
@@ -1,7 +1,7 @@
/*
* QEMU PowerPC PowerNV LPC controller
*
- * Copyright (c) 2016, IBM Corporation.
+ * Copyright (c) 2016-2022, IBM Corporation.
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
@@ -20,7 +20,6 @@
#ifndef PPC_PNV_LPC_H
#define PPC_PNV_LPC_H
-#include "hw/ppc/pnv_psi.h"
#include "qom/object.h"
#define TYPE_PNV_LPC "pnv-lpc"
@@ -84,15 +83,12 @@ struct PnvLpcController {
MemoryRegion xscom_regs;
/* PSI to generate interrupts */
- PnvPsi *psi;
+ qemu_irq psi_irq;
};
-
struct PnvLpcClass {
DeviceClass parent_class;
- int psi_irq;
-
DeviceRealize parent_realize;
};
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 00f57c9678e6..8082462bdfb1 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -615,24 +615,36 @@ static void pnv_reset(MachineState *machine)
static ISABus *pnv_chip_power8_isa_create(PnvChip *chip, Error **errp)
{
Pnv8Chip *chip8 = PNV8_CHIP(chip);
+ qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip8->psi), PSIHB_IRQ_EXTERNAL);
+
+ qdev_connect_gpio_out(DEVICE(&chip8->lpc), 0, irq);
return pnv_lpc_isa_create(&chip8->lpc, true, errp);
}
static ISABus *pnv_chip_power8nvl_isa_create(PnvChip *chip, Error **errp)
{
Pnv8Chip *chip8 = PNV8_CHIP(chip);
+ qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip8->psi), PSIHB_IRQ_LPC_I2C);
+
+ qdev_connect_gpio_out(DEVICE(&chip8->lpc), 0, irq);
return pnv_lpc_isa_create(&chip8->lpc, false, errp);
}
static ISABus *pnv_chip_power9_isa_create(PnvChip *chip, Error **errp)
{
Pnv9Chip *chip9 = PNV9_CHIP(chip);
+ qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip9->psi), PSIHB9_IRQ_LPCHC);
+
+ qdev_connect_gpio_out(DEVICE(&chip9->lpc), 0, irq);
return pnv_lpc_isa_create(&chip9->lpc, false, errp);
}
static ISABus *pnv_chip_power10_isa_create(PnvChip *chip, Error **errp)
{
Pnv10Chip *chip10 = PNV10_CHIP(chip);
+ qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip10->psi), PSIHB9_IRQ_LPCHC);
+
+ qdev_connect_gpio_out(DEVICE(&chip10->lpc), 0, irq);
return pnv_lpc_isa_create(&chip10->lpc, false, errp);
}
@@ -1223,8 +1235,6 @@ static void pnv_chip_power8_realize(DeviceState *dev, Error **errp)
&PNV_PSI(psi8)->xscom_regs);
/* Create LPC controller */
- object_property_set_link(OBJECT(&chip8->lpc), "psi", OBJECT(&chip8->psi),
- &error_abort);
qdev_realize(DEVICE(&chip8->lpc), NULL, &error_fatal);
pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, &chip8->lpc.xscom_regs);
@@ -1508,8 +1518,6 @@ static void pnv_chip_power9_realize(DeviceState *dev, Error **errp)
&PNV_PSI(psi9)->xscom_regs);
/* LPC */
- object_property_set_link(OBJECT(&chip9->lpc), "psi", OBJECT(&chip9->psi),
- &error_abort);
if (!qdev_realize(DEVICE(&chip9->lpc), NULL, errp)) {
return;
}
@@ -1713,8 +1721,6 @@ static void pnv_chip_power10_realize(DeviceState *dev, Error **errp)
&PNV_PSI(&chip10->psi)->xscom_regs);
/* LPC */
- object_property_set_link(OBJECT(&chip10->lpc), "psi",
- OBJECT(&chip10->psi), &error_abort);
if (!qdev_realize(DEVICE(&chip10->lpc), NULL, errp)) {
return;
}
diff --git a/hw/ppc/pnv_lpc.c b/hw/ppc/pnv_lpc.c
index bcbca3db9743..ee890e7ab419 100644
--- a/hw/ppc/pnv_lpc.c
+++ b/hw/ppc/pnv_lpc.c
@@ -422,7 +422,6 @@ static const MemoryRegionOps pnv_lpc_mmio_ops = {
static void pnv_lpc_eval_irqs(PnvLpcController *lpc)
{
bool lpc_to_opb_irq = false;
- PnvLpcClass *plc = PNV_LPC_GET_CLASS(lpc);
/* Update LPC controller to OPB line */
if (lpc->lpc_hc_irqser_ctrl & LPC_HC_IRQSER_EN) {
@@ -445,7 +444,7 @@ static void pnv_lpc_eval_irqs(PnvLpcController *lpc)
lpc->opb_irq_stat |= lpc->opb_irq_input & lpc->opb_irq_mask;
/* Reflect the interrupt */
- pnv_psi_irq_set(lpc->psi, plc->psi_irq, lpc->opb_irq_stat != 0);
+ qemu_set_irq(lpc->psi_irq, lpc->opb_irq_stat != 0);
}
static uint64_t lpc_hc_read(void *opaque, hwaddr addr, unsigned size)
@@ -637,8 +636,6 @@ static void pnv_lpc_power8_class_init(ObjectClass *klass, void *data)
xdc->dt_xscom = pnv_lpc_dt_xscom;
- plc->psi_irq = PSIHB_IRQ_LPC_I2C;
-
device_class_set_parent_realize(dc, pnv_lpc_power8_realize,
&plc->parent_realize);
}
@@ -677,8 +674,6 @@ static void pnv_lpc_power9_class_init(ObjectClass *klass, void *data)
dc->desc = "PowerNV LPC Controller POWER9";
- plc->psi_irq = PSIHB9_IRQ_LPCHC;
-
device_class_set_parent_realize(dc, pnv_lpc_power9_realize,
&plc->parent_realize);
}
@@ -706,8 +701,6 @@ static void pnv_lpc_realize(DeviceState *dev, Error **errp)
{
PnvLpcController *lpc = PNV_LPC(dev);
- assert(lpc->psi);
-
/* Reg inits */
lpc->lpc_hc_fw_rd_acc_size = LPC_HC_FW_RD_4B;
@@ -746,12 +739,9 @@ static void pnv_lpc_realize(DeviceState *dev, Error **errp)
"lpc-hc", LPC_HC_REGS_OPB_SIZE);
memory_region_add_subregion(&lpc->opb_mr, LPC_HC_REGS_OPB_ADDR,
&lpc->lpc_hc_regs);
-}
-static Property pnv_lpc_properties[] = {
- DEFINE_PROP_LINK("psi", PnvLpcController, psi, TYPE_PNV_PSI, PnvPsi *),
- DEFINE_PROP_END_OF_LIST(),
-};
+ qdev_init_gpio_out(DEVICE(dev), &lpc->psi_irq, 1);
+}
static void pnv_lpc_class_init(ObjectClass *klass, void *data)
{
@@ -759,7 +749,6 @@ static void pnv_lpc_class_init(ObjectClass *klass, void *data)
dc->realize = pnv_lpc_realize;
dc->desc = "PowerNV LPC Controller";
- device_class_set_props(dc, pnv_lpc_properties);
dc->user_creatable = false;
}
@@ -803,7 +792,7 @@ static void pnv_lpc_isa_irq_handler_cpld(void *opaque, int n, int level)
}
if (pnv->cpld_irqstate != old_state) {
- pnv_psi_irq_set(lpc->psi, PSIHB_IRQ_EXTERNAL, pnv->cpld_irqstate != 0);
+ qemu_set_irq(lpc->psi_irq, pnv->cpld_irqstate != 0);
}
}
diff --git a/hw/ppc/pnv_psi.c b/hw/ppc/pnv_psi.c
index c588a506c7cc..8b6298d4bd96 100644
--- a/hw/ppc/pnv_psi.c
+++ b/hw/ppc/pnv_psi.c
@@ -216,6 +216,12 @@ void pnv_psi_irq_set(PnvPsi *psi, int irq, bool state)
PNV_PSI_GET_CLASS(psi)->irq_set(psi, irq, state);
}
+static void __pnv_psi_irq_set(void *opaque, int irq, int state)
+{
+ PnvPsi *psi = (PnvPsi *) opaque;
+ PNV_PSI_GET_CLASS(psi)->irq_set(psi, irq, state);
+}
+
static void pnv_psi_power8_irq_set(PnvPsi *psi, int irq, bool state)
{
uint32_t xivr_reg;
@@ -512,6 +518,8 @@ static void pnv_psi_power8_realize(DeviceState *dev, Error **errp)
ics_set_irq_type(ics, i, true);
}
+ qdev_init_gpio_in(dev, __pnv_psi_irq_set, ics->nr_irqs);
+
psi->qirqs = qemu_allocate_irqs(ics_set_irq, ics, ics->nr_irqs);
/* XSCOM region for PSI registers */
@@ -873,6 +881,8 @@ static void pnv_psi_power9_realize(DeviceState *dev, Error **errp)
psi->qirqs = qemu_allocate_irqs(xive_source_set_irq, xsrc, xsrc->nr_irqs);
+ qdev_init_gpio_in(dev, __pnv_psi_irq_set, xsrc->nr_irqs);
+
/* XSCOM region for PSI registers */
pnv_xscom_region_init(&psi->xscom_regs, OBJECT(dev), &pnv_psi_p9_xscom_ops,
psi, "xscom-psi", PNV9_XSCOM_PSIHB_SIZE);
--
2.34.1
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH 3/5] ppc/pnv: Remove PnvOCC::psi link
2022-03-23 7:28 [PATCH 0/5] ppc/pnv: Introduce GPIO lines to drive the PSIHB device Cédric Le Goater
2022-03-23 7:28 ` [PATCH 1/5] ppc/pnv: Fix PSI IRQ definition Cédric Le Goater
2022-03-23 7:28 ` [PATCH 2/5] ppc/pnv: Remove PnvLpcController::psi link Cédric Le Goater
@ 2022-03-23 7:28 ` Cédric Le Goater
2022-03-23 7:28 ` [PATCH 4/5] ppc/pnv: Remove PnvPsiClas::irq_set Cédric Le Goater
` (3 subsequent siblings)
6 siblings, 0 replies; 9+ messages in thread
From: Cédric Le Goater @ 2022-03-23 7:28 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Frederic Barrat, Daniel Henrique Barboza, Cédric Le Goater
Use an anonymous output GPIO line to connect the OCC device with the
PSIHB device and raise the appropriate PSI IRQ line depending on the
processor model.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
include/hw/ppc/pnv_occ.h | 7 ++-----
hw/ppc/pnv.c | 12 ++++++------
hw/ppc/pnv_occ.c | 16 ++++------------
3 files changed, 12 insertions(+), 23 deletions(-)
diff --git a/include/hw/ppc/pnv_occ.h b/include/hw/ppc/pnv_occ.h
index f982ba002481..90a81dae2b8d 100644
--- a/include/hw/ppc/pnv_occ.h
+++ b/include/hw/ppc/pnv_occ.h
@@ -1,7 +1,7 @@
/*
* QEMU PowerPC PowerNV Emulation of a few OCC related registers
*
- * Copyright (c) 2015-2017, IBM Corporation.
+ * Copyright (c) 2015-2022, IBM Corporation.
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
@@ -20,7 +20,6 @@
#ifndef PPC_PNV_OCC_H
#define PPC_PNV_OCC_H
-#include "hw/ppc/pnv_psi.h"
#include "qom/object.h"
#define TYPE_PNV_OCC "pnv-occ"
@@ -44,19 +43,17 @@ struct PnvOCC {
/* OCC Misc interrupt */
uint64_t occmisc;
- PnvPsi *psi;
+ qemu_irq psi_irq;
MemoryRegion xscom_regs;
MemoryRegion sram_regs;
};
-
struct PnvOCCClass {
DeviceClass parent_class;
int xscom_size;
const MemoryRegionOps *xscom_ops;
- int psi_irq;
};
#define PNV_OCC_SENSOR_DATA_BLOCK_BASE(i) \
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 8082462bdfb1..0e3cff8aa47b 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -1254,12 +1254,12 @@ static void pnv_chip_power8_realize(DeviceState *dev, Error **errp)
}
/* Create the simplified OCC model */
- object_property_set_link(OBJECT(&chip8->occ), "psi", OBJECT(&chip8->psi),
- &error_abort);
if (!qdev_realize(DEVICE(&chip8->occ), NULL, errp)) {
return;
}
pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip8->occ.xscom_regs);
+ qdev_connect_gpio_out(DEVICE(&chip8->occ), 0,
+ qdev_get_gpio_in(DEVICE(&chip8->psi), PSIHB_IRQ_OCC));
/* OCC SRAM model */
memory_region_add_subregion(get_system_memory(), PNV_OCC_SENSOR_BASE(chip),
@@ -1529,12 +1529,12 @@ static void pnv_chip_power9_realize(DeviceState *dev, Error **errp)
(uint64_t) PNV9_LPCM_BASE(chip));
/* Create the simplified OCC model */
- object_property_set_link(OBJECT(&chip9->occ), "psi", OBJECT(&chip9->psi),
- &error_abort);
if (!qdev_realize(DEVICE(&chip9->occ), NULL, errp)) {
return;
}
pnv_xscom_add_subregion(chip, PNV9_XSCOM_OCC_BASE, &chip9->occ.xscom_regs);
+ qdev_connect_gpio_out(DEVICE(&chip9->occ), 0, qdev_get_gpio_in(
+ DEVICE(&chip9->psi), PSIHB9_IRQ_OCC));
/* OCC SRAM model */
memory_region_add_subregion(get_system_memory(), PNV9_OCC_SENSOR_BASE(chip),
@@ -1732,13 +1732,13 @@ static void pnv_chip_power10_realize(DeviceState *dev, Error **errp)
(uint64_t) PNV10_LPCM_BASE(chip));
/* Create the simplified OCC model */
- object_property_set_link(OBJECT(&chip10->occ), "psi", OBJECT(&chip10->psi),
- &error_abort);
if (!qdev_realize(DEVICE(&chip10->occ), NULL, errp)) {
return;
}
pnv_xscom_add_subregion(chip, PNV10_XSCOM_OCC_BASE,
&chip10->occ.xscom_regs);
+ qdev_connect_gpio_out(DEVICE(&chip10->occ), 0, qdev_get_gpio_in(
+ DEVICE(&chip10->psi), PSIHB9_IRQ_OCC));
/* OCC SRAM model */
memory_region_add_subregion(get_system_memory(),
diff --git a/hw/ppc/pnv_occ.c b/hw/ppc/pnv_occ.c
index 4ed66f5e1fcc..9fa6d91d3122 100644
--- a/hw/ppc/pnv_occ.c
+++ b/hw/ppc/pnv_occ.c
@@ -21,6 +21,7 @@
#include "qapi/error.h"
#include "qemu/log.h"
#include "qemu/module.h"
+#include "hw/irq.h"
#include "hw/qdev-properties.h"
#include "hw/ppc/pnv.h"
#include "hw/ppc/pnv_xscom.h"
@@ -51,13 +52,12 @@
static void pnv_occ_set_misc(PnvOCC *occ, uint64_t val)
{
bool irq_state;
- PnvOCCClass *poc = PNV_OCC_GET_CLASS(occ);
val &= 0xffff000000000000ull;
occ->occmisc = val;
irq_state = !!(val >> 63);
- pnv_psi_irq_set(occ->psi, poc->psi_irq, irq_state);
+ qemu_set_irq(occ->psi_irq, irq_state);
}
static uint64_t pnv_occ_power8_xscom_read(void *opaque, hwaddr addr,
@@ -168,7 +168,6 @@ static void pnv_occ_power8_class_init(ObjectClass *klass, void *data)
poc->xscom_size = PNV_XSCOM_OCC_SIZE;
poc->xscom_ops = &pnv_occ_power8_xscom_ops;
- poc->psi_irq = PSIHB_IRQ_OCC;
}
static const TypeInfo pnv_occ_power8_type_info = {
@@ -241,7 +240,6 @@ static void pnv_occ_power9_class_init(ObjectClass *klass, void *data)
dc->desc = "PowerNV OCC Controller (POWER9)";
poc->xscom_size = PNV9_XSCOM_OCC_SIZE;
poc->xscom_ops = &pnv_occ_power9_xscom_ops;
- poc->psi_irq = PSIHB9_IRQ_OCC;
}
static const TypeInfo pnv_occ_power9_type_info = {
@@ -269,8 +267,6 @@ static void pnv_occ_realize(DeviceState *dev, Error **errp)
PnvOCC *occ = PNV_OCC(dev);
PnvOCCClass *poc = PNV_OCC_GET_CLASS(occ);
- assert(occ->psi);
-
occ->occmisc = 0;
/* XScom region for OCC registers */
@@ -281,12 +277,9 @@ static void pnv_occ_realize(DeviceState *dev, Error **errp)
memory_region_init_io(&occ->sram_regs, OBJECT(dev), &pnv_occ_sram_ops,
occ, "occ-common-area",
PNV_OCC_SENSOR_DATA_BLOCK_SIZE);
-}
-static Property pnv_occ_properties[] = {
- DEFINE_PROP_LINK("psi", PnvOCC, psi, TYPE_PNV_PSI, PnvPsi *),
- DEFINE_PROP_END_OF_LIST(),
-};
+ qdev_init_gpio_out(DEVICE(dev), &occ->psi_irq, 1);
+}
static void pnv_occ_class_init(ObjectClass *klass, void *data)
{
@@ -294,7 +287,6 @@ static void pnv_occ_class_init(ObjectClass *klass, void *data)
dc->realize = pnv_occ_realize;
dc->desc = "PowerNV OCC Controller";
- device_class_set_props(dc, pnv_occ_properties);
dc->user_creatable = false;
}
--
2.34.1
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH 4/5] ppc/pnv: Remove PnvPsiClas::irq_set
2022-03-23 7:28 [PATCH 0/5] ppc/pnv: Introduce GPIO lines to drive the PSIHB device Cédric Le Goater
` (2 preceding siblings ...)
2022-03-23 7:28 ` [PATCH 3/5] ppc/pnv: Remove PnvOCC::psi link Cédric Le Goater
@ 2022-03-23 7:28 ` Cédric Le Goater
2022-03-23 7:28 ` [PATCH 5/5] ppc/pnv: Remove usless checks in set_irq handlers Cédric Le Goater
` (2 subsequent siblings)
6 siblings, 0 replies; 9+ messages in thread
From: Cédric Le Goater @ 2022-03-23 7:28 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Frederic Barrat, Daniel Henrique Barboza, Cédric Le Goater
All devices raising PSI interrupts are now converted to use GPIO lines
and the pnv_psi_irq_set() routines have become useless. Drop them.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
include/hw/ppc/pnv_psi.h | 4 ----
hw/ppc/pnv_psi.c | 23 ++++++-----------------
2 files changed, 6 insertions(+), 21 deletions(-)
diff --git a/include/hw/ppc/pnv_psi.h b/include/hw/ppc/pnv_psi.h
index 6d9f8ce7c031..8253469b8fee 100644
--- a/include/hw/ppc/pnv_psi.h
+++ b/include/hw/ppc/pnv_psi.h
@@ -79,8 +79,6 @@ struct PnvPsiClass {
uint64_t bar_mask;
const char *compat;
int compat_size;
-
- void (*irq_set)(PnvPsi *psi, int, bool state);
};
/* The PSI and FSP interrupts are muxed on the same IRQ number */
@@ -95,8 +93,6 @@ typedef enum PnvPsiIrq {
#define PSI_NUM_INTERRUPTS 6
-void pnv_psi_irq_set(PnvPsi *psi, int irq, bool state);
-
/* P9 PSI Interrupts */
#define PSIHB9_IRQ_PSI 0
#define PSIHB9_IRQ_OCC 1
diff --git a/hw/ppc/pnv_psi.c b/hw/ppc/pnv_psi.c
index 8b6298d4bd96..950ecca40573 100644
--- a/hw/ppc/pnv_psi.c
+++ b/hw/ppc/pnv_psi.c
@@ -211,19 +211,9 @@ static const uint64_t stat_bits[PSI_NUM_INTERRUPTS] = {
[PSIHB_IRQ_EXTERNAL] = PSIHB_IRQ_STAT_EXT,
};
-void pnv_psi_irq_set(PnvPsi *psi, int irq, bool state)
-{
- PNV_PSI_GET_CLASS(psi)->irq_set(psi, irq, state);
-}
-
-static void __pnv_psi_irq_set(void *opaque, int irq, int state)
-{
- PnvPsi *psi = (PnvPsi *) opaque;
- PNV_PSI_GET_CLASS(psi)->irq_set(psi, irq, state);
-}
-
-static void pnv_psi_power8_irq_set(PnvPsi *psi, int irq, bool state)
+static void pnv_psi_power8_set_irq(void *opaque, int irq, int state)
{
+ PnvPsi *psi = opaque;
uint32_t xivr_reg;
uint32_t stat_reg;
uint32_t src;
@@ -518,7 +508,7 @@ static void pnv_psi_power8_realize(DeviceState *dev, Error **errp)
ics_set_irq_type(ics, i, true);
}
- qdev_init_gpio_in(dev, __pnv_psi_irq_set, ics->nr_irqs);
+ qdev_init_gpio_in(dev, pnv_psi_power8_set_irq, ics->nr_irqs);
psi->qirqs = qemu_allocate_irqs(ics_set_irq, ics, ics->nr_irqs);
@@ -581,7 +571,6 @@ static void pnv_psi_power8_class_init(ObjectClass *klass, void *data)
ppc->xscom_pcba = PNV_XSCOM_PSIHB_BASE;
ppc->xscom_size = PNV_XSCOM_PSIHB_SIZE;
ppc->bar_mask = PSIHB_BAR_MASK;
- ppc->irq_set = pnv_psi_power8_irq_set;
ppc->compat = compat;
ppc->compat_size = sizeof(compat);
}
@@ -819,8 +808,9 @@ static const MemoryRegionOps pnv_psi_p9_xscom_ops = {
}
};
-static void pnv_psi_power9_irq_set(PnvPsi *psi, int irq, bool state)
+static void pnv_psi_power9_set_irq(void *opaque, int irq, int state)
{
+ PnvPsi *psi = opaque;
uint64_t irq_method = psi->regs[PSIHB_REG(PSIHB9_INTERRUPT_CONTROL)];
if (irq > PSIHB9_NUM_IRQS) {
@@ -881,7 +871,7 @@ static void pnv_psi_power9_realize(DeviceState *dev, Error **errp)
psi->qirqs = qemu_allocate_irqs(xive_source_set_irq, xsrc, xsrc->nr_irqs);
- qdev_init_gpio_in(dev, __pnv_psi_irq_set, xsrc->nr_irqs);
+ qdev_init_gpio_in(dev, pnv_psi_power9_set_irq, xsrc->nr_irqs);
/* XSCOM region for PSI registers */
pnv_xscom_region_init(&psi->xscom_regs, OBJECT(dev), &pnv_psi_p9_xscom_ops,
@@ -908,7 +898,6 @@ static void pnv_psi_power9_class_init(ObjectClass *klass, void *data)
ppc->xscom_pcba = PNV9_XSCOM_PSIHB_BASE;
ppc->xscom_size = PNV9_XSCOM_PSIHB_SIZE;
ppc->bar_mask = PSIHB9_BAR_MASK;
- ppc->irq_set = pnv_psi_power9_irq_set;
ppc->compat = compat;
ppc->compat_size = sizeof(compat);
--
2.34.1
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH 5/5] ppc/pnv: Remove usless checks in set_irq handlers
2022-03-23 7:28 [PATCH 0/5] ppc/pnv: Introduce GPIO lines to drive the PSIHB device Cédric Le Goater
` (3 preceding siblings ...)
2022-03-23 7:28 ` [PATCH 4/5] ppc/pnv: Remove PnvPsiClas::irq_set Cédric Le Goater
@ 2022-03-23 7:28 ` Cédric Le Goater
2022-03-24 18:02 ` Daniel Henrique Barboza
2022-03-24 18:02 ` [PATCH 0/5] ppc/pnv: Introduce GPIO lines to drive the PSIHB device Daniel Henrique Barboza
2022-04-20 19:11 ` Daniel Henrique Barboza
6 siblings, 1 reply; 9+ messages in thread
From: Cédric Le Goater @ 2022-03-23 7:28 UTC (permalink / raw)
To: qemu-ppc, qemu-devel
Cc: Frederic Barrat, Daniel Henrique Barboza, Cédric Le Goater
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
hw/ppc/pnv_psi.c | 10 ----------
1 file changed, 10 deletions(-)
diff --git a/hw/ppc/pnv_psi.c b/hw/ppc/pnv_psi.c
index 950ecca40573..98045ed3d249 100644
--- a/hw/ppc/pnv_psi.c
+++ b/hw/ppc/pnv_psi.c
@@ -219,11 +219,6 @@ static void pnv_psi_power8_set_irq(void *opaque, int irq, int state)
uint32_t src;
bool masked;
- if (irq > PSIHB_IRQ_EXTERNAL) {
- qemu_log_mask(LOG_GUEST_ERROR, "PSI: Unsupported irq %d\n", irq);
- return;
- }
-
xivr_reg = xivr_regs[irq];
stat_reg = stat_regs[irq];
@@ -813,11 +808,6 @@ static void pnv_psi_power9_set_irq(void *opaque, int irq, int state)
PnvPsi *psi = opaque;
uint64_t irq_method = psi->regs[PSIHB_REG(PSIHB9_INTERRUPT_CONTROL)];
- if (irq > PSIHB9_NUM_IRQS) {
- qemu_log_mask(LOG_GUEST_ERROR, "PSI: Unsupported irq %d\n", irq);
- return;
- }
-
if (irq_method & PSIHB9_IRQ_METHOD) {
qemu_log_mask(LOG_GUEST_ERROR, "PSI: LSI IRQ method no supported\n");
return;
--
2.34.1
^ permalink raw reply related [flat|nested] 9+ messages in thread* Re: [PATCH 5/5] ppc/pnv: Remove usless checks in set_irq handlers
2022-03-23 7:28 ` [PATCH 5/5] ppc/pnv: Remove usless checks in set_irq handlers Cédric Le Goater
@ 2022-03-24 18:02 ` Daniel Henrique Barboza
0 siblings, 0 replies; 9+ messages in thread
From: Daniel Henrique Barboza @ 2022-03-24 18:02 UTC (permalink / raw)
To: Cédric Le Goater, qemu-ppc, qemu-devel; +Cc: Frederic Barrat
Typo in the commit title: s/usless/useless
On 3/23/22 04:28, Cédric Le Goater wrote:
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> ---
> hw/ppc/pnv_psi.c | 10 ----------
> 1 file changed, 10 deletions(-)
>
> diff --git a/hw/ppc/pnv_psi.c b/hw/ppc/pnv_psi.c
> index 950ecca40573..98045ed3d249 100644
> --- a/hw/ppc/pnv_psi.c
> +++ b/hw/ppc/pnv_psi.c
> @@ -219,11 +219,6 @@ static void pnv_psi_power8_set_irq(void *opaque, int irq, int state)
> uint32_t src;
> bool masked;
>
> - if (irq > PSIHB_IRQ_EXTERNAL) {
> - qemu_log_mask(LOG_GUEST_ERROR, "PSI: Unsupported irq %d\n", irq);
> - return;
> - }
> -
> xivr_reg = xivr_regs[irq];
> stat_reg = stat_regs[irq];
>
> @@ -813,11 +808,6 @@ static void pnv_psi_power9_set_irq(void *opaque, int irq, int state)
> PnvPsi *psi = opaque;
> uint64_t irq_method = psi->regs[PSIHB_REG(PSIHB9_INTERRUPT_CONTROL)];
>
> - if (irq > PSIHB9_NUM_IRQS) {
> - qemu_log_mask(LOG_GUEST_ERROR, "PSI: Unsupported irq %d\n", irq);
> - return;
> - }
> -
> if (irq_method & PSIHB9_IRQ_METHOD) {
> qemu_log_mask(LOG_GUEST_ERROR, "PSI: LSI IRQ method no supported\n");
> return;
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 0/5] ppc/pnv: Introduce GPIO lines to drive the PSIHB device
2022-03-23 7:28 [PATCH 0/5] ppc/pnv: Introduce GPIO lines to drive the PSIHB device Cédric Le Goater
` (4 preceding siblings ...)
2022-03-23 7:28 ` [PATCH 5/5] ppc/pnv: Remove usless checks in set_irq handlers Cédric Le Goater
@ 2022-03-24 18:02 ` Daniel Henrique Barboza
2022-04-20 19:11 ` Daniel Henrique Barboza
6 siblings, 0 replies; 9+ messages in thread
From: Daniel Henrique Barboza @ 2022-03-24 18:02 UTC (permalink / raw)
To: Cédric Le Goater, qemu-ppc, qemu-devel; +Cc: Frederic Barrat
On 3/23/22 04:28, Cédric Le Goater wrote:
> Hello,
>
> The PSIHB OCC and LPC interrupts are driven by a complex framework
> using Object links and class handlers. Simplify the whole with GPIO
> lines.
Series LGTM. All patches:
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Daniel
>
> Thanks,
>
> C.
>
> Cédric Le Goater (5):
> ppc/pnv: Fix PSI IRQ definition
> ppc/pnv: Remove PnvLpcController::psi link
> ppc/pnv: Remove PnvOCC::psi link
> ppc/pnv: Remove PnvPsiClas::irq_set
> ppc/pnv: Remove usless checks in set_irq handlers
>
> include/hw/ppc/pnv_lpc.h | 8 ++------
> include/hw/ppc/pnv_occ.h | 7 ++-----
> include/hw/ppc/pnv_psi.h | 7 +------
> hw/ppc/pnv.c | 30 ++++++++++++++++++------------
> hw/ppc/pnv_lpc.c | 19 ++++---------------
> hw/ppc/pnv_occ.c | 16 ++++------------
> hw/ppc/pnv_psi.c | 36 +++++++++++-------------------------
> 7 files changed, 42 insertions(+), 81 deletions(-)
>
^ permalink raw reply [flat|nested] 9+ messages in thread* Re: [PATCH 0/5] ppc/pnv: Introduce GPIO lines to drive the PSIHB device
2022-03-23 7:28 [PATCH 0/5] ppc/pnv: Introduce GPIO lines to drive the PSIHB device Cédric Le Goater
` (5 preceding siblings ...)
2022-03-24 18:02 ` [PATCH 0/5] ppc/pnv: Introduce GPIO lines to drive the PSIHB device Daniel Henrique Barboza
@ 2022-04-20 19:11 ` Daniel Henrique Barboza
6 siblings, 0 replies; 9+ messages in thread
From: Daniel Henrique Barboza @ 2022-04-20 19:11 UTC (permalink / raw)
To: Cédric Le Goater, qemu-ppc, qemu-devel; +Cc: Frederic Barrat
On 3/23/22 04:28, Cédric Le Goater wrote:
> Hello,
>
> The PSIHB OCC and LPC interrupts are driven by a complex framework
> using Object links and class handlers. Simplify the whole with GPIO
> lines.
>
> Thanks,
Queued in gitlab.com/danielhb/qemu/tree/ppc-next. Thanks,
Daniel
>
> C.
>
> Cédric Le Goater (5):
> ppc/pnv: Fix PSI IRQ definition
> ppc/pnv: Remove PnvLpcController::psi link
> ppc/pnv: Remove PnvOCC::psi link
> ppc/pnv: Remove PnvPsiClas::irq_set
> ppc/pnv: Remove usless checks in set_irq handlers
>
> include/hw/ppc/pnv_lpc.h | 8 ++------
> include/hw/ppc/pnv_occ.h | 7 ++-----
> include/hw/ppc/pnv_psi.h | 7 +------
> hw/ppc/pnv.c | 30 ++++++++++++++++++------------
> hw/ppc/pnv_lpc.c | 19 ++++---------------
> hw/ppc/pnv_occ.c | 16 ++++------------
> hw/ppc/pnv_psi.c | 36 +++++++++++-------------------------
> 7 files changed, 42 insertions(+), 81 deletions(-)
>
^ permalink raw reply [flat|nested] 9+ messages in thread