* [PATCH 1/2] target/riscv: optimize condition assign for scale < 0
@ 2022-03-25 8:59 Weiwei Li
2022-03-25 8:59 ` [PATCH 2/2] target/riscv: optimize helper for vmv<nr>r.v Weiwei Li
` (3 more replies)
0 siblings, 4 replies; 7+ messages in thread
From: Weiwei Li @ 2022-03-25 8:59 UTC (permalink / raw)
To: richard.henderson, palmer, alistair.francis, bin.meng, qemu-riscv,
qemu-devel
Cc: wangjunqiang, Weiwei Li, lazyparser
for some cases, scale is always equal or less than 0, since lmul is not larger than 3
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
---
target/riscv/insn_trans/trans_rvv.c.inc | 8 +++-----
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index 4ea7e41e1a..2878ca3132 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -1198,7 +1198,7 @@ GEN_LDST_WHOLE_TRANS(vs8r_v, 8, true)
static inline uint32_t MAXSZ(DisasContext *s)
{
int scale = s->lmul - 3;
- return scale < 0 ? s->cfg_ptr->vlen >> -scale : s->cfg_ptr->vlen << scale;
+ return s->cfg_ptr->vlen >> -scale;
}
static bool opivv_check(DisasContext *s, arg_rmrr *a)
@@ -3597,8 +3597,7 @@ static bool trans_vrgather_vx(DisasContext *s, arg_rmrr *a)
if (a->vm && s->vl_eq_vlmax) {
int scale = s->lmul - (s->sew + 3);
- int vlmax = scale < 0 ?
- s->cfg_ptr->vlen >> -scale : s->cfg_ptr->vlen << scale;
+ int vlmax = s->cfg_ptr->vlen >> -scale;
TCGv_i64 dest = tcg_temp_new_i64();
if (a->rs1 == 0) {
@@ -3630,8 +3629,7 @@ static bool trans_vrgather_vi(DisasContext *s, arg_rmrr *a)
if (a->vm && s->vl_eq_vlmax) {
int scale = s->lmul - (s->sew + 3);
- int vlmax = scale < 0 ?
- s->cfg_ptr->vlen >> -scale : s->cfg_ptr->vlen << scale;
+ int vlmax = s->cfg_ptr->vlen >> -scale;
if (a->rs1 >= vlmax) {
tcg_gen_gvec_dup_imm(MO_64, vreg_ofs(s, a->rd),
MAXSZ(s), MAXSZ(s), 0);
--
2.17.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH 2/2] target/riscv: optimize helper for vmv<nr>r.v
2022-03-25 8:59 [PATCH 1/2] target/riscv: optimize condition assign for scale < 0 Weiwei Li
@ 2022-03-25 8:59 ` Weiwei Li
2022-03-25 9:26 ` Frank Chang
2022-03-28 1:11 ` Alistair Francis
2022-03-25 9:26 ` [PATCH 1/2] target/riscv: optimize condition assign for scale < 0 Frank Chang
` (2 subsequent siblings)
3 siblings, 2 replies; 7+ messages in thread
From: Weiwei Li @ 2022-03-25 8:59 UTC (permalink / raw)
To: richard.henderson, palmer, alistair.francis, bin.meng, qemu-riscv,
qemu-devel
Cc: wangjunqiang, Weiwei Li, lazyparser
LEN is not used for GEN_VEXT_VMV_WHOLE macro, so vmv<nr>r.v can share
the same helper
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
---
target/riscv/helper.h | 5 +----
target/riscv/insn_trans/trans_rvv.c.inc | 17 +++++----------
target/riscv/vector_helper.c | 29 ++++++++++---------------
3 files changed, 18 insertions(+), 33 deletions(-)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 26bbab2fab..a669d0187b 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -1086,10 +1086,7 @@ DEF_HELPER_6(vcompress_vm_h, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vcompress_vm_w, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vcompress_vm_d, void, ptr, ptr, ptr, ptr, env, i32)
-DEF_HELPER_4(vmv1r_v, void, ptr, ptr, env, i32)
-DEF_HELPER_4(vmv2r_v, void, ptr, ptr, env, i32)
-DEF_HELPER_4(vmv4r_v, void, ptr, ptr, env, i32)
-DEF_HELPER_4(vmv8r_v, void, ptr, ptr, env, i32)
+DEF_HELPER_4(vmvr_v, void, ptr, ptr, env, i32)
DEF_HELPER_5(vzext_vf2_h, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_5(vzext_vf2_w, void, ptr, ptr, ptr, env, i32)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index 2878ca3132..ec7c0e0d36 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -3695,7 +3695,7 @@ static bool trans_vcompress_vm(DisasContext *s, arg_r *a)
* Whole Vector Register Move Instructions ignore vtype and vl setting.
* Thus, we don't need to check vill bit. (Section 16.6)
*/
-#define GEN_VMV_WHOLE_TRANS(NAME, LEN, SEQ) \
+#define GEN_VMV_WHOLE_TRANS(NAME, LEN) \
static bool trans_##NAME(DisasContext *s, arg_##NAME * a) \
{ \
if (require_rvv(s) && \
@@ -3710,13 +3710,8 @@ static bool trans_##NAME(DisasContext *s, arg_##NAME * a) \
} else { \
TCGLabel *over = gen_new_label(); \
tcg_gen_brcondi_tl(TCG_COND_GEU, cpu_vstart, maxsz, over); \
- \
- static gen_helper_gvec_2_ptr * const fns[4] = { \
- gen_helper_vmv1r_v, gen_helper_vmv2r_v, \
- gen_helper_vmv4r_v, gen_helper_vmv8r_v, \
- }; \
tcg_gen_gvec_2_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, a->rs2), \
- cpu_env, maxsz, maxsz, 0, fns[SEQ]); \
+ cpu_env, maxsz, maxsz, 0, gen_helper_vmvr_v); \
mark_vs_dirty(s); \
gen_set_label(over); \
} \
@@ -3725,10 +3720,10 @@ static bool trans_##NAME(DisasContext *s, arg_##NAME * a) \
return false; \
}
-GEN_VMV_WHOLE_TRANS(vmv1r_v, 1, 0)
-GEN_VMV_WHOLE_TRANS(vmv2r_v, 2, 1)
-GEN_VMV_WHOLE_TRANS(vmv4r_v, 4, 2)
-GEN_VMV_WHOLE_TRANS(vmv8r_v, 8, 3)
+GEN_VMV_WHOLE_TRANS(vmv1r_v, 1)
+GEN_VMV_WHOLE_TRANS(vmv2r_v, 2)
+GEN_VMV_WHOLE_TRANS(vmv4r_v, 4)
+GEN_VMV_WHOLE_TRANS(vmv8r_v, 8)
static bool int_ext_check(DisasContext *s, arg_rmr *a, uint8_t div)
{
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 3bd4aac9c9..1d4982ef7f 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -4888,25 +4888,18 @@ GEN_VEXT_VCOMPRESS_VM(vcompress_vm_w, uint32_t, H4)
GEN_VEXT_VCOMPRESS_VM(vcompress_vm_d, uint64_t, H8)
/* Vector Whole Register Move */
-#define GEN_VEXT_VMV_WHOLE(NAME, LEN) \
-void HELPER(NAME)(void *vd, void *vs2, CPURISCVState *env, \
- uint32_t desc) \
-{ \
- /* EEW = 8 */ \
- uint32_t maxsz = simd_maxsz(desc); \
- uint32_t i = env->vstart; \
- \
- memcpy((uint8_t *)vd + H1(i), \
- (uint8_t *)vs2 + H1(i), \
- maxsz - env->vstart); \
- \
- env->vstart = 0; \
-}
+void HELPER(vmvr_v)(void *vd, void *vs2, CPURISCVState *env, uint32_t desc)
+{
+ /* EEW = 8 */
+ uint32_t maxsz = simd_maxsz(desc);
+ uint32_t i = env->vstart;
+
+ memcpy((uint8_t *)vd + H1(i),
+ (uint8_t *)vs2 + H1(i),
+ maxsz - env->vstart);
-GEN_VEXT_VMV_WHOLE(vmv1r_v, 1)
-GEN_VEXT_VMV_WHOLE(vmv2r_v, 2)
-GEN_VEXT_VMV_WHOLE(vmv4r_v, 4)
-GEN_VEXT_VMV_WHOLE(vmv8r_v, 8)
+ env->vstart = 0;
+}
/* Vector Integer Extension */
#define GEN_VEXT_INT_EXT(NAME, ETYPE, DTYPE, HD, HS1) \
--
2.17.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH 2/2] target/riscv: optimize helper for vmv<nr>r.v
2022-03-25 8:59 ` [PATCH 2/2] target/riscv: optimize helper for vmv<nr>r.v Weiwei Li
@ 2022-03-25 9:26 ` Frank Chang
2022-03-28 1:11 ` Alistair Francis
1 sibling, 0 replies; 7+ messages in thread
From: Frank Chang @ 2022-03-25 9:26 UTC (permalink / raw)
To: Weiwei Li
Cc: lazyparser, open list:RISC-V, wangjunqiang, Bin Meng,
Richard Henderson, qemu-devel@nongnu.org Developers,
Palmer Dabbelt, Alistair Francis
[-- Attachment #1: Type: text/plain, Size: 5709 bytes --]
Reviewed-by: Frank Chang <frank.chang@sifive.com>
On Fri, Mar 25, 2022 at 5:00 PM Weiwei Li <liweiwei@iscas.ac.cn> wrote:
> LEN is not used for GEN_VEXT_VMV_WHOLE macro, so vmv<nr>r.v can share
> the same helper
>
> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
> ---
> target/riscv/helper.h | 5 +----
> target/riscv/insn_trans/trans_rvv.c.inc | 17 +++++----------
> target/riscv/vector_helper.c | 29 ++++++++++---------------
> 3 files changed, 18 insertions(+), 33 deletions(-)
>
> diff --git a/target/riscv/helper.h b/target/riscv/helper.h
> index 26bbab2fab..a669d0187b 100644
> --- a/target/riscv/helper.h
> +++ b/target/riscv/helper.h
> @@ -1086,10 +1086,7 @@ DEF_HELPER_6(vcompress_vm_h, void, ptr, ptr, ptr,
> ptr, env, i32)
> DEF_HELPER_6(vcompress_vm_w, void, ptr, ptr, ptr, ptr, env, i32)
> DEF_HELPER_6(vcompress_vm_d, void, ptr, ptr, ptr, ptr, env, i32)
>
> -DEF_HELPER_4(vmv1r_v, void, ptr, ptr, env, i32)
> -DEF_HELPER_4(vmv2r_v, void, ptr, ptr, env, i32)
> -DEF_HELPER_4(vmv4r_v, void, ptr, ptr, env, i32)
> -DEF_HELPER_4(vmv8r_v, void, ptr, ptr, env, i32)
> +DEF_HELPER_4(vmvr_v, void, ptr, ptr, env, i32)
>
> DEF_HELPER_5(vzext_vf2_h, void, ptr, ptr, ptr, env, i32)
> DEF_HELPER_5(vzext_vf2_w, void, ptr, ptr, ptr, env, i32)
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
> b/target/riscv/insn_trans/trans_rvv.c.inc
> index 2878ca3132..ec7c0e0d36 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -3695,7 +3695,7 @@ static bool trans_vcompress_vm(DisasContext *s,
> arg_r *a)
> * Whole Vector Register Move Instructions ignore vtype and vl setting.
> * Thus, we don't need to check vill bit. (Section 16.6)
> */
> -#define GEN_VMV_WHOLE_TRANS(NAME, LEN, SEQ) \
> +#define GEN_VMV_WHOLE_TRANS(NAME, LEN) \
> static bool trans_##NAME(DisasContext *s, arg_##NAME * a) \
> { \
> if (require_rvv(s) && \
> @@ -3710,13 +3710,8 @@ static bool trans_##NAME(DisasContext *s,
> arg_##NAME * a) \
> } else { \
> TCGLabel *over = gen_new_label(); \
> tcg_gen_brcondi_tl(TCG_COND_GEU, cpu_vstart, maxsz, over); \
> - \
> - static gen_helper_gvec_2_ptr * const fns[4] = { \
> - gen_helper_vmv1r_v, gen_helper_vmv2r_v, \
> - gen_helper_vmv4r_v, gen_helper_vmv8r_v, \
> - }; \
> tcg_gen_gvec_2_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, a->rs2), \
> - cpu_env, maxsz, maxsz, 0, fns[SEQ]); \
> + cpu_env, maxsz, maxsz, 0,
> gen_helper_vmvr_v); \
> mark_vs_dirty(s); \
> gen_set_label(over); \
> } \
> @@ -3725,10 +3720,10 @@ static bool trans_##NAME(DisasContext *s,
> arg_##NAME * a) \
> return false; \
> }
>
> -GEN_VMV_WHOLE_TRANS(vmv1r_v, 1, 0)
> -GEN_VMV_WHOLE_TRANS(vmv2r_v, 2, 1)
> -GEN_VMV_WHOLE_TRANS(vmv4r_v, 4, 2)
> -GEN_VMV_WHOLE_TRANS(vmv8r_v, 8, 3)
> +GEN_VMV_WHOLE_TRANS(vmv1r_v, 1)
> +GEN_VMV_WHOLE_TRANS(vmv2r_v, 2)
> +GEN_VMV_WHOLE_TRANS(vmv4r_v, 4)
> +GEN_VMV_WHOLE_TRANS(vmv8r_v, 8)
>
> static bool int_ext_check(DisasContext *s, arg_rmr *a, uint8_t div)
> {
> diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
> index 3bd4aac9c9..1d4982ef7f 100644
> --- a/target/riscv/vector_helper.c
> +++ b/target/riscv/vector_helper.c
> @@ -4888,25 +4888,18 @@ GEN_VEXT_VCOMPRESS_VM(vcompress_vm_w, uint32_t, H4)
> GEN_VEXT_VCOMPRESS_VM(vcompress_vm_d, uint64_t, H8)
>
> /* Vector Whole Register Move */
> -#define GEN_VEXT_VMV_WHOLE(NAME, LEN) \
> -void HELPER(NAME)(void *vd, void *vs2, CPURISCVState *env, \
> - uint32_t desc) \
> -{ \
> - /* EEW = 8 */ \
> - uint32_t maxsz = simd_maxsz(desc); \
> - uint32_t i = env->vstart; \
> - \
> - memcpy((uint8_t *)vd + H1(i), \
> - (uint8_t *)vs2 + H1(i), \
> - maxsz - env->vstart); \
> - \
> - env->vstart = 0; \
> -}
> +void HELPER(vmvr_v)(void *vd, void *vs2, CPURISCVState *env, uint32_t
> desc)
> +{
> + /* EEW = 8 */
> + uint32_t maxsz = simd_maxsz(desc);
> + uint32_t i = env->vstart;
> +
> + memcpy((uint8_t *)vd + H1(i),
> + (uint8_t *)vs2 + H1(i),
> + maxsz - env->vstart);
>
> -GEN_VEXT_VMV_WHOLE(vmv1r_v, 1)
> -GEN_VEXT_VMV_WHOLE(vmv2r_v, 2)
> -GEN_VEXT_VMV_WHOLE(vmv4r_v, 4)
> -GEN_VEXT_VMV_WHOLE(vmv8r_v, 8)
> + env->vstart = 0;
> +}
>
> /* Vector Integer Extension */
> #define GEN_VEXT_INT_EXT(NAME, ETYPE, DTYPE, HD, HS1) \
> --
> 2.17.1
>
>
>
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^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 1/2] target/riscv: optimize condition assign for scale < 0
2022-03-25 8:59 [PATCH 1/2] target/riscv: optimize condition assign for scale < 0 Weiwei Li
2022-03-25 8:59 ` [PATCH 2/2] target/riscv: optimize helper for vmv<nr>r.v Weiwei Li
@ 2022-03-25 9:26 ` Frank Chang
2022-03-28 1:11 ` Alistair Francis
2022-03-28 4:01 ` Alistair Francis
3 siblings, 0 replies; 7+ messages in thread
From: Frank Chang @ 2022-03-25 9:26 UTC (permalink / raw)
To: Weiwei Li
Cc: lazyparser, open list:RISC-V, wangjunqiang, Bin Meng,
Richard Henderson, qemu-devel@nongnu.org Developers,
Palmer Dabbelt, Alistair Francis
[-- Attachment #1: Type: text/plain, Size: 1952 bytes --]
Reviewed-by: Frank Chang <frank.chang@sifive.com>
On Fri, Mar 25, 2022 at 5:00 PM Weiwei Li <liweiwei@iscas.ac.cn> wrote:
> for some cases, scale is always equal or less than 0, since lmul is not
> larger than 3
>
> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
> ---
> target/riscv/insn_trans/trans_rvv.c.inc | 8 +++-----
> 1 file changed, 3 insertions(+), 5 deletions(-)
>
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
> b/target/riscv/insn_trans/trans_rvv.c.inc
> index 4ea7e41e1a..2878ca3132 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -1198,7 +1198,7 @@ GEN_LDST_WHOLE_TRANS(vs8r_v, 8, true)
> static inline uint32_t MAXSZ(DisasContext *s)
> {
> int scale = s->lmul - 3;
> - return scale < 0 ? s->cfg_ptr->vlen >> -scale : s->cfg_ptr->vlen <<
> scale;
> + return s->cfg_ptr->vlen >> -scale;
> }
>
> static bool opivv_check(DisasContext *s, arg_rmrr *a)
> @@ -3597,8 +3597,7 @@ static bool trans_vrgather_vx(DisasContext *s,
> arg_rmrr *a)
>
> if (a->vm && s->vl_eq_vlmax) {
> int scale = s->lmul - (s->sew + 3);
> - int vlmax = scale < 0 ?
> - s->cfg_ptr->vlen >> -scale : s->cfg_ptr->vlen <<
> scale;
> + int vlmax = s->cfg_ptr->vlen >> -scale;
> TCGv_i64 dest = tcg_temp_new_i64();
>
> if (a->rs1 == 0) {
> @@ -3630,8 +3629,7 @@ static bool trans_vrgather_vi(DisasContext *s,
> arg_rmrr *a)
>
> if (a->vm && s->vl_eq_vlmax) {
> int scale = s->lmul - (s->sew + 3);
> - int vlmax = scale < 0 ?
> - s->cfg_ptr->vlen >> -scale : s->cfg_ptr->vlen <<
> scale;
> + int vlmax = s->cfg_ptr->vlen >> -scale;
> if (a->rs1 >= vlmax) {
> tcg_gen_gvec_dup_imm(MO_64, vreg_ofs(s, a->rd),
> MAXSZ(s), MAXSZ(s), 0);
> --
> 2.17.1
>
>
>
[-- Attachment #2: Type: text/html, Size: 2847 bytes --]
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 2/2] target/riscv: optimize helper for vmv<nr>r.v
2022-03-25 8:59 ` [PATCH 2/2] target/riscv: optimize helper for vmv<nr>r.v Weiwei Li
2022-03-25 9:26 ` Frank Chang
@ 2022-03-28 1:11 ` Alistair Francis
1 sibling, 0 replies; 7+ messages in thread
From: Alistair Francis @ 2022-03-28 1:11 UTC (permalink / raw)
To: Weiwei Li
Cc: Wei Wu (吴伟), open list:RISC-V, wangjunqiang,
Bin Meng, Richard Henderson, qemu-devel@nongnu.org Developers,
Palmer Dabbelt, Alistair Francis
On Fri, Mar 25, 2022 at 7:01 PM Weiwei Li <liweiwei@iscas.ac.cn> wrote:
>
> LEN is not used for GEN_VEXT_VMV_WHOLE macro, so vmv<nr>r.v can share
> the same helper
>
> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/helper.h | 5 +----
> target/riscv/insn_trans/trans_rvv.c.inc | 17 +++++----------
> target/riscv/vector_helper.c | 29 ++++++++++---------------
> 3 files changed, 18 insertions(+), 33 deletions(-)
>
> diff --git a/target/riscv/helper.h b/target/riscv/helper.h
> index 26bbab2fab..a669d0187b 100644
> --- a/target/riscv/helper.h
> +++ b/target/riscv/helper.h
> @@ -1086,10 +1086,7 @@ DEF_HELPER_6(vcompress_vm_h, void, ptr, ptr, ptr, ptr, env, i32)
> DEF_HELPER_6(vcompress_vm_w, void, ptr, ptr, ptr, ptr, env, i32)
> DEF_HELPER_6(vcompress_vm_d, void, ptr, ptr, ptr, ptr, env, i32)
>
> -DEF_HELPER_4(vmv1r_v, void, ptr, ptr, env, i32)
> -DEF_HELPER_4(vmv2r_v, void, ptr, ptr, env, i32)
> -DEF_HELPER_4(vmv4r_v, void, ptr, ptr, env, i32)
> -DEF_HELPER_4(vmv8r_v, void, ptr, ptr, env, i32)
> +DEF_HELPER_4(vmvr_v, void, ptr, ptr, env, i32)
>
> DEF_HELPER_5(vzext_vf2_h, void, ptr, ptr, ptr, env, i32)
> DEF_HELPER_5(vzext_vf2_w, void, ptr, ptr, ptr, env, i32)
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
> index 2878ca3132..ec7c0e0d36 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -3695,7 +3695,7 @@ static bool trans_vcompress_vm(DisasContext *s, arg_r *a)
> * Whole Vector Register Move Instructions ignore vtype and vl setting.
> * Thus, we don't need to check vill bit. (Section 16.6)
> */
> -#define GEN_VMV_WHOLE_TRANS(NAME, LEN, SEQ) \
> +#define GEN_VMV_WHOLE_TRANS(NAME, LEN) \
> static bool trans_##NAME(DisasContext *s, arg_##NAME * a) \
> { \
> if (require_rvv(s) && \
> @@ -3710,13 +3710,8 @@ static bool trans_##NAME(DisasContext *s, arg_##NAME * a) \
> } else { \
> TCGLabel *over = gen_new_label(); \
> tcg_gen_brcondi_tl(TCG_COND_GEU, cpu_vstart, maxsz, over); \
> - \
> - static gen_helper_gvec_2_ptr * const fns[4] = { \
> - gen_helper_vmv1r_v, gen_helper_vmv2r_v, \
> - gen_helper_vmv4r_v, gen_helper_vmv8r_v, \
> - }; \
> tcg_gen_gvec_2_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, a->rs2), \
> - cpu_env, maxsz, maxsz, 0, fns[SEQ]); \
> + cpu_env, maxsz, maxsz, 0, gen_helper_vmvr_v); \
> mark_vs_dirty(s); \
> gen_set_label(over); \
> } \
> @@ -3725,10 +3720,10 @@ static bool trans_##NAME(DisasContext *s, arg_##NAME * a) \
> return false; \
> }
>
> -GEN_VMV_WHOLE_TRANS(vmv1r_v, 1, 0)
> -GEN_VMV_WHOLE_TRANS(vmv2r_v, 2, 1)
> -GEN_VMV_WHOLE_TRANS(vmv4r_v, 4, 2)
> -GEN_VMV_WHOLE_TRANS(vmv8r_v, 8, 3)
> +GEN_VMV_WHOLE_TRANS(vmv1r_v, 1)
> +GEN_VMV_WHOLE_TRANS(vmv2r_v, 2)
> +GEN_VMV_WHOLE_TRANS(vmv4r_v, 4)
> +GEN_VMV_WHOLE_TRANS(vmv8r_v, 8)
>
> static bool int_ext_check(DisasContext *s, arg_rmr *a, uint8_t div)
> {
> diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
> index 3bd4aac9c9..1d4982ef7f 100644
> --- a/target/riscv/vector_helper.c
> +++ b/target/riscv/vector_helper.c
> @@ -4888,25 +4888,18 @@ GEN_VEXT_VCOMPRESS_VM(vcompress_vm_w, uint32_t, H4)
> GEN_VEXT_VCOMPRESS_VM(vcompress_vm_d, uint64_t, H8)
>
> /* Vector Whole Register Move */
> -#define GEN_VEXT_VMV_WHOLE(NAME, LEN) \
> -void HELPER(NAME)(void *vd, void *vs2, CPURISCVState *env, \
> - uint32_t desc) \
> -{ \
> - /* EEW = 8 */ \
> - uint32_t maxsz = simd_maxsz(desc); \
> - uint32_t i = env->vstart; \
> - \
> - memcpy((uint8_t *)vd + H1(i), \
> - (uint8_t *)vs2 + H1(i), \
> - maxsz - env->vstart); \
> - \
> - env->vstart = 0; \
> -}
> +void HELPER(vmvr_v)(void *vd, void *vs2, CPURISCVState *env, uint32_t desc)
> +{
> + /* EEW = 8 */
> + uint32_t maxsz = simd_maxsz(desc);
> + uint32_t i = env->vstart;
> +
> + memcpy((uint8_t *)vd + H1(i),
> + (uint8_t *)vs2 + H1(i),
> + maxsz - env->vstart);
>
> -GEN_VEXT_VMV_WHOLE(vmv1r_v, 1)
> -GEN_VEXT_VMV_WHOLE(vmv2r_v, 2)
> -GEN_VEXT_VMV_WHOLE(vmv4r_v, 4)
> -GEN_VEXT_VMV_WHOLE(vmv8r_v, 8)
> + env->vstart = 0;
> +}
>
> /* Vector Integer Extension */
> #define GEN_VEXT_INT_EXT(NAME, ETYPE, DTYPE, HD, HS1) \
> --
> 2.17.1
>
>
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 1/2] target/riscv: optimize condition assign for scale < 0
2022-03-25 8:59 [PATCH 1/2] target/riscv: optimize condition assign for scale < 0 Weiwei Li
2022-03-25 8:59 ` [PATCH 2/2] target/riscv: optimize helper for vmv<nr>r.v Weiwei Li
2022-03-25 9:26 ` [PATCH 1/2] target/riscv: optimize condition assign for scale < 0 Frank Chang
@ 2022-03-28 1:11 ` Alistair Francis
2022-03-28 4:01 ` Alistair Francis
3 siblings, 0 replies; 7+ messages in thread
From: Alistair Francis @ 2022-03-28 1:11 UTC (permalink / raw)
To: Weiwei Li
Cc: Wei Wu (吴伟), open list:RISC-V, wangjunqiang,
Bin Meng, Richard Henderson, qemu-devel@nongnu.org Developers,
Palmer Dabbelt, Alistair Francis
On Fri, Mar 25, 2022 at 7:03 PM Weiwei Li <liweiwei@iscas.ac.cn> wrote:
>
> for some cases, scale is always equal or less than 0, since lmul is not larger than 3
>
> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/insn_trans/trans_rvv.c.inc | 8 +++-----
> 1 file changed, 3 insertions(+), 5 deletions(-)
>
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
> index 4ea7e41e1a..2878ca3132 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -1198,7 +1198,7 @@ GEN_LDST_WHOLE_TRANS(vs8r_v, 8, true)
> static inline uint32_t MAXSZ(DisasContext *s)
> {
> int scale = s->lmul - 3;
> - return scale < 0 ? s->cfg_ptr->vlen >> -scale : s->cfg_ptr->vlen << scale;
> + return s->cfg_ptr->vlen >> -scale;
> }
>
> static bool opivv_check(DisasContext *s, arg_rmrr *a)
> @@ -3597,8 +3597,7 @@ static bool trans_vrgather_vx(DisasContext *s, arg_rmrr *a)
>
> if (a->vm && s->vl_eq_vlmax) {
> int scale = s->lmul - (s->sew + 3);
> - int vlmax = scale < 0 ?
> - s->cfg_ptr->vlen >> -scale : s->cfg_ptr->vlen << scale;
> + int vlmax = s->cfg_ptr->vlen >> -scale;
> TCGv_i64 dest = tcg_temp_new_i64();
>
> if (a->rs1 == 0) {
> @@ -3630,8 +3629,7 @@ static bool trans_vrgather_vi(DisasContext *s, arg_rmrr *a)
>
> if (a->vm && s->vl_eq_vlmax) {
> int scale = s->lmul - (s->sew + 3);
> - int vlmax = scale < 0 ?
> - s->cfg_ptr->vlen >> -scale : s->cfg_ptr->vlen << scale;
> + int vlmax = s->cfg_ptr->vlen >> -scale;
> if (a->rs1 >= vlmax) {
> tcg_gen_gvec_dup_imm(MO_64, vreg_ofs(s, a->rd),
> MAXSZ(s), MAXSZ(s), 0);
> --
> 2.17.1
>
>
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 1/2] target/riscv: optimize condition assign for scale < 0
2022-03-25 8:59 [PATCH 1/2] target/riscv: optimize condition assign for scale < 0 Weiwei Li
` (2 preceding siblings ...)
2022-03-28 1:11 ` Alistair Francis
@ 2022-03-28 4:01 ` Alistair Francis
3 siblings, 0 replies; 7+ messages in thread
From: Alistair Francis @ 2022-03-28 4:01 UTC (permalink / raw)
To: Weiwei Li
Cc: Wei Wu (吴伟), open list:RISC-V, wangjunqiang,
Bin Meng, Richard Henderson, qemu-devel@nongnu.org Developers,
Palmer Dabbelt, Alistair Francis
On Fri, Mar 25, 2022 at 7:03 PM Weiwei Li <liweiwei@iscas.ac.cn> wrote:
>
> for some cases, scale is always equal or less than 0, since lmul is not larger than 3
>
> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Thanks!
Applied to riscv-to-apply.next
Alistair
> ---
> target/riscv/insn_trans/trans_rvv.c.inc | 8 +++-----
> 1 file changed, 3 insertions(+), 5 deletions(-)
>
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
> index 4ea7e41e1a..2878ca3132 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -1198,7 +1198,7 @@ GEN_LDST_WHOLE_TRANS(vs8r_v, 8, true)
> static inline uint32_t MAXSZ(DisasContext *s)
> {
> int scale = s->lmul - 3;
> - return scale < 0 ? s->cfg_ptr->vlen >> -scale : s->cfg_ptr->vlen << scale;
> + return s->cfg_ptr->vlen >> -scale;
> }
>
> static bool opivv_check(DisasContext *s, arg_rmrr *a)
> @@ -3597,8 +3597,7 @@ static bool trans_vrgather_vx(DisasContext *s, arg_rmrr *a)
>
> if (a->vm && s->vl_eq_vlmax) {
> int scale = s->lmul - (s->sew + 3);
> - int vlmax = scale < 0 ?
> - s->cfg_ptr->vlen >> -scale : s->cfg_ptr->vlen << scale;
> + int vlmax = s->cfg_ptr->vlen >> -scale;
> TCGv_i64 dest = tcg_temp_new_i64();
>
> if (a->rs1 == 0) {
> @@ -3630,8 +3629,7 @@ static bool trans_vrgather_vi(DisasContext *s, arg_rmrr *a)
>
> if (a->vm && s->vl_eq_vlmax) {
> int scale = s->lmul - (s->sew + 3);
> - int vlmax = scale < 0 ?
> - s->cfg_ptr->vlen >> -scale : s->cfg_ptr->vlen << scale;
> + int vlmax = s->cfg_ptr->vlen >> -scale;
> if (a->rs1 >= vlmax) {
> tcg_gen_gvec_dup_imm(MO_64, vreg_ofs(s, a->rd),
> MAXSZ(s), MAXSZ(s), 0);
> --
> 2.17.1
>
>
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2022-03-28 4:08 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz follow: Atom feed
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2022-03-25 8:59 [PATCH 1/2] target/riscv: optimize condition assign for scale < 0 Weiwei Li
2022-03-25 8:59 ` [PATCH 2/2] target/riscv: optimize helper for vmv<nr>r.v Weiwei Li
2022-03-25 9:26 ` Frank Chang
2022-03-28 1:11 ` Alistair Francis
2022-03-25 9:26 ` [PATCH 1/2] target/riscv: optimize condition assign for scale < 0 Frank Chang
2022-03-28 1:11 ` Alistair Francis
2022-03-28 4:01 ` Alistair Francis
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