From: Idan Horowitz <idan.horowitz@gmail.com>
To: qemu-arm@nongnu.org
Cc: "Peter Maydell" <peter.maydell@linaro.org>,
"Idan Horowitz" <idan.horowitz@gmail.com>,
qemu-devel@nongnu.org, "Rémi Denis-Courmont" <remi@remlab.net>
Subject: Re: [PATCH 1/3] target/arm: Check VSTCR.SW when assigning the stage 2 output PA space
Date: Mon, 28 Mar 2022 00:45:51 +0300 [thread overview]
Message-ID: <20220327214551.2070008-1-idan.horowitz@gmail.com> (raw)
Rémi Denis-Courmont <remi@remlab.net> wrote:
> The VTCR_EL2 specification says that the NSA bit "behaves as 1 for all purposes
> other than reading back the value of the bit when one of the following is true
> (...)
> * The value of VTCR_EL2.NSW is 1.
> * The value of VSTCR_EL2.SA is 1."
>
> Sorry but I don't see any reason to check the SW bit here.
That still does not cover the case of NSA=0, NSW=0, SA=0, SW=1.
> --
> Реми Дёни-Курмон
> http://www.remlab.net/
Idan Horowitz
next reply other threads:[~2022-03-27 21:47 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-03-27 21:45 Idan Horowitz [this message]
-- strict thread matches above, loose matches on Subject: below --
2022-03-27 9:34 [PATCH 0/3] Bug fixes related to secure 2 stage translation Idan Horowitz
2022-03-27 9:34 ` [PATCH 1/3] target/arm: Check VSTCR.SW when assigning the stage 2 output PA space Idan Horowitz
2022-03-27 14:24 ` Rémi Denis-Courmont
2022-03-29 14:59 ` Richard Henderson
2022-03-29 14:59 ` Richard Henderson
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