* [PATCH 1/3] target/arm: Check VSTCR.SW when assigning the stage 2 output PA space
2022-03-27 9:34 [PATCH 0/3] Bug fixes related to secure 2 stage translation Idan Horowitz
@ 2022-03-27 9:34 ` Idan Horowitz
2022-03-27 14:24 ` Rémi Denis-Courmont
2022-03-29 14:59 ` Richard Henderson
0 siblings, 2 replies; 5+ messages in thread
From: Idan Horowitz @ 2022-03-27 9:34 UTC (permalink / raw)
To: qemu-arm; +Cc: Peter Maydell, Idan Horowitz, qemu-devel
As per the AArch64.SS2OutputPASpace() psuedo-code in the ARMv8 ARM when the
PA space of the IPA is non secure, the output PA space is secure if and only
if all of the bits VTCR.<NSW, NSA>, VSTCR.<SW, SA> are not set.
Signed-off-by: Idan Horowitz <idan.horowitz@gmail.com>
---
target/arm/helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 812ca591f4..d0265b760f 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -12697,7 +12697,7 @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
} else {
attrs->secure =
!((env->cp15.vtcr_el2.raw_tcr & (VTCR_NSA | VTCR_NSW))
- || (env->cp15.vstcr_el2.raw_tcr & VSTCR_SA));
+ || (env->cp15.vstcr_el2.raw_tcr & (VSTCR_SA | VSTCR_SW)));
}
}
return 0;
--
2.35.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH 1/3] target/arm: Check VSTCR.SW when assigning the stage 2 output PA space
2022-03-27 9:34 ` [PATCH 1/3] target/arm: Check VSTCR.SW when assigning the stage 2 output PA space Idan Horowitz
@ 2022-03-27 14:24 ` Rémi Denis-Courmont
2022-03-29 14:59 ` Richard Henderson
2022-03-29 14:59 ` Richard Henderson
1 sibling, 1 reply; 5+ messages in thread
From: Rémi Denis-Courmont @ 2022-03-27 14:24 UTC (permalink / raw)
To: qemu-arm; +Cc: Peter Maydell, Idan Horowitz, qemu-devel
Le sunnuntaina 27. maaliskuuta 2022, 12.34.26 EEST Idan Horowitz a écrit :
> As per the AArch64.SS2OutputPASpace() psuedo-code in the ARMv8 ARM when the
> PA space of the IPA is non secure, the output PA space is secure if and only
> if all of the bits VTCR.<NSW, NSA>, VSTCR.<SW, SA> are not set.
>
> Signed-off-by: Idan Horowitz <idan.horowitz@gmail.com>
> ---
> target/arm/helper.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target/arm/helper.c b/target/arm/helper.c
> index 812ca591f4..d0265b760f 100644
> --- a/target/arm/helper.c
> +++ b/target/arm/helper.c
> @@ -12697,7 +12697,7 @@ bool get_phys_addr(CPUARMState *env, target_ulong
> address, } else {
> attrs->secure =
> !((env->cp15.vtcr_el2.raw_tcr & (VTCR_NSA |
> VTCR_NSW)) - || (env->cp15.vstcr_el2.raw_tcr &
> VSTCR_SA)); + || (env->cp15.vstcr_el2.raw_tcr &
> (VSTCR_SA | VSTCR_SW))); }
The VTCR_EL2 specification says that the NSA bit "behaves as 1 for all purposes
other than reading back the value of the bit when one of the following is true
(...)
* The value of VTCR_EL2.NSW is 1.
* The value of VSTCR_EL2.SA is 1."
Sorry but I don't see any reason to check the SW bit here.
--
Реми Дёни-Курмон
http://www.remlab.net/
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH 1/3] target/arm: Check VSTCR.SW when assigning the stage 2 output PA space
@ 2022-03-27 21:45 Idan Horowitz
0 siblings, 0 replies; 5+ messages in thread
From: Idan Horowitz @ 2022-03-27 21:45 UTC (permalink / raw)
To: qemu-arm; +Cc: Peter Maydell, Idan Horowitz, qemu-devel,
Rémi Denis-Courmont
Rémi Denis-Courmont <remi@remlab.net> wrote:
> The VTCR_EL2 specification says that the NSA bit "behaves as 1 for all purposes
> other than reading back the value of the bit when one of the following is true
> (...)
> * The value of VTCR_EL2.NSW is 1.
> * The value of VSTCR_EL2.SA is 1."
>
> Sorry but I don't see any reason to check the SW bit here.
That still does not cover the case of NSA=0, NSW=0, SA=0, SW=1.
> --
> Реми Дёни-Курмон
> http://www.remlab.net/
Idan Horowitz
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH 1/3] target/arm: Check VSTCR.SW when assigning the stage 2 output PA space
2022-03-27 14:24 ` Rémi Denis-Courmont
@ 2022-03-29 14:59 ` Richard Henderson
0 siblings, 0 replies; 5+ messages in thread
From: Richard Henderson @ 2022-03-29 14:59 UTC (permalink / raw)
To: Rémi Denis-Courmont, qemu-arm
Cc: Peter Maydell, Idan Horowitz, qemu-devel
On 3/27/22 08:24, Rémi Denis-Courmont wrote:
> Le sunnuntaina 27. maaliskuuta 2022, 12.34.26 EEST Idan Horowitz a écrit :
>> As per the AArch64.SS2OutputPASpace() psuedo-code in the ARMv8 ARM when the
>> PA space of the IPA is non secure, the output PA space is secure if and only
>> if all of the bits VTCR.<NSW, NSA>, VSTCR.<SW, SA> are not set.
>>
>> Signed-off-by: Idan Horowitz <idan.horowitz@gmail.com>
>> ---
>> target/arm/helper.c | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/target/arm/helper.c b/target/arm/helper.c
>> index 812ca591f4..d0265b760f 100644
>> --- a/target/arm/helper.c
>> +++ b/target/arm/helper.c
>> @@ -12697,7 +12697,7 @@ bool get_phys_addr(CPUARMState *env, target_ulong
>> address, } else {
>> attrs->secure =
>> !((env->cp15.vtcr_el2.raw_tcr & (VTCR_NSA |
>> VTCR_NSW)) - || (env->cp15.vstcr_el2.raw_tcr &
>> VSTCR_SA)); + || (env->cp15.vstcr_el2.raw_tcr &
>> (VSTCR_SA | VSTCR_SW))); }
>
> The VTCR_EL2 specification says that the NSA bit "behaves as 1 for all purposes
> other than reading back the value of the bit when one of the following is true
> (...)
> * The value of VTCR_EL2.NSW is 1.
> * The value of VSTCR_EL2.SA is 1."
>
> Sorry but I don't see any reason to check the SW bit here.
Because the description of SA says that it behaves as 1 if SW is 1.
r~
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH 1/3] target/arm: Check VSTCR.SW when assigning the stage 2 output PA space
2022-03-27 9:34 ` [PATCH 1/3] target/arm: Check VSTCR.SW when assigning the stage 2 output PA space Idan Horowitz
2022-03-27 14:24 ` Rémi Denis-Courmont
@ 2022-03-29 14:59 ` Richard Henderson
1 sibling, 0 replies; 5+ messages in thread
From: Richard Henderson @ 2022-03-29 14:59 UTC (permalink / raw)
To: Idan Horowitz, qemu-arm; +Cc: Peter Maydell, qemu-devel
On 3/27/22 03:34, Idan Horowitz wrote:
> As per the AArch64.SS2OutputPASpace() psuedo-code in the ARMv8 ARM when the
> PA space of the IPA is non secure, the output PA space is secure if and only
> if all of the bits VTCR.<NSW, NSA>, VSTCR.<SW, SA> are not set.
>
> Signed-off-by: Idan Horowitz<idan.horowitz@gmail.com>
> ---
> target/arm/helper.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 5+ messages in thread
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2022-03-27 14:24 ` Rémi Denis-Courmont
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