From: "Alex Bennée" <alex.bennee@linaro.org>
To: qemu-devel@nongnu.org
Cc: "Peter Maydell" <peter.maydell@linaro.org>,
aaron@os.amperecomputing.com, robhenry@microsoft.com,
mahmoudabdalghany@outlook.com, minyihh@uci.edu, cota@braap.org,
Luke.Craig@ll.mit.edu, kuhn.chenqun@huawei.com,
ma.mandourr@gmail.com, "Alex Bennée" <alex.bennee@linaro.org>,
"open list:ARM TCG CPUs" <qemu-arm@nongnu.org>
Subject: [PATCH v1 1/2] tests/tcg: add memory-sve test for aarch64
Date: Mon, 28 Mar 2022 16:26:13 +0100 [thread overview]
Message-ID: <20220328152614.2452259-2-alex.bennee@linaro.org> (raw)
In-Reply-To: <20220328152614.2452259-1-alex.bennee@linaro.org>
This will be helpful in debugging problems with tracking SVE memory
accesses via the TCG plugins system.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Cc: Robert Henry <robhenry@microsoft.com>
Cc: Aaron Lindsay <aaron@os.amperecomputing.com>
---
tests/tcg/aarch64/Makefile.softmmu-target | 7 +++++++
tests/tcg/aarch64/system/boot.S | 3 ++-
2 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/tests/tcg/aarch64/Makefile.softmmu-target b/tests/tcg/aarch64/Makefile.softmmu-target
index a7286ac295..cc02814065 100644
--- a/tests/tcg/aarch64/Makefile.softmmu-target
+++ b/tests/tcg/aarch64/Makefile.softmmu-target
@@ -31,6 +31,13 @@ LDFLAGS+=-static -nostdlib $(CRT_OBJS) $(MINILIB_OBJS) -lgcc
memory: CFLAGS+=-DCHECK_UNALIGNED=1
+memory-sve: memory.c $(LINK_SCRIPT) $(CRT_OBJS) $(MINILIB_OBJS)
+ $(CC) $(CFLAGS) $(EXTRA_CFLAGS) $< -o $@ $(LDFLAGS)
+
+memory-sve: CFLAGS+=-DCHECK_UNALIGNED=1 -march=armv8.1-a+sve -O3 -fno-tree-loop-distribute-patterns
+
+TESTS+=memory-sve
+
# Running
QEMU_BASE_MACHINE=-M virt -cpu max -display none
QEMU_OPTS+=$(QEMU_BASE_MACHINE) -semihosting-config enable=on,target=native,chardev=output -kernel
diff --git a/tests/tcg/aarch64/system/boot.S b/tests/tcg/aarch64/system/boot.S
index e190b1efa6..f136363d2a 100644
--- a/tests/tcg/aarch64/system/boot.S
+++ b/tests/tcg/aarch64/system/boot.S
@@ -179,12 +179,13 @@ __start:
isb
/*
- * Enable FP registers. The standard C pre-amble will be
+ * Enable FP/SVE registers. The standard C pre-amble will be
* saving these and A-profile compilers will use AdvSIMD
* registers unless we tell it not to.
*/
mrs x0, cpacr_el1
orr x0, x0, #(3 << 20)
+ orr x0, x0, #(3 << 16)
msr cpacr_el1, x0
/* Setup some stack space and enter the test code.
--
2.30.2
next prev parent reply other threads:[~2022-03-28 15:28 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-03-28 15:26 [PATCH v1 0/2] some tests and plugin tweaks for SVE Alex Bennée
2022-03-28 15:26 ` Alex Bennée [this message]
2022-03-28 15:26 ` [PATCH v1 2/2] plugins: extend execlog to filter matches Alex Bennée
2022-04-03 13:14 ` Alexandre IOOSS
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