* [RESEND PATCH] target/riscv: fix start byte for vmv<nf>r.v when vstart != 0
@ 2022-03-30 2:13 Weiwei Li
2022-03-31 0:15 ` Alistair Francis
2022-04-06 23:07 ` Alistair Francis
0 siblings, 2 replies; 3+ messages in thread
From: Weiwei Li @ 2022-03-30 2:13 UTC (permalink / raw)
To: palmer, alistair.francis, bin.meng, qemu-riscv, qemu-devel
Cc: wangjunqiang, Weiwei Li, lazyparser
The spec for vmv<nf>r.v says: 'the instructions operate as if EEW=SEW,
EMUL = NREG, effective length evl= EMUL * VLEN/SEW.'
So the start byte for vstart != 0 should take sew into account
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
---
target/riscv/vector_helper.c | 8 +++++---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 1d4982ef7f..b5fbdabbb1 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -4890,13 +4890,15 @@ GEN_VEXT_VCOMPRESS_VM(vcompress_vm_d, uint64_t, H8)
/* Vector Whole Register Move */
void HELPER(vmvr_v)(void *vd, void *vs2, CPURISCVState *env, uint32_t desc)
{
- /* EEW = 8 */
+ /* EEW = SEW */
uint32_t maxsz = simd_maxsz(desc);
- uint32_t i = env->vstart;
+ uint32_t sewb = 1 << FIELD_EX64(env->vtype, VTYPE, VSEW);
+ uint32_t startb = env->vstart * sewb;
+ uint32_t i = startb;
memcpy((uint8_t *)vd + H1(i),
(uint8_t *)vs2 + H1(i),
- maxsz - env->vstart);
+ maxsz - startb);
env->vstart = 0;
}
--
2.17.1
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [RESEND PATCH] target/riscv: fix start byte for vmv<nf>r.v when vstart != 0
2022-03-30 2:13 [RESEND PATCH] target/riscv: fix start byte for vmv<nf>r.v when vstart != 0 Weiwei Li
@ 2022-03-31 0:15 ` Alistair Francis
2022-04-06 23:07 ` Alistair Francis
1 sibling, 0 replies; 3+ messages in thread
From: Alistair Francis @ 2022-03-31 0:15 UTC (permalink / raw)
To: Weiwei Li
Cc: Wei Wu (吴伟), open list:RISC-V, wangjunqiang,
Bin Meng, qemu-devel@nongnu.org Developers, Alistair Francis,
Palmer Dabbelt
On Wed, Mar 30, 2022 at 12:14 PM Weiwei Li <liweiwei@iscas.ac.cn> wrote:
>
> The spec for vmv<nf>r.v says: 'the instructions operate as if EEW=SEW,
> EMUL = NREG, effective length evl= EMUL * VLEN/SEW.'
>
> So the start byte for vstart != 0 should take sew into account
>
> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/vector_helper.c | 8 +++++---
> 1 file changed, 5 insertions(+), 3 deletions(-)
>
> diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
> index 1d4982ef7f..b5fbdabbb1 100644
> --- a/target/riscv/vector_helper.c
> +++ b/target/riscv/vector_helper.c
> @@ -4890,13 +4890,15 @@ GEN_VEXT_VCOMPRESS_VM(vcompress_vm_d, uint64_t, H8)
> /* Vector Whole Register Move */
> void HELPER(vmvr_v)(void *vd, void *vs2, CPURISCVState *env, uint32_t desc)
> {
> - /* EEW = 8 */
> + /* EEW = SEW */
> uint32_t maxsz = simd_maxsz(desc);
> - uint32_t i = env->vstart;
> + uint32_t sewb = 1 << FIELD_EX64(env->vtype, VTYPE, VSEW);
> + uint32_t startb = env->vstart * sewb;
> + uint32_t i = startb;
>
> memcpy((uint8_t *)vd + H1(i),
> (uint8_t *)vs2 + H1(i),
> - maxsz - env->vstart);
> + maxsz - startb);
>
> env->vstart = 0;
> }
> --
> 2.17.1
>
>
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [RESEND PATCH] target/riscv: fix start byte for vmv<nf>r.v when vstart != 0
2022-03-30 2:13 [RESEND PATCH] target/riscv: fix start byte for vmv<nf>r.v when vstart != 0 Weiwei Li
2022-03-31 0:15 ` Alistair Francis
@ 2022-04-06 23:07 ` Alistair Francis
1 sibling, 0 replies; 3+ messages in thread
From: Alistair Francis @ 2022-04-06 23:07 UTC (permalink / raw)
To: Weiwei Li
Cc: Wei Wu (吴伟), open list:RISC-V, wangjunqiang,
Bin Meng, qemu-devel@nongnu.org Developers, Alistair Francis,
Palmer Dabbelt
On Wed, Mar 30, 2022 at 12:14 PM Weiwei Li <liweiwei@iscas.ac.cn> wrote:
>
> The spec for vmv<nf>r.v says: 'the instructions operate as if EEW=SEW,
> EMUL = NREG, effective length evl= EMUL * VLEN/SEW.'
>
> So the start byte for vstart != 0 should take sew into account
>
> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Thanks!
Applied to riscv-to-apply.next
Alistair
> ---
> target/riscv/vector_helper.c | 8 +++++---
> 1 file changed, 5 insertions(+), 3 deletions(-)
>
> diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
> index 1d4982ef7f..b5fbdabbb1 100644
> --- a/target/riscv/vector_helper.c
> +++ b/target/riscv/vector_helper.c
> @@ -4890,13 +4890,15 @@ GEN_VEXT_VCOMPRESS_VM(vcompress_vm_d, uint64_t, H8)
> /* Vector Whole Register Move */
> void HELPER(vmvr_v)(void *vd, void *vs2, CPURISCVState *env, uint32_t desc)
> {
> - /* EEW = 8 */
> + /* EEW = SEW */
> uint32_t maxsz = simd_maxsz(desc);
> - uint32_t i = env->vstart;
> + uint32_t sewb = 1 << FIELD_EX64(env->vtype, VTYPE, VSEW);
> + uint32_t startb = env->vstart * sewb;
> + uint32_t i = startb;
>
> memcpy((uint8_t *)vd + H1(i),
> (uint8_t *)vs2 + H1(i),
> - maxsz - env->vstart);
> + maxsz - startb);
>
> env->vstart = 0;
> }
> --
> 2.17.1
>
>
^ permalink raw reply [flat|nested] 3+ messages in thread
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2022-03-30 2:13 [RESEND PATCH] target/riscv: fix start byte for vmv<nf>r.v when vstart != 0 Weiwei Li
2022-03-31 0:15 ` Alistair Francis
2022-04-06 23:07 ` Alistair Francis
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