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[31.208.27.151]) by smtp.gmail.com with ESMTPSA id d25-20020a194f19000000b0044a2ad98dcasm166203lfb.167.2022.04.01.01.11.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Apr 2022 01:11:53 -0700 (PDT) Date: Fri, 1 Apr 2022 10:11:51 +0200 From: Francisco Iglesias To: "Edgar E. Iglesias" Subject: Re: [PATCH v1 1/2] timer: cadence_ttc: Break out header file to allow embedding Message-ID: <20220401081151.GA18849@fralle-msi> References: <20220331222017.2914409-1-edgar.iglesias@gmail.com> <20220331222017.2914409-2-edgar.iglesias@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20220331222017.2914409-2-edgar.iglesias@gmail.com> User-Agent: Mutt/1.10.1 (2018-07-13) X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::12a (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::12a; envelope-from=frasse.iglesias@gmail.com; helo=mail-lf1-x12a.google.com X-Spam_score_int: -1006 X-Spam_score: -100.7 X-Spam_bar: --------------------------------------------------- X-Spam_report: (-100.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01, USER_IN_WELCOMELIST=-0.01, USER_IN_WHITELIST=-100 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org, luc@lmichel.fr, asifsiddiqui120@gmail.com, edgar.iglesias@amd.com, sai.pavan.boddu@xilinx.com, alistair@alistair23.me, richard.henderson@linaro.org, qemu-devel@nongnu.org, f4bug@amsat.org, francisco.iglesias@xilinx.com, frederic.konrad@adacore.com, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On [2022 Apr 01] Fri 00:20:16, Edgar E. Iglesias wrote: > From: "Edgar E. Iglesias" > > Break out header file to allow embedding of the the TTC. > > Signed-off-by: Edgar E. Iglesias Reviewed-by: Francisco Iglesias > --- > include/hw/timer/cadence_ttc.h | 54 ++++++++++++++++++++++++++++++++++ > hw/timer/cadence_ttc.c | 32 ++------------------ > 2 files changed, 56 insertions(+), 30 deletions(-) > create mode 100644 include/hw/timer/cadence_ttc.h > > diff --git a/include/hw/timer/cadence_ttc.h b/include/hw/timer/cadence_ttc.h > new file mode 100644 > index 0000000000..e1251383f2 > --- /dev/null > +++ b/include/hw/timer/cadence_ttc.h > @@ -0,0 +1,54 @@ > +/* > + * Xilinx Zynq cadence TTC model > + * > + * Copyright (c) 2011 Xilinx Inc. > + * Copyright (c) 2012 Peter A.G. Crosthwaite (peter.crosthwaite@petalogix.com) > + * Copyright (c) 2012 PetaLogix Pty Ltd. > + * Written By Haibing Ma > + * M. Habib > + * > + * This program is free software; you can redistribute it and/or > + * modify it under the terms of the GNU General Public License > + * as published by the Free Software Foundation; either version > + * 2 of the License, or (at your option) any later version. > + * > + * You should have received a copy of the GNU General Public License along > + * with this program; if not, see . > + */ > +#ifndef HW_TIMER_CADENCE_TTC_H > +#define HW_TIMER_CADENCE_TTC_H > + > +#include "hw/sysbus.h" > +#include "qemu/timer.h" > + > +typedef struct { > + QEMUTimer *timer; > + int freq; > + > + uint32_t reg_clock; > + uint32_t reg_count; > + uint32_t reg_value; > + uint16_t reg_interval; > + uint16_t reg_match[3]; > + uint32_t reg_intr; > + uint32_t reg_intr_en; > + uint32_t reg_event_ctrl; > + uint32_t reg_event; > + > + uint64_t cpu_time; > + unsigned int cpu_time_valid; > + > + qemu_irq irq; > +} CadenceTimerState; > + > +#define TYPE_CADENCE_TTC "cadence_ttc" > +OBJECT_DECLARE_SIMPLE_TYPE(CadenceTTCState, CADENCE_TTC) > + > +struct CadenceTTCState { > + SysBusDevice parent_obj; > + > + MemoryRegion iomem; > + CadenceTimerState timer[3]; > +}; > + > +#endif > diff --git a/hw/timer/cadence_ttc.c b/hw/timer/cadence_ttc.c > index 64108241ba..e57a0f5f09 100644 > --- a/hw/timer/cadence_ttc.c > +++ b/hw/timer/cadence_ttc.c > @@ -24,6 +24,8 @@ > #include "qemu/timer.h" > #include "qom/object.h" > > +#include "hw/timer/cadence_ttc.h" > + > #ifdef CADENCE_TTC_ERR_DEBUG > #define DB_PRINT(...) do { \ > fprintf(stderr, ": %s: ", __func__); \ > @@ -49,36 +51,6 @@ > #define CLOCK_CTRL_PS_EN 0x00000001 > #define CLOCK_CTRL_PS_V 0x0000001e > > -typedef struct { > - QEMUTimer *timer; > - int freq; > - > - uint32_t reg_clock; > - uint32_t reg_count; > - uint32_t reg_value; > - uint16_t reg_interval; > - uint16_t reg_match[3]; > - uint32_t reg_intr; > - uint32_t reg_intr_en; > - uint32_t reg_event_ctrl; > - uint32_t reg_event; > - > - uint64_t cpu_time; > - unsigned int cpu_time_valid; > - > - qemu_irq irq; > -} CadenceTimerState; > - > -#define TYPE_CADENCE_TTC "cadence_ttc" > -OBJECT_DECLARE_SIMPLE_TYPE(CadenceTTCState, CADENCE_TTC) > - > -struct CadenceTTCState { > - SysBusDevice parent_obj; > - > - MemoryRegion iomem; > - CadenceTimerState timer[3]; > -}; > - > static void cadence_timer_update(CadenceTimerState *s) > { > qemu_set_irq(s->irq, !!(s->reg_intr & s->reg_intr_en)); > -- > 2.25.1 >