From: Jonathan Cameron via <qemu-devel@nongnu.org>
To: Tong Zhang <t.zhang2@samsung.com>
Cc: "linuxarm@huawei.com" <linuxarm@huawei.com>,
"qemu-devel@nongnu.org" <qemu-devel@nongnu.org>,
"Alex Bennée" <alex.bennee@linaro.org>,
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"Mark Cave-Ayland" <mark.cave-ayland@ilande.co.uk>,
"Adam Manzanares" <a.manzanares@samsung.com>,
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"Ben Widawsky" <ben.widawsky@intel.com>,
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"Shameerali Kolothum Thodi"
<shameerali.kolothum.thodi@huawei.com>,
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Subject: Re: [PATCH v9 33/45] cxl/cxl-host: Add memops for CFMWS region.
Date: Fri, 8 Apr 2022 12:49:01 +0100 [thread overview]
Message-ID: <20220408124901.00007ced@Huawei.com> (raw)
In-Reply-To: <7a17a19d-dcd4-61d5-b699-7ba06c9600bd@samsung.com>
On Thu, 7 Apr 2022 21:07:06 +0000
Tong Zhang <t.zhang2@samsung.com> wrote:
> On 4/4/22 08:14, Jonathan Cameron wrote:
> > From: Jonathan Cameron <jonathan.cameron@huawei.com>
> >
> >
> > +static MemTxResult cxl_read_cfmws(void *opaque, hwaddr addr, uint64_t *data,
> > + unsigned size, MemTxAttrs attrs)
> > +{
> > + CXLFixedWindow *fw = opaque;
> > + PCIDevice *d;
> > +
> > + d = cxl_cfmws_find_device(fw, addr);
> > + if (d == NULL) {
> > + *data = 0;
>
> I'm looking at this code and comparing it to CXL2.0 spec 8.2.5.12.2 CXL HDM
>
> Decoder Global Control Register (Offset 04h) table. It seems that we should
>
> check POSION_ON_ERR_EN bit, if this bit is set, we return poison, otherwise
>
> should return all 1's data.
Good point. Takes a bit of searching to find the statements on that, but
it should indeed by all 1s not all 0s. I'll fix that up.
>
> Also, from the spec, this bit is implementation specific and hard
> wired(RO) to either 1 or 0,
My temptation is to set that to 0 and not return poison, because the handling
of that in the host is horribly implementation specific.
>
> but for type3 device looks like we are currently allowing it to be
> overwritten in ct3d_reg_write()
>
> function. We probably also need more sanitation in ct3d_reg_write. (Also
> for HDM
>
> range/interleaving settings.)
Absolutely agree. Generally my plan was to tighten up write restrictions
as a follow on series because it tends to require quite a lot of code and
makes it much harder to see the overall flow.
So far I've done most of the PCI config space santization (see the gitlab
tree) but not much yet on the memory mapped register space.
I'll add it to the todo list. If it turns out this particular case is
reasonably clean I might add it within this series.
Jonathan
>
> > + /* Reads to invalid address return poison */
> > + return MEMTX_ERROR;
> > + }
> > +
> > + return cxl_type3_read(d, addr + fw->base, data, size, attrs);
> > +}
> > +
>
> - Tong
>
next prev parent reply other threads:[~2022-04-08 11:51 UTC|newest]
Thread overview: 51+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-04-04 15:14 [PATCH v9 00/45] CXl 2.0 emulation Support Jonathan Cameron via
2022-04-04 15:14 ` [PATCH v9 01/45] hw/pci/cxl: Add a CXL component type (interface) Jonathan Cameron via
2022-04-04 15:14 ` [PATCH v9 02/45] hw/cxl/component: Introduce CXL components (8.1.x, 8.2.5) Jonathan Cameron via
2022-04-04 15:14 ` [PATCH v9 03/45] MAINTAINERS: Add entry for Compute Express Link Emulation Jonathan Cameron via
2022-04-04 15:14 ` [PATCH v9 04/45] hw/cxl/device: Introduce a CXL device (8.2.8) Jonathan Cameron via
2022-04-04 15:14 ` [PATCH v9 05/45] hw/cxl/device: Implement the CAP array (8.2.8.1-2) Jonathan Cameron via
2022-04-04 15:14 ` [PATCH v9 06/45] hw/cxl/device: Implement basic mailbox (8.2.8.4) Jonathan Cameron via
2022-04-04 15:14 ` [PATCH v9 07/45] hw/cxl/device: Add memory device utilities Jonathan Cameron via
2022-04-04 15:14 ` [PATCH v9 08/45] hw/cxl/device: Add cheap EVENTS implementation (8.2.9.1) Jonathan Cameron via
2022-04-04 15:14 ` [PATCH v9 09/45] hw/cxl/device: Timestamp implementation (8.2.9.3) Jonathan Cameron via
2022-04-04 15:14 ` [PATCH v9 10/45] hw/cxl/device: Add log commands (8.2.9.4) + CEL Jonathan Cameron via
2022-04-04 15:14 ` [PATCH v9 11/45] hw/pxb: Use a type for realizing expanders Jonathan Cameron via
2022-04-04 15:14 ` [PATCH v9 12/45] hw/pci/cxl: Create a CXL bus type Jonathan Cameron via
2022-04-04 15:14 ` [PATCH v9 13/45] cxl: Machine level control on whether CXL support is enabled Jonathan Cameron via
2022-04-04 15:14 ` [PATCH v9 14/45] hw/pxb: Allow creation of a CXL PXB (host bridge) Jonathan Cameron via
2022-04-04 15:14 ` [PATCH v9 15/45] qtest/cxl: Introduce initial test for pxb-cxl only Jonathan Cameron via
2022-04-04 15:14 ` [PATCH v9 16/45] hw/cxl/rp: Add a root port Jonathan Cameron via
2022-04-04 15:14 ` [PATCH v9 17/45] hw/cxl/device: Add a memory device (8.2.8.5) Jonathan Cameron via
2022-04-04 15:14 ` [PATCH v9 18/45] hw/cxl/device: Implement MMIO HDM decoding (8.2.5.12) Jonathan Cameron via
2022-04-04 19:19 ` Tong Zhang
2022-04-05 8:44 ` Jonathan Cameron via
2022-04-04 15:14 ` [PATCH v9 19/45] hw/cxl/device: Add some trivial commands Jonathan Cameron via
2022-04-04 15:14 ` [PATCH v9 20/45] hw/cxl/device: Plumb real Label Storage Area (LSA) sizing Jonathan Cameron via
2022-04-04 15:14 ` [PATCH v9 21/45] hw/cxl/device: Implement get/set Label Storage Area (LSA) Jonathan Cameron via
2022-04-04 15:14 ` [PATCH v9 22/45] qtests/cxl: Add initial root port and CXL type3 tests Jonathan Cameron via
2022-04-04 15:14 ` [PATCH v9 23/45] hw/cxl/component: Implement host bridge MMIO (8.2.5, table 142) Jonathan Cameron via
2022-04-04 15:14 ` [PATCH v9 24/45] acpi/cxl: Add _OSC implementation (9.14.2) Jonathan Cameron via
2022-04-04 15:14 ` [PATCH v9 25/45] acpi/cxl: Create the CEDT (9.14.1) Jonathan Cameron via
2022-04-04 15:14 ` [PATCH v9 26/45] hw/cxl/component: Add utils for interleave parameter encoding/decoding Jonathan Cameron via
2022-04-04 15:14 ` [PATCH v9 27/45] hw/cxl/host: Add support for CXL Fixed Memory Windows Jonathan Cameron via
2022-04-05 13:41 ` Markus Armbruster
2022-04-04 15:14 ` [PATCH v9 28/45] acpi/cxl: Introduce CFMWS structures in CEDT Jonathan Cameron via
2022-04-04 15:14 ` [PATCH v9 29/45] hw/pci-host/gpex-acpi: Add support for dsdt construction for pxb-cxl Jonathan Cameron via
2022-04-04 15:14 ` [PATCH v9 30/45] pci/pcie_port: Add pci_find_port_by_pn() Jonathan Cameron via
2022-04-04 15:14 ` [PATCH v9 31/45] CXL/cxl_component: Add cxl_get_hb_cstate() Jonathan Cameron via
2022-04-04 15:14 ` [PATCH v9 32/45] mem/cxl_type3: Add read and write functions for associated hostmem Jonathan Cameron via
2022-04-04 15:14 ` [PATCH v9 33/45] cxl/cxl-host: Add memops for CFMWS region Jonathan Cameron via
2022-04-07 21:07 ` Tong Zhang
2022-04-08 11:49 ` Jonathan Cameron via [this message]
2022-04-04 15:14 ` [PATCH v9 34/45] hw/cxl/component Add a dumb HDM decoder handler Jonathan Cameron via
2022-04-04 15:14 ` [PATCH v9 35/45] i386/pc: Enable CXL fixed memory windows Jonathan Cameron via
2022-04-04 15:14 ` [PATCH v9 36/45] tests/acpi: q35: Allow addition of a CXL test Jonathan Cameron via
2022-04-04 15:14 ` [PATCH v9 37/45] qtests/bios-tables-test: Add a test for CXL emulation Jonathan Cameron via
2022-04-04 15:14 ` [PATCH v9 38/45] tests/acpi: Add tables " Jonathan Cameron via
2022-04-04 15:14 ` [PATCH v9 39/45] qtest/cxl: Add more complex test cases with CFMWs Jonathan Cameron via
2022-04-04 15:14 ` [PATCH v9 40/45] hw/arm/virt: Basic CXL enablement on pci_expander_bridge instances pxb-cxl Jonathan Cameron via
2022-04-04 15:14 ` [PATCH v9 41/45] qtest/cxl: Add aarch64 virt test for CXL Jonathan Cameron via
2022-04-04 15:14 ` [PATCH v9 42/45] docs/cxl: Add initial Compute eXpress Link (CXL) documentation Jonathan Cameron via
2022-04-04 15:14 ` [PATCH v9 43/45] pci-bridge/cxl_upstream: Add a CXL switch upstream port Jonathan Cameron via
2022-04-04 15:14 ` [PATCH v9 44/45] pci-bridge/cxl_downstream: Add a CXL switch downstream port Jonathan Cameron via
2022-04-04 15:14 ` [PATCH v9 45/45] docs/cxl: Add switch documentation Jonathan Cameron via
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