From: Gavin Shan <gshan@redhat.com>
To: qemu-arm@nongnu.org
Cc: peter.maydell@linaro.org, drjones@redhat.com,
richard.henderson@linaro.org, qemu-devel@nongnu.org,
eric.auger@redhat.com, agraf@csgraf.de, shan.gavin@gmail.com,
pbonzini@redhat.com
Subject: [PATCH 2/5] target/arm/hvf: Indirect addressing for coprocessor register storage
Date: Mon, 11 Apr 2022 14:58:39 +0800 [thread overview]
Message-ID: <20220411065842.63880-3-gshan@redhat.com> (raw)
In-Reply-To: <20220411065842.63880-1-gshan@redhat.com>
Similar to what we did for TCG, this uses @cpreg_value_indexes[] to
track the storage space for the corresponding coprocessor register.
As all coprocessor register have fixed 8 bytes storage space, so
the indirect and direct addressing mechanisms can co-exist and
interchangeable, even in migration circumstance.
Signed-off-by: Gavin Shan <gshan@redhat.com>
---
target/arm/hvf/hvf.c | 20 +++++++++++++++++---
1 file changed, 17 insertions(+), 3 deletions(-)
diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c
index 8c34f86792..8cca26a59c 100644
--- a/target/arm/hvf/hvf.c
+++ b/target/arm/hvf/hvf.c
@@ -334,6 +334,7 @@ int hvf_get_registers(CPUState *cpu)
ARMCPU *arm_cpu = ARM_CPU(cpu);
CPUARMState *env = &arm_cpu->env;
hv_return_t ret;
+ uint32_t value_index;
uint64_t val;
hv_simd_fp_uchar16_t fpval;
int i;
@@ -373,7 +374,8 @@ int hvf_get_registers(CPUState *cpu)
ret = hv_vcpu_get_sys_reg(cpu->hvf->fd, hvf_sreg_match[i].reg, &val);
assert_hvf_ok(ret);
- arm_cpu->cpreg_values[hvf_sreg_match[i].cp_idx] = val;
+ value_index = arm_cpu->cpreg_value_indexes[hvf_sreg_match[i].cp_idx];
+ arm_cpu->cpreg_values[value_index] = val;
}
assert(write_list_to_cpustate(arm_cpu));
@@ -387,6 +389,7 @@ int hvf_put_registers(CPUState *cpu)
ARMCPU *arm_cpu = ARM_CPU(cpu);
CPUARMState *env = &arm_cpu->env;
hv_return_t ret;
+ uint32_t value_index;
uint64_t val;
hv_simd_fp_uchar16_t fpval;
int i;
@@ -421,7 +424,8 @@ int hvf_put_registers(CPUState *cpu)
continue;
}
- val = arm_cpu->cpreg_values[hvf_sreg_match[i].cp_idx];
+ value_index = arm_cpu->cpreg_value_indexes[hvf_sreg_match[i].cp_idx];
+ val = arm_cpu->cpreg_values[value_index];
ret = hv_vcpu_set_sys_reg(cpu->hvf->fd, hvf_sreg_match[i].reg, val);
assert_hvf_ok(ret);
}
@@ -573,12 +577,18 @@ int hvf_arch_init_vcpu(CPUState *cpu)
sregs_match_len);
arm_cpu->cpreg_values = g_renew(uint64_t, arm_cpu->cpreg_values,
sregs_match_len);
+ arm_cpu->cpreg_value_indexes =
+ g_renew(uint32_t, arm_cpu->cpreg_value_indexes,
+ sregs_match_len);
arm_cpu->cpreg_vmstate_indexes = g_renew(uint64_t,
arm_cpu->cpreg_vmstate_indexes,
sregs_match_len);
arm_cpu->cpreg_vmstate_values = g_renew(uint64_t,
arm_cpu->cpreg_vmstate_values,
sregs_match_len);
+ arm_cpu->cpreg_vmstate_value_indexes =
+ g_renew(uint32_t, arm_cpu->cpreg_vmstate_value_indexes,
+ sregs_match_len);
memset(arm_cpu->cpreg_values, 0, sregs_match_len * sizeof(uint64_t));
@@ -591,13 +601,17 @@ int hvf_arch_init_vcpu(CPUState *cpu)
if (ri) {
assert(!(ri->type & ARM_CP_NO_RAW));
hvf_sreg_match[i].cp_idx = sregs_cnt;
- arm_cpu->cpreg_indexes[sregs_cnt++] = cpreg_to_kvm_id(key);
+ arm_cpu->cpreg_indexes[sregs_cnt] = cpreg_to_kvm_id(key);
+ arm_cpu->cpreg_value_indexes[sregs_cnt] = sregs_cnt;
+ sregs_cnt++;
} else {
hvf_sreg_match[i].cp_idx = -1;
}
}
arm_cpu->cpreg_array_len = sregs_cnt;
+ arm_cpu->cpreg_value_array_len = sregs_cnt;
arm_cpu->cpreg_vmstate_array_len = sregs_cnt;
+ arm_cpu->cpreg_vmstate_value_array_len = sregs_cnt;
assert(write_cpustate_to_list(arm_cpu, false));
--
2.23.0
next prev parent reply other threads:[~2022-04-11 7:09 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-04-11 6:58 [PATCH 0/5] target/arm: Support variable sized coprocessor registers Gavin Shan
2022-04-11 6:58 ` [PATCH 1/5] target/arm/tcg: Indirect addressing for coprocessor register storage Gavin Shan
2022-04-11 6:58 ` Gavin Shan [this message]
2022-04-11 6:58 ` [PATCH 3/5] target/arm/kvm: " Gavin Shan
2022-04-11 6:58 ` [PATCH 4/5] target/arm: Migrate coprocessor register indirect addressing information Gavin Shan
2022-04-11 6:58 ` [PATCH 5/5] target/arm/kvm: Support coprocessor register with variable size Gavin Shan
2022-04-11 9:22 ` [PATCH 0/5] target/arm: Support variable sized coprocessor registers Peter Maydell
2022-04-11 9:49 ` Gavin Shan
2022-04-11 10:05 ` Peter Maydell
2022-04-12 1:54 ` Gavin Shan
2022-04-11 12:02 ` Andrew Jones
2022-04-11 12:10 ` Peter Maydell
2022-04-13 2:55 ` Gavin Shan
2022-04-12 2:08 ` Gavin Shan
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