From: Gavin Shan <gshan@redhat.com>
To: qemu-arm@nongnu.org
Cc: peter.maydell@linaro.org, drjones@redhat.com,
richard.henderson@linaro.org, qemu-devel@nongnu.org,
eric.auger@redhat.com, agraf@csgraf.de, shan.gavin@gmail.com,
pbonzini@redhat.com
Subject: [PATCH 5/5] target/arm/kvm: Support coprocessor register with variable size
Date: Mon, 11 Apr 2022 14:58:42 +0800 [thread overview]
Message-ID: <20220411065842.63880-6-gshan@redhat.com> (raw)
In-Reply-To: <20220411065842.63880-1-gshan@redhat.com>
With the indirect addressing mechanism, we can support large-sized
coprocessor registers. This calculates the length of @cpreg_values
and allocate the storage space accordingly. @cpreg_value_indexes
is also initialized according to the coprocessor register size.
For those registers whose sizes are less than 8 bytes, we always
reserve 8 bytes storage space for it, to gurantee the storage
space address is aligned to 8 bytes. On the other hand, the storage
space size for other registers are allocated based on their sizes.
Signed-off-by: Gavin Shan <gshan@redhat.com>
---
target/arm/kvm.c | 55 ++++++++++++++++++++++++++++++++++++++++++++++--
1 file changed, 53 insertions(+), 2 deletions(-)
diff --git a/target/arm/kvm.c b/target/arm/kvm.c
index 5d1ce431b0..71f602fd81 100644
--- a/target/arm/kvm.c
+++ b/target/arm/kvm.c
@@ -471,8 +471,18 @@ int kvm_arm_init_cpreg_list(ARMCPU *cpu)
continue;
}
switch (rlp->reg[i] & KVM_REG_SIZE_MASK) {
+ case KVM_REG_SIZE_U8:
+ case KVM_REG_SIZE_U16:
case KVM_REG_SIZE_U32:
+ value_arraylen++;
+ break;
case KVM_REG_SIZE_U64:
+ case KVM_REG_SIZE_U128:
+ case KVM_REG_SIZE_U256:
+ case KVM_REG_SIZE_U512:
+ case KVM_REG_SIZE_U1024:
+ case KVM_REG_SIZE_U2048:
+ value_arraylen += KVM_REG_SIZE(rlp->reg[i]) / sizeof(uint64_t);
break;
default:
fprintf(stderr, "Can't handle size of register in kernel list\n");
@@ -481,7 +491,6 @@ int kvm_arm_init_cpreg_list(ARMCPU *cpu)
}
arraylen++;
- value_arraylen++;
}
cpu->cpreg_indexes = g_renew(uint64_t, cpu->cpreg_indexes, arraylen);
@@ -507,7 +516,13 @@ int kvm_arm_init_cpreg_list(ARMCPU *cpu)
cpu->cpreg_indexes[arraylen] = regidx;
cpu->cpreg_value_indexes[arraylen] = value_arraylen;
arraylen++;
- value_arraylen++;
+
+ /* We validate the size just now and no need to do it again */
+ if (KVM_REG_SIZE(rlp->reg[i]) < sizeof(uint64_t)) {
+ value_arraylen++;
+ } else {
+ value_arraylen += KVM_REG_SIZE(rlp->reg[i]) / sizeof(uint64_t);
+ }
}
assert(cpu->cpreg_array_len == arraylen);
assert(cpu->cpreg_value_array_len == value_arraylen);
@@ -535,12 +550,28 @@ bool write_kvmstate_to_list(ARMCPU *cpu)
for (i = 0; i < cpu->cpreg_array_len; i++) {
struct kvm_one_reg r;
uint64_t regidx = cpu->cpreg_indexes[i];
+ uint8_t v8;
+ uint16_t v16;
uint32_t v32;
int ret;
r.id = regidx;
switch (regidx & KVM_REG_SIZE_MASK) {
+ case KVM_REG_SIZE_U8:
+ r.addr = (uintptr_t)&v8;
+ ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r);
+ if (!ret) {
+ cpu->cpreg_values[cpu->cpreg_value_indexes[i]] = v8;
+ }
+ break;
+ case KVM_REG_SIZE_U16:
+ r.addr = (uintptr_t)&v16;
+ ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r);
+ if (!ret) {
+ cpu->cpreg_values[cpu->cpreg_value_indexes[i]] = v16;
+ }
+ break;
case KVM_REG_SIZE_U32:
r.addr = (uintptr_t)&v32;
ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r);
@@ -549,6 +580,11 @@ bool write_kvmstate_to_list(ARMCPU *cpu)
}
break;
case KVM_REG_SIZE_U64:
+ case KVM_REG_SIZE_U128:
+ case KVM_REG_SIZE_U256:
+ case KVM_REG_SIZE_U512:
+ case KVM_REG_SIZE_U1024:
+ case KVM_REG_SIZE_U2048:
r.addr = (uintptr_t)(cpu->cpreg_values +
cpu->cpreg_value_indexes[i]);
ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r);
@@ -572,6 +608,8 @@ bool write_list_to_kvmstate(ARMCPU *cpu, int level)
for (i = 0; i < cpu->cpreg_array_len; i++) {
struct kvm_one_reg r;
uint64_t regidx = cpu->cpreg_indexes[i];
+ uint8_t v8;
+ uint16_t v16;
uint32_t v32;
int ret;
@@ -581,11 +619,24 @@ bool write_list_to_kvmstate(ARMCPU *cpu, int level)
r.id = regidx;
switch (regidx & KVM_REG_SIZE_MASK) {
+ case KVM_REG_SIZE_U8:
+ v8 = cpu->cpreg_values[cpu->cpreg_value_indexes[i]];
+ r.addr = (uintptr_t)&v8;
+ break;
+ case KVM_REG_SIZE_U16:
+ v16 = cpu->cpreg_values[cpu->cpreg_value_indexes[i]];
+ r.addr = (uintptr_t)&v16;
+ break;
case KVM_REG_SIZE_U32:
v32 = cpu->cpreg_values[cpu->cpreg_value_indexes[i]];
r.addr = (uintptr_t)&v32;
break;
case KVM_REG_SIZE_U64:
+ case KVM_REG_SIZE_U128:
+ case KVM_REG_SIZE_U256:
+ case KVM_REG_SIZE_U512:
+ case KVM_REG_SIZE_U1024:
+ case KVM_REG_SIZE_U2048:
r.addr = (uintptr_t)(cpu->cpreg_values +
cpu->cpreg_value_indexes[i]);
break;
--
2.23.0
next prev parent reply other threads:[~2022-04-11 7:18 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-04-11 6:58 [PATCH 0/5] target/arm: Support variable sized coprocessor registers Gavin Shan
2022-04-11 6:58 ` [PATCH 1/5] target/arm/tcg: Indirect addressing for coprocessor register storage Gavin Shan
2022-04-11 6:58 ` [PATCH 2/5] target/arm/hvf: " Gavin Shan
2022-04-11 6:58 ` [PATCH 3/5] target/arm/kvm: " Gavin Shan
2022-04-11 6:58 ` [PATCH 4/5] target/arm: Migrate coprocessor register indirect addressing information Gavin Shan
2022-04-11 6:58 ` Gavin Shan [this message]
2022-04-11 9:22 ` [PATCH 0/5] target/arm: Support variable sized coprocessor registers Peter Maydell
2022-04-11 9:49 ` Gavin Shan
2022-04-11 10:05 ` Peter Maydell
2022-04-12 1:54 ` Gavin Shan
2022-04-11 12:02 ` Andrew Jones
2022-04-11 12:10 ` Peter Maydell
2022-04-13 2:55 ` Gavin Shan
2022-04-12 2:08 ` Gavin Shan
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