From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: qemu-arm@nongnu.org
Subject: [PATCH v2 06/24] target/arm: Split out arm32_max_features
Date: Mon, 11 Apr 2022 17:33:08 -0700 [thread overview]
Message-ID: <20220412003326.588530-7-richard.henderson@linaro.org> (raw)
In-Reply-To: <20220412003326.588530-1-richard.henderson@linaro.org>
Share the code to set AArch32 max features so that we no
longer have code drift between qemu{-system,}-{arm,aarch64}.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/internals.h | 2 +
target/arm/cpu64.c | 50 +-----------------
target/arm/cpu_tcg.c | 114 ++++++++++++++++++++++-------------------
3 files changed, 65 insertions(+), 101 deletions(-)
diff --git a/target/arm/internals.h b/target/arm/internals.h
index 96a57ee68f..ca9782b9f0 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -1301,4 +1301,6 @@ static inline void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu) { }
void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu);
#endif
+void arm32_max_features(ARMCPU *cpu);
+
#endif
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 67d628c0af..528b0f5e64 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -682,7 +682,6 @@ static void aarch64_max_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
uint64_t t;
- uint32_t u;
if (kvm_enabled() || hvf_enabled()) {
/* With KVM or HVF, '-cpu max' is identical to '-cpu host' */
@@ -797,57 +796,12 @@ static void aarch64_max_initfn(Object *obj)
t = FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1);
cpu->isar.id_aa64zfr0 = t;
- /* Replicate the same data to the 32-bit id registers. */
- u = cpu->isar.id_isar5;
- u = FIELD_DP32(u, ID_ISAR5, AES, 2); /* AES + PMULL */
- u = FIELD_DP32(u, ID_ISAR5, SHA1, 1);
- u = FIELD_DP32(u, ID_ISAR5, SHA2, 1);
- u = FIELD_DP32(u, ID_ISAR5, CRC32, 1);
- u = FIELD_DP32(u, ID_ISAR5, RDM, 1);
- u = FIELD_DP32(u, ID_ISAR5, VCMA, 1);
- cpu->isar.id_isar5 = u;
-
- u = cpu->isar.id_isar6;
- u = FIELD_DP32(u, ID_ISAR6, JSCVT, 1);
- u = FIELD_DP32(u, ID_ISAR6, DP, 1);
- u = FIELD_DP32(u, ID_ISAR6, FHM, 1);
- u = FIELD_DP32(u, ID_ISAR6, SB, 1);
- u = FIELD_DP32(u, ID_ISAR6, SPECRES, 1);
- u = FIELD_DP32(u, ID_ISAR6, BF16, 1);
- u = FIELD_DP32(u, ID_ISAR6, I8MM, 1);
- cpu->isar.id_isar6 = u;
-
- u = cpu->isar.id_pfr0;
- u = FIELD_DP32(u, ID_PFR0, DIT, 1);
- cpu->isar.id_pfr0 = u;
-
- u = cpu->isar.id_pfr2;
- u = FIELD_DP32(u, ID_PFR2, SSBS, 1);
- cpu->isar.id_pfr2 = u;
-
- u = cpu->isar.id_mmfr3;
- u = FIELD_DP32(u, ID_MMFR3, PAN, 2); /* ATS1E1 */
- cpu->isar.id_mmfr3 = u;
-
- u = cpu->isar.id_mmfr4;
- u = FIELD_DP32(u, ID_MMFR4, HPDS, 1); /* AA32HPD */
- u = FIELD_DP32(u, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
- u = FIELD_DP32(u, ID_MMFR4, CNP, 1); /* TTCNP */
- u = FIELD_DP32(u, ID_MMFR4, XNX, 1); /* TTS2UXN */
- cpu->isar.id_mmfr4 = u;
-
t = cpu->isar.id_aa64dfr0;
t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* v8.4-PMU */
cpu->isar.id_aa64dfr0 = t;
- u = cpu->isar.id_dfr0;
- u = FIELD_DP32(u, ID_DFR0, PERFMON, 5); /* v8.4-PMU */
- cpu->isar.id_dfr0 = u;
-
- u = cpu->isar.mvfr1;
- u = FIELD_DP32(u, MVFR1, FPHP, 3); /* v8.2-FP16 */
- u = FIELD_DP32(u, MVFR1, SIMDHP, 2); /* v8.2-FP16 */
- cpu->isar.mvfr1 = u;
+ /* Replicate the same data to the 32-bit id registers. */
+ arm32_max_features(cpu);
#ifdef CONFIG_USER_ONLY
/*
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
index ac782531a7..94af0c3bda 100644
--- a/target/arm/cpu_tcg.c
+++ b/target/arm/cpu_tcg.c
@@ -19,6 +19,66 @@
#include "hw/boards.h"
#endif
+
+/* Share AArch32 -cpu max features with AArch64. */
+void arm32_max_features(ARMCPU *cpu)
+{
+ uint32_t t;
+
+ /* Add additional features supported by QEMU */
+ t = cpu->isar.id_isar5;
+ t = FIELD_DP32(t, ID_ISAR5, AES, 2);
+ t = FIELD_DP32(t, ID_ISAR5, SHA1, 1);
+ t = FIELD_DP32(t, ID_ISAR5, SHA2, 1);
+ t = FIELD_DP32(t, ID_ISAR5, CRC32, 1);
+ t = FIELD_DP32(t, ID_ISAR5, RDM, 1);
+ t = FIELD_DP32(t, ID_ISAR5, VCMA, 1);
+ cpu->isar.id_isar5 = t;
+
+ t = cpu->isar.id_isar6;
+ t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1);
+ t = FIELD_DP32(t, ID_ISAR6, DP, 1);
+ t = FIELD_DP32(t, ID_ISAR6, FHM, 1);
+ t = FIELD_DP32(t, ID_ISAR6, SB, 1);
+ t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1);
+ t = FIELD_DP32(t, ID_ISAR6, BF16, 1);
+ t = FIELD_DP32(t, ID_ISAR6, I8MM, 1);
+ cpu->isar.id_isar6 = t;
+
+ t = cpu->isar.mvfr1;
+ t = FIELD_DP32(t, MVFR1, FPHP, 3); /* v8.2-FP16 */
+ t = FIELD_DP32(t, MVFR1, SIMDHP, 2); /* v8.2-FP16 */
+ cpu->isar.mvfr1 = t;
+
+ t = cpu->isar.mvfr2;
+ t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */
+ t = FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */
+ cpu->isar.mvfr2 = t;
+
+ t = cpu->isar.id_mmfr3;
+ t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */
+ cpu->isar.id_mmfr3 = t;
+
+ t = cpu->isar.id_mmfr4;
+ t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */
+ t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
+ t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */
+ t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */
+ cpu->isar.id_mmfr4 = t;
+
+ t = cpu->isar.id_pfr0;
+ t = FIELD_DP32(t, ID_PFR0, DIT, 1);
+ cpu->isar.id_pfr0 = t;
+
+ t = cpu->isar.id_pfr2;
+ t = FIELD_DP32(t, ID_PFR2, SSBS, 1);
+ cpu->isar.id_pfr2 = t;
+
+ t = cpu->isar.id_dfr0;
+ t = FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* v8.4-PMU */
+ cpu->isar.id_dfr0 = t;
+}
+
#ifndef CONFIG_USER_ONLY
static uint64_t l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
{
@@ -998,7 +1058,6 @@ static void arm_v7m_class_init(ObjectClass *oc, void *data)
static void arm_max_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
- uint32_t t;
/* aarch64_a57_initfn, advertising none of the aarch64 features */
cpu->dtb_compatible = "arm,cortex-a57";
@@ -1039,58 +1098,7 @@ static void arm_max_initfn(Object *obj)
cpu->ccsidr[2] = 0x70ffe07a; /* 2048KB L2 cache */
define_cortex_a72_a57_a53_cp_reginfo(cpu);
- /* Add additional features supported by QEMU */
- t = cpu->isar.id_isar5;
- t = FIELD_DP32(t, ID_ISAR5, AES, 2);
- t = FIELD_DP32(t, ID_ISAR5, SHA1, 1);
- t = FIELD_DP32(t, ID_ISAR5, SHA2, 1);
- t = FIELD_DP32(t, ID_ISAR5, CRC32, 1);
- t = FIELD_DP32(t, ID_ISAR5, RDM, 1);
- t = FIELD_DP32(t, ID_ISAR5, VCMA, 1);
- cpu->isar.id_isar5 = t;
-
- t = cpu->isar.id_isar6;
- t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1);
- t = FIELD_DP32(t, ID_ISAR6, DP, 1);
- t = FIELD_DP32(t, ID_ISAR6, FHM, 1);
- t = FIELD_DP32(t, ID_ISAR6, SB, 1);
- t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1);
- t = FIELD_DP32(t, ID_ISAR6, BF16, 1);
- t = FIELD_DP32(t, ID_ISAR6, I8MM, 1);
- cpu->isar.id_isar6 = t;
-
- t = cpu->isar.mvfr1;
- t = FIELD_DP32(t, MVFR1, FPHP, 3); /* v8.2-FP16 */
- t = FIELD_DP32(t, MVFR1, SIMDHP, 2); /* v8.2-FP16 */
- cpu->isar.mvfr1 = t;
-
- t = cpu->isar.mvfr2;
- t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */
- t = FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */
- cpu->isar.mvfr2 = t;
-
- t = cpu->isar.id_mmfr3;
- t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */
- cpu->isar.id_mmfr3 = t;
-
- t = cpu->isar.id_mmfr4;
- t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */
- t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
- t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */
- t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */
- cpu->isar.id_mmfr4 = t;
-
- t = cpu->isar.id_pfr0;
- t = FIELD_DP32(t, ID_PFR0, DIT, 1);
- cpu->isar.id_pfr0 = t;
-
- t = cpu->isar.id_pfr2;
- t = FIELD_DP32(t, ID_PFR2, SSBS, 1);
- cpu->isar.id_pfr2 = t;
-
- t = cpu->isar.id_dfr0;
- t = FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* v8.4-PMU */
- cpu->isar.id_dfr0 = t;
+ arm32_max_features(cpu);
#ifdef CONFIG_USER_ONLY
/*
--
2.25.1
next prev parent reply other threads:[~2022-04-12 0:40 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-04-12 0:33 [PATCH v2 00/24] target/arm: 8 new features, A76 and N1 Richard Henderson
2022-04-12 0:33 ` [PATCH v2 01/24] target/arm: Add isar predicates for FEAT_Debugv8p2 Richard Henderson
2022-04-12 0:33 ` [PATCH v2 02/24] target/arm: Adjust definition of CONTEXTIDR_EL2 Richard Henderson
2022-04-12 0:33 ` [PATCH v2 03/24] target/arm: Move cortex impdef sysregs to cpu_tcg.c Richard Henderson
2022-04-12 0:33 ` [PATCH v2 04/24] target/arm: Update qemu-system-arm -cpu max to cortex-a57 Richard Henderson
2022-04-12 0:33 ` [PATCH v2 05/24] target/arm: Set ID_DFR0.PerfMon for qemu-system-arm -cpu max Richard Henderson
2022-04-12 0:33 ` Richard Henderson [this message]
2022-04-12 0:33 ` [PATCH v2 07/24] target/arm: Annotate arm_max_initfn with FEAT identifiers Richard Henderson
2022-04-12 0:33 ` [PATCH v2 08/24] target/arm: Use field names for manipulating EL2 and EL3 modes Richard Henderson
2022-04-12 0:33 ` [PATCH v2 09/24] target/arm: Enable FEAT_Debugv8p2 for -cpu max Richard Henderson
2022-04-12 0:33 ` [PATCH v2 10/24] target/arm: Enable FEAT_Debugv8p4 " Richard Henderson
2022-04-12 0:33 ` [PATCH v2 11/24] target/arm: Add isar_feature_{aa64,any}_ras Richard Henderson
2022-04-12 0:33 ` [PATCH v2 12/24] target/arm: Add minimal RAS registers Richard Henderson
2022-04-12 0:33 ` [PATCH v2 13/24] target/arm: Enable SCR and HCR bits for RAS Richard Henderson
2022-04-12 0:33 ` [PATCH v2 14/24] target/arm: Implement virtual SError exceptions Richard Henderson
2022-04-12 0:33 ` [PATCH v2 15/24] target/arm: Implement ESB instruction Richard Henderson
2022-04-12 0:33 ` [PATCH v2 16/24] target/arm: Enable FEAT_RAS for -cpu max Richard Henderson
2022-04-12 0:33 ` [PATCH v2 17/24] target/arm: Enable FEAT_IESB " Richard Henderson
2022-04-12 0:33 ` [PATCH v2 18/24] target/arm: Enable FEAT_CSV2 " Richard Henderson
2022-04-12 0:33 ` [PATCH v2 19/24] target/arm: Update ISAR fields for ARMv8.8 Richard Henderson
2022-04-12 0:33 ` [PATCH v2 20/24] target/arm: Enable FEAT_CSV2_2 for -cpu max Richard Henderson
2022-04-12 0:33 ` [PATCH v2 21/24] target/arm: Enable FEAT_CSV3 " Richard Henderson
2022-04-12 0:33 ` [PATCH v2 22/24] target/arm: Enable FEAT_DGH " Richard Henderson
2022-04-12 0:33 ` [PATCH v2 23/24] target/arm: Define cortex-a76 Richard Henderson
2022-04-12 0:33 ` [PATCH v2 24/24] target/arm: Define neoverse-n1 Richard Henderson
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