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From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: Peter Maydell <peter.maydell@linaro.org>, qemu-arm@nongnu.org
Subject: [PATCH v2 08/24] target/arm: Use field names for manipulating EL2 and EL3 modes
Date: Mon, 11 Apr 2022 17:33:10 -0700	[thread overview]
Message-ID: <20220412003326.588530-9-richard.henderson@linaro.org> (raw)
In-Reply-To: <20220412003326.588530-1-richard.henderson@linaro.org>

Use FIELD_DP{32,64} to manipulate id_pfr1 and id_aa64pfr0
during arm_cpu_realizefn.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/arm/cpu.c | 22 +++++++++++++---------
 1 file changed, 13 insertions(+), 9 deletions(-)

diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 5d4ca7a227..6521f350f9 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -1795,11 +1795,13 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
          */
         unset_feature(env, ARM_FEATURE_EL3);
 
-        /* Disable the security extension feature bits in the processor feature
-         * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12].
+        /*
+         * Disable the security extension feature bits in the processor
+         * feature registers as well.
          */
-        cpu->isar.id_pfr1 &= ~0xf0;
-        cpu->isar.id_aa64pfr0 &= ~0xf000;
+        cpu->isar.id_pfr1 = FIELD_DP32(cpu->isar.id_pfr1, ID_PFR1, SECURITY, 0);
+        cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0,
+                                           ID_AA64PFR0, EL3, 0);
     }
 
     if (!cpu->has_el2) {
@@ -1830,12 +1832,14 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
     }
 
     if (!arm_feature(env, ARM_FEATURE_EL2)) {
-        /* Disable the hypervisor feature bits in the processor feature
-         * registers if we don't have EL2. These are id_pfr1[15:12] and
-         * id_aa64pfr0_el1[11:8].
+        /*
+         * Disable the hypervisor feature bits in the processor feature
+         * registers if we don't have EL2.
          */
-        cpu->isar.id_aa64pfr0 &= ~0xf00;
-        cpu->isar.id_pfr1 &= ~0xf000;
+        cpu->isar.id_aa64pfr0 = FIELD_DP64(cpu->isar.id_aa64pfr0,
+                                           ID_AA64PFR0, EL2, 0);
+        cpu->isar.id_pfr1 = FIELD_DP32(cpu->isar.id_pfr1,
+                                       ID_PFR1, VIRTUALIZATION, 0);
     }
 
 #ifndef CONFIG_USER_ONLY
-- 
2.25.1



  parent reply	other threads:[~2022-04-12  0:44 UTC|newest]

Thread overview: 25+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-04-12  0:33 [PATCH v2 00/24] target/arm: 8 new features, A76 and N1 Richard Henderson
2022-04-12  0:33 ` [PATCH v2 01/24] target/arm: Add isar predicates for FEAT_Debugv8p2 Richard Henderson
2022-04-12  0:33 ` [PATCH v2 02/24] target/arm: Adjust definition of CONTEXTIDR_EL2 Richard Henderson
2022-04-12  0:33 ` [PATCH v2 03/24] target/arm: Move cortex impdef sysregs to cpu_tcg.c Richard Henderson
2022-04-12  0:33 ` [PATCH v2 04/24] target/arm: Update qemu-system-arm -cpu max to cortex-a57 Richard Henderson
2022-04-12  0:33 ` [PATCH v2 05/24] target/arm: Set ID_DFR0.PerfMon for qemu-system-arm -cpu max Richard Henderson
2022-04-12  0:33 ` [PATCH v2 06/24] target/arm: Split out arm32_max_features Richard Henderson
2022-04-12  0:33 ` [PATCH v2 07/24] target/arm: Annotate arm_max_initfn with FEAT identifiers Richard Henderson
2022-04-12  0:33 ` Richard Henderson [this message]
2022-04-12  0:33 ` [PATCH v2 09/24] target/arm: Enable FEAT_Debugv8p2 for -cpu max Richard Henderson
2022-04-12  0:33 ` [PATCH v2 10/24] target/arm: Enable FEAT_Debugv8p4 " Richard Henderson
2022-04-12  0:33 ` [PATCH v2 11/24] target/arm: Add isar_feature_{aa64,any}_ras Richard Henderson
2022-04-12  0:33 ` [PATCH v2 12/24] target/arm: Add minimal RAS registers Richard Henderson
2022-04-12  0:33 ` [PATCH v2 13/24] target/arm: Enable SCR and HCR bits for RAS Richard Henderson
2022-04-12  0:33 ` [PATCH v2 14/24] target/arm: Implement virtual SError exceptions Richard Henderson
2022-04-12  0:33 ` [PATCH v2 15/24] target/arm: Implement ESB instruction Richard Henderson
2022-04-12  0:33 ` [PATCH v2 16/24] target/arm: Enable FEAT_RAS for -cpu max Richard Henderson
2022-04-12  0:33 ` [PATCH v2 17/24] target/arm: Enable FEAT_IESB " Richard Henderson
2022-04-12  0:33 ` [PATCH v2 18/24] target/arm: Enable FEAT_CSV2 " Richard Henderson
2022-04-12  0:33 ` [PATCH v2 19/24] target/arm: Update ISAR fields for ARMv8.8 Richard Henderson
2022-04-12  0:33 ` [PATCH v2 20/24] target/arm: Enable FEAT_CSV2_2 for -cpu max Richard Henderson
2022-04-12  0:33 ` [PATCH v2 21/24] target/arm: Enable FEAT_CSV3 " Richard Henderson
2022-04-12  0:33 ` [PATCH v2 22/24] target/arm: Enable FEAT_DGH " Richard Henderson
2022-04-12  0:33 ` [PATCH v2 23/24] target/arm: Define cortex-a76 Richard Henderson
2022-04-12  0:33 ` [PATCH v2 24/24] target/arm: Define neoverse-n1 Richard Henderson

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