From: Daniel Henrique Barboza <danielhb413@gmail.com>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, richard.henderson@linaro.org,
danielhb413@gmail.com, qemu-ppc@nongnu.org,
"Cédric Le Goater" <clg@kaod.org>
Subject: [PULL 03/23] ppc/pnv: Fix PSI IRQ definition
Date: Wed, 20 Apr 2022 19:13:09 -0300 [thread overview]
Message-ID: <20220420221329.169755-4-danielhb413@gmail.com> (raw)
In-Reply-To: <20220420221329.169755-1-danielhb413@gmail.com>
From: Cédric Le Goater <clg@kaod.org>
On HW, the PSI and FSP interrupt levels are muxed under the same
interrupt number. For coding reasons, an extra IRQ number was
introduced to index register values in an array. It increased the
count of IRQs which do not fit in the PSI IRQ range anymore.
The PSI and FSP interrupts should be modeled with an extra level of
GPIO lines but since QEMU does not support them, simply drop the extra
number to stay within the IRQ range.
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220323072846.1780212-2-clg@kaod.org>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
---
hw/ppc/pnv_psi.c | 9 +++------
include/hw/ppc/pnv_psi.h | 3 +--
2 files changed, 4 insertions(+), 8 deletions(-)
diff --git a/hw/ppc/pnv_psi.c b/hw/ppc/pnv_psi.c
index 466fb79798..c588a506c7 100644
--- a/hw/ppc/pnv_psi.c
+++ b/hw/ppc/pnv_psi.c
@@ -184,8 +184,7 @@ static void pnv_psi_set_irsn(PnvPsi *psi, uint64_t val)
/*
* FSP and PSI interrupts are muxed under the same number.
*/
-static const uint32_t xivr_regs[] = {
- [PSIHB_IRQ_PSI] = PSIHB_XSCOM_XIVR_FSP,
+static const uint32_t xivr_regs[PSI_NUM_INTERRUPTS] = {
[PSIHB_IRQ_FSP] = PSIHB_XSCOM_XIVR_FSP,
[PSIHB_IRQ_OCC] = PSIHB_XSCOM_XIVR_OCC,
[PSIHB_IRQ_FSI] = PSIHB_XSCOM_XIVR_FSI,
@@ -194,8 +193,7 @@ static const uint32_t xivr_regs[] = {
[PSIHB_IRQ_EXTERNAL] = PSIHB_XSCOM_XIVR_EXT,
};
-static const uint32_t stat_regs[] = {
- [PSIHB_IRQ_PSI] = PSIHB_XSCOM_CR,
+static const uint32_t stat_regs[PSI_NUM_INTERRUPTS] = {
[PSIHB_IRQ_FSP] = PSIHB_XSCOM_CR,
[PSIHB_IRQ_OCC] = PSIHB_XSCOM_IRQ_STAT,
[PSIHB_IRQ_FSI] = PSIHB_XSCOM_IRQ_STAT,
@@ -204,8 +202,7 @@ static const uint32_t stat_regs[] = {
[PSIHB_IRQ_EXTERNAL] = PSIHB_XSCOM_IRQ_STAT,
};
-static const uint64_t stat_bits[] = {
- [PSIHB_IRQ_PSI] = PSIHB_CR_PSI_IRQ,
+static const uint64_t stat_bits[PSI_NUM_INTERRUPTS] = {
[PSIHB_IRQ_FSP] = PSIHB_CR_FSP_IRQ,
[PSIHB_IRQ_OCC] = PSIHB_IRQ_STAT_OCC,
[PSIHB_IRQ_FSI] = PSIHB_IRQ_STAT_FSI,
diff --git a/include/hw/ppc/pnv_psi.h b/include/hw/ppc/pnv_psi.h
index eb841b34a1..6d9f8ce7c0 100644
--- a/include/hw/ppc/pnv_psi.h
+++ b/include/hw/ppc/pnv_psi.h
@@ -1,7 +1,7 @@
/*
* QEMU PowerPC PowerNV Processor Service Interface (PSI) model
*
- * Copyright (c) 2015-2017, IBM Corporation.
+ * Copyright (c) 2015-2022, IBM Corporation.
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
@@ -85,7 +85,6 @@ struct PnvPsiClass {
/* The PSI and FSP interrupts are muxed on the same IRQ number */
typedef enum PnvPsiIrq {
- PSIHB_IRQ_PSI, /* internal use only */
PSIHB_IRQ_FSP, /* internal use only */
PSIHB_IRQ_OCC,
PSIHB_IRQ_FSI,
--
2.35.1
next prev parent reply other threads:[~2022-04-20 22:21 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-04-20 22:13 [PULL 00/23] ppc queue Daniel Henrique Barboza
2022-04-20 22:13 ` [PULL 01/23] ppc/pnv: Update skiboot to v7.0 Daniel Henrique Barboza
2022-04-20 22:13 ` [PULL 02/23] ppc/spapr/ddw: Add 2M pagesize Daniel Henrique Barboza
2022-04-20 22:13 ` Daniel Henrique Barboza [this message]
2022-04-20 22:13 ` [PULL 04/23] ppc/pnv: Remove PnvLpcController::psi link Daniel Henrique Barboza
2022-04-20 22:13 ` [PULL 05/23] ppc/pnv: Remove PnvOCC::psi link Daniel Henrique Barboza
2022-04-20 22:13 ` [PULL 06/23] ppc/pnv: Remove PnvPsiClas::irq_set Daniel Henrique Barboza
2022-04-20 22:13 ` [PULL 07/23] ppc/pnv: Remove useless checks in set_irq handlers Daniel Henrique Barboza
2022-04-20 22:13 ` [PULL 08/23] spapr: Move hypercall_register_softmmu Daniel Henrique Barboza
2022-04-20 22:13 ` [PULL 09/23] spapr: Move nested KVM hypercalls under a TCG only config Daniel Henrique Barboza
2022-04-20 22:13 ` [PULL 10/23] target/ppc: Improve KVM hypercall trace Daniel Henrique Barboza
2022-04-20 22:13 ` [PULL 11/23] qemu/int128: add int128_urshift Daniel Henrique Barboza
2022-04-20 22:13 ` [PULL 12/23] softfloat: add uint128_to_float128 Daniel Henrique Barboza
2022-04-20 22:13 ` [PULL 13/23] softfloat: add int128_to_float128 Daniel Henrique Barboza
2022-04-20 22:13 ` [PULL 14/23] softfloat: add float128_to_uint128 Daniel Henrique Barboza
2022-04-20 22:13 ` [PULL 15/23] softfloat: add float128_to_int128 Daniel Henrique Barboza
2022-04-20 22:13 ` [PULL 16/23] target/ppc: implement xscv[su]qqp Daniel Henrique Barboza
2022-04-20 22:13 ` [PULL 17/23] target/ppc: implement xscvqp[su]qz Daniel Henrique Barboza
2022-04-20 22:13 ` [PULL 18/23] hw/ppc/ppc405_boards: Initialize g_autofree pointer Daniel Henrique Barboza
2022-04-20 22:13 ` [PULL 19/23] ppc/vof: Fix uninitialized string tracing Daniel Henrique Barboza
2022-04-20 22:13 ` [PULL 20/23] pcie: Don't try triggering a LSI when not defined Daniel Henrique Barboza
2022-04-20 22:13 ` [PULL 21/23] ppc/pnv: Remove LSI on the PCIE host bridge Daniel Henrique Barboza
2022-04-20 22:13 ` [PULL 22/23] target/ppc: Add two missing register callbacks on POWER10 Daniel Henrique Barboza
2022-04-20 22:13 ` [PULL 23/23] hw/ppc: change indentation to spaces from TABs Daniel Henrique Barboza
2022-04-21 13:53 ` [PULL 00/23] ppc queue Richard Henderson
2022-04-21 14:21 ` Peter Maydell
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